BR112017024976A2 - sistemas, aparelho e método para embutir um componente 3d com uma estrutura de interligação - Google Patents

sistemas, aparelho e método para embutir um componente 3d com uma estrutura de interligação

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Publication number
BR112017024976A2
BR112017024976A2 BR112017024976A BR112017024976A BR112017024976A2 BR 112017024976 A2 BR112017024976 A2 BR 112017024976A2 BR 112017024976 A BR112017024976 A BR 112017024976A BR 112017024976 A BR112017024976 A BR 112017024976A BR 112017024976 A2 BR112017024976 A2 BR 112017024976A2
Authority
BR
Brazil
Prior art keywords
component
matrix
embedding
systems
substrate
Prior art date
Application number
BR112017024976A
Other languages
English (en)
Inventor
Fraser Rae David
Ann Keser Lizabeth
Tamunan Alvarado Reynante
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112017024976A2 publication Critical patent/BR112017024976A2/pt

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

um pacote incluindo uma matriz (110) próxima a uma estrutura (130) tendo um substrato (131) com interligações (132) e um primeiro componente (133) acoplado às interligações. o substrato é orientado em um ângulo maior do que 10 graus em relação a uma face da matriz. a matriz (110) pode ser virada para cima ou virada para baixo. o pacote inclui uma primeira camada de redistribuição 150 acoplando a matriz às interligações (132) do substrato e um composto de molde (120) cobrindo ao menos parcialmente a matriz (110) e a estrutura (130).
BR112017024976A 2015-05-22 2016-05-19 sistemas, aparelho e método para embutir um componente 3d com uma estrutura de interligação BR112017024976A2 (pt)

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US201562165820P 2015-05-22 2015-05-22
US14/861,484 US10163687B2 (en) 2015-05-22 2015-09-22 System, apparatus, and method for embedding a 3D component with an interconnect structure
PCT/US2016/033261 WO2016191193A1 (en) 2015-05-22 2016-05-19 System, apparatus, and method for embedding a 3d component with an interconnect structure

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WO2016191193A1 (en) 2016-12-01
SG11201708388VA (en) 2017-12-28
CN107636814A (zh) 2018-01-26
US20160343651A1 (en) 2016-11-24
US10163687B2 (en) 2018-12-25
JP2018519657A (ja) 2018-07-19
EP3298625A1 (en) 2018-03-28
KR20180010190A (ko) 2018-01-30

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