BR112012028774A2 - pacote semicondutor empilhado - Google Patents
pacote semicondutor empilhadoInfo
- Publication number
- BR112012028774A2 BR112012028774A2 BR112012028774A BR112012028774A BR112012028774A2 BR 112012028774 A2 BR112012028774 A2 BR 112012028774A2 BR 112012028774 A BR112012028774 A BR 112012028774A BR 112012028774 A BR112012028774 A BR 112012028774A BR 112012028774 A2 BR112012028774 A2 BR 112012028774A2
- Authority
- BR
- Brazil
- Prior art keywords
- semiconductor package
- substrate
- stacked semiconductor
- stacked
- chip
- Prior art date
Links
Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L2924/151—Die mounting substrate
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
pacote semicondutor empilhado. a presente invenção se refere a um pacote semicondutor empilhaod. o pacote semicondutor empilhado da presente invenção compreende: um substrato que inclui pelo menos uma almofada de contacto; um laminado de chip externo que inclui uma pluralidade de chips semicondutores montados sobre o substrato; e que é empilhado em múltiplas etapas de modo que as extremidades em um lado da pluralidade de chips semicondutores se projetam de modo alternado em condições opostas para expor as almofadas de ligação que são formadas sobre a superfície voltada para cima; pelo menos um chip interno que é disposto em um espaço de montagem formado entre o laminaod de chip externo e o substrato de modo a ser conectado de modo elétrico ao subtrato; e um fio condutor que conecta de modo elétrico a almofada de ligada do chip semicondutor e a almofada de contacto do substrato.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR1020100043641A KR20110124065A (ko) | 2010-05-10 | 2010-05-10 | 적층형 반도체 패키지 |
PCT/KR2011/003467 WO2011142581A2 (ko) | 2010-05-10 | 2011-05-11 | 적층형 반도체 패키지 |
Publications (1)
Publication Number | Publication Date |
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BR112012028774A2 true BR112012028774A2 (pt) | 2016-07-19 |
Family
ID=44914815
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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BR112012028774A BR112012028774A2 (pt) | 2010-05-10 | 2011-05-11 | pacote semicondutor empilhado |
Country Status (4)
Country | Link |
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US (1) | US8729688B2 (pt) |
KR (1) | KR20110124065A (pt) |
BR (1) | BR112012028774A2 (pt) |
WO (1) | WO2011142581A2 (pt) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9607971B2 (en) | 2012-06-04 | 2017-03-28 | Sony Corporation | Semiconductor device and sensing system |
KR20140135319A (ko) * | 2013-05-15 | 2014-11-26 | 삼성전자주식회사 | 와이어 본딩 방법 및 이를 이용하여 제조된 반도체 패키지 |
KR102191669B1 (ko) | 2013-08-05 | 2020-12-16 | 삼성전자주식회사 | 멀티-칩 패키지 |
US11171114B2 (en) * | 2015-12-02 | 2021-11-09 | Intel Corporation | Die stack with cascade and vertical connections |
KR102505206B1 (ko) | 2015-12-15 | 2023-03-03 | 삼성전자주식회사 | 반도체 패키지 |
KR102384505B1 (ko) * | 2016-01-12 | 2022-04-08 | 삼성전자주식회사 | 칩 간 무선 통신을 제공하기 위한 방법 및 장치 |
KR102534732B1 (ko) | 2016-06-14 | 2023-05-19 | 삼성전자 주식회사 | 반도체 패키지 |
US10453820B2 (en) * | 2018-02-07 | 2019-10-22 | Micron Technology, Inc. | Semiconductor assemblies using edge stacking and methods of manufacturing the same |
CN108417556A (zh) * | 2018-05-23 | 2018-08-17 | 奥肯思(北京)科技有限公司 | 多芯片堆叠封装结构 |
KR102571267B1 (ko) | 2018-09-19 | 2023-08-29 | 에스케이하이닉스 주식회사 | 부분 중첩 반도체 다이 스택 패키지 |
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US5378927A (en) * | 1993-05-24 | 1995-01-03 | International Business Machines Corporation | Thin-film wiring layout for a non-planar thin-film structure |
JP2001217388A (ja) | 2000-02-01 | 2001-08-10 | Sony Corp | 電子装置およびその製造方法 |
JP3818359B2 (ja) * | 2000-07-18 | 2006-09-06 | セイコーエプソン株式会社 | 半導体装置、回路基板及び電子機器 |
US7021520B2 (en) * | 2001-12-05 | 2006-04-04 | Micron Technology, Inc. | Stacked chip connection using stand off stitch bonding |
KR101166575B1 (ko) | 2002-09-17 | 2012-07-18 | 스태츠 칩팩, 엘티디. | 적층형 패키지들 간 도선연결에 의한 상호연결을 이용한반도체 멀티-패키지 모듈 및 그 제작 방법 |
DE102004049356B4 (de) * | 2004-10-08 | 2006-06-29 | Infineon Technologies Ag | Halbleitermodul mit einem internen Halbleiterchipstapel und Verfahren zur Herstellung desselben |
KR20070009776A (ko) * | 2005-07-14 | 2007-01-19 | 삼성전자주식회사 | 고집적 적층 칩 패키지 |
JP2007059541A (ja) * | 2005-08-23 | 2007-03-08 | Toshiba Corp | 半導体装置及びその組立方法 |
JP2007123454A (ja) | 2005-10-27 | 2007-05-17 | Renesas Technology Corp | 半導体装置及びその製造方法 |
TW200843077A (en) * | 2007-04-27 | 2008-11-01 | En-Min Jow | Package structure of memory |
TW200820402A (en) * | 2006-10-26 | 2008-05-01 | Chipmos Technologies Inc | Stacked chip packaging with heat sink struct |
JP5529371B2 (ja) * | 2007-10-16 | 2014-06-25 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びその製造方法 |
KR101026488B1 (ko) * | 2009-08-10 | 2011-04-01 | 주식회사 하이닉스반도체 | 반도체 패키지 |
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2010
- 2010-05-10 KR KR1020100043641A patent/KR20110124065A/ko not_active Application Discontinuation
-
2011
- 2011-05-11 WO PCT/KR2011/003467 patent/WO2011142581A2/ko active Application Filing
- 2011-05-11 BR BR112012028774A patent/BR112012028774A2/pt not_active IP Right Cessation
- 2011-05-11 US US13/697,266 patent/US8729688B2/en not_active Expired - Fee Related
Also Published As
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WO2011142581A3 (ko) | 2012-03-01 |
US20130127070A1 (en) | 2013-05-23 |
KR20110124065A (ko) | 2011-11-16 |
WO2011142581A2 (ko) | 2011-11-17 |
US8729688B2 (en) | 2014-05-20 |
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