BR0209559A - Arquitetura de buffer para um decodificador turbo - Google Patents

Arquitetura de buffer para um decodificador turbo

Info

Publication number
BR0209559A
BR0209559A BR0209559-9A BR0209559A BR0209559A BR 0209559 A BR0209559 A BR 0209559A BR 0209559 A BR0209559 A BR 0209559A BR 0209559 A BR0209559 A BR 0209559A
Authority
BR
Brazil
Prior art keywords
banks
assigned
buffer
turbo decoder
architecture
Prior art date
Application number
BR0209559-9A
Other languages
English (en)
Inventor
Da-Shan Shiu
Iwen Yao
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR0209559A publication Critical patent/BR0209559A/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2771—Internal interleaver for turbo codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6566—Implementations concerning memory access contentions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0055—MAP-decoding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H04L1/0068—Rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H03M13/2714—Turbo interleaver for 3rd generation partnership project [3GPP] universal mobile telecommunications systems [UMTS], e.g. as defined in technical specification TS 25.212

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

"ARQUITETURA DE BUFFER PARA UM DECODIFICADOR TURBO". Uma arquitetura de buffer ou acumulador para armazenar resultados intermediários (isto é, dados APP) para um decodificador turbo. Para aumentar a capacidade de acesso a arquitetura de buffer é projetada para dar suporte a acesso concomitante de dados APP para dois ou mais bits para cada ciclo de acesso. Tal é obtido pela partição do buffer em um certo número de bancos, com cada banco sendo independentemente acessível. Para evitar conflitos de acesso, os bancos são designados para as filas e colunas de um arranjo bidimensional usado para intercalação de códigos, de tal forma que os dados APP para bits consecutivos sejam acessados a partir de bancos diferentes. Para dar suporte ao endereçamento "linear", os bancos podem ser dispostos em dois conjuntos, os quais são designados para colunas pares e colunas ímpares do arranjo. Para dar suporte ao endereçamento "intercalado", os bancos podem ser designados para grupos de filas do arranjo de tal forma que filas adjacentes no arranjo intercalado sejam designadas para diferentes grupos.
BR0209559-9A 2001-05-11 2002-05-09 Arquitetura de buffer para um decodificador turbo BR0209559A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/854,278 US6392572B1 (en) 2001-05-11 2001-05-11 Buffer architecture for a turbo decoder
PCT/US2002/015006 WO2002093755A1 (en) 2001-05-11 2002-05-09 Buffer architecture for a turbo decoder

Publications (1)

Publication Number Publication Date
BR0209559A true BR0209559A (pt) 2004-06-15

Family

ID=25318231

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0209559-9A BR0209559A (pt) 2001-05-11 2002-05-09 Arquitetura de buffer para um decodificador turbo

Country Status (8)

Country Link
US (1) US6392572B1 (pt)
EP (1) EP1388213A1 (pt)
JP (1) JP3996514B2 (pt)
KR (1) KR100963718B1 (pt)
CN (2) CN100426680C (pt)
BR (1) BR0209559A (pt)
TW (1) TW543303B (pt)
WO (1) WO2002093755A1 (pt)

Families Citing this family (95)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
PL207275B1 (pl) 1999-07-08 2010-11-30 Samsung Electronics Co Ltd Urządzenie nadawcze dla łącza w górę w systemie łączności ruchomej, urządzenie nadawcze w systemie łączności ruchomej oraz sposób nadawania w systemie łączności ruchomej
US6734962B2 (en) * 2000-10-13 2004-05-11 Chemimage Corporation Near infrared chemical imaging microscope
AU4710501A (en) * 1999-12-03 2001-06-18 Broadcom Corporation Interspersed training for turbo coded modulation
JP2001352254A (ja) * 2000-06-08 2001-12-21 Sony Corp 復号装置及び復号方法
EP2293452B1 (en) * 2000-07-05 2012-06-06 LG ELectronics INC. Method of puncturing a turbo coded data block
US7178089B1 (en) * 2000-08-23 2007-02-13 Telefonaktiebolaget Lm Ericsson (Publ) Two stage date packet processing scheme
US6604220B1 (en) * 2000-09-28 2003-08-05 Western Digital Technologies, Inc. Disk drive comprising a multiple-input sequence detector selectively biased by bits of a decoded ECC codedword
US7187708B1 (en) * 2000-10-03 2007-03-06 Qualcomm Inc. Data buffer structure for physical and transport channels in a CDMA system
KR100628201B1 (ko) * 2000-10-16 2006-09-26 엘지전자 주식회사 터보 디코딩 방법
US6662331B1 (en) * 2000-10-27 2003-12-09 Qualcomm Inc. Space-efficient turbo decoder
US6987543B1 (en) * 2000-11-30 2006-01-17 Lsi Logic Corporation System to efficiently transmit two HDTV channels over satellite using turbo coded 8PSK modulation for DSS compliant receivers
US7333419B2 (en) * 2000-11-30 2008-02-19 Sasken Communication Technologies, Inc. Method to improve performance and reduce complexity of turbo decoder
US7111207B2 (en) * 2001-01-31 2006-09-19 Mitsubishi Denki Kabushiki Kaisha Error-correcting communication method and communication apparatus with de-interleaving and rate de-matching
WO2002079758A1 (en) * 2001-03-29 2002-10-10 Circadiant Systems, Inc. Error function analysis of optical components with uncertainty ranges
US6973611B2 (en) * 2001-04-17 2005-12-06 Texas Instruments Incorporated Interleaved coder and method
US6392572B1 (en) * 2001-05-11 2002-05-21 Qualcomm Incorporated Buffer architecture for a turbo decoder
US7085969B2 (en) * 2001-08-27 2006-08-01 Industrial Technology Research Institute Encoding and decoding apparatus and method
US6961921B2 (en) * 2001-09-06 2005-11-01 Interdigital Technology Corporation Pipeline architecture for maximum a posteriori (MAP) decoders
US6701482B2 (en) * 2001-09-20 2004-03-02 Qualcomm Incorporated Method and apparatus for coding bits of data in parallel
US7586993B2 (en) * 2001-12-06 2009-09-08 Texas Instruments Incorporated Interleaver memory selectably receiving PN or counter chain read address
KR100762612B1 (ko) * 2001-12-07 2007-10-01 삼성전자주식회사 터보 복호화 장치에서 인터리버와 디인터리버간 메모리공유 장치 및 방법
JP2003203435A (ja) * 2002-01-09 2003-07-18 Fujitsu Ltd データ再生装置
US7092464B2 (en) * 2002-01-23 2006-08-15 Bae Systems Information And Electronic Systems Integration Inc. Multiuser detection with targeted error correction coding
US6981203B2 (en) * 2002-04-29 2005-12-27 Bae Systems Information And Electronic Systems Integration Inc. Method and apparatus for random shuffled turbo multiuser detector
TWI581121B (zh) 2002-05-01 2017-05-01 內數位科技公司 無線通信系統中使用高速共享頻道之點對多點服務
TWI445423B (zh) * 2002-05-01 2014-07-11 Interdigital Tech Corp 無線通信系統中使用共享頻道之點對多點服務
US6788240B2 (en) * 2002-05-15 2004-09-07 Justin Reyneri Single-chip massively parallel analog-to-digital conversion
US7111226B1 (en) * 2002-05-31 2006-09-19 Broadcom Corporation Communication decoder employing single trellis to support multiple code rates and/or multiple modulations
US7209527B2 (en) * 2002-07-08 2007-04-24 Agere Systems Inc. Turbo decoder employing max and max* map decoding
US7433429B2 (en) * 2002-07-19 2008-10-07 Intel Corporation De-interleaver method and system
US7091889B2 (en) 2002-09-09 2006-08-15 Telefonaktiebolaget Lm Ericsson (Publ) Speed and memory optimized interleaving
CN1685620A (zh) * 2002-09-25 2005-10-19 皇家飞利浦电子股份有限公司 用于递归运算数据的电路
US6907010B2 (en) * 2002-10-11 2005-06-14 Interdigital Technology Corporation Dynamic radio link adaptation for interference in cellular systems
JP4195484B2 (ja) * 2003-01-07 2008-12-10 サムスン エレクトロニクス カンパニー リミテッド 複合再伝送方式の移動通信システムにおける出力バッファ制御装置及び方法
US7139862B2 (en) * 2003-02-24 2006-11-21 Nokia Corporation Interleaving method and apparatus with parallel access in linear and interleaved order
US7352723B2 (en) * 2003-04-25 2008-04-01 Lucent Technologies Inc. Method of forming a coded composite transport channel for downlink transmissions
US7269783B2 (en) * 2003-04-30 2007-09-11 Lucent Technologies Inc. Method and apparatus for dedicated hardware and software split implementation of rate matching and de-matching
US7613985B2 (en) * 2003-10-24 2009-11-03 Ikanos Communications, Inc. Hierarchical trellis coded modulation
US20050180332A1 (en) * 2004-02-13 2005-08-18 Broadcom Corporation Low latency interleaving and deinterleaving
US9001921B1 (en) * 2004-02-18 2015-04-07 Marvell International Ltd. Circuits, architectures, methods, algorithms, software, and systems for improving the reliability of data communications having time-dependent fluctuations
US7702968B2 (en) * 2004-02-27 2010-04-20 Qualcomm Incorporated Efficient multi-symbol deinterleaver
US7386766B2 (en) * 2004-03-05 2008-06-10 Thomson Licensing Address generation apparatus for turbo interleaver and deinterleaver in W-CDMA systems
JP4765260B2 (ja) * 2004-03-31 2011-09-07 日本電気株式会社 データ処理装置およびその処理方法ならびにプログラムおよび携帯電話装置
EP1733477B1 (en) * 2004-04-09 2013-06-19 Agere Systems Inc. Sub-block interleaving and de-interleaving for multidimensional product block codes
CN1954503A (zh) 2004-05-18 2007-04-25 皇家飞利浦电子股份有限公司 Turbo解码器输入重新排序
US20070081484A1 (en) * 2004-07-29 2007-04-12 Wang Michael M Methods and apparatus for transmitting a frame structure in a wireless communication system
US9246728B2 (en) 2004-07-29 2016-01-26 Qualcomm Incorporated System and method for frequency diversity
US8391410B2 (en) * 2004-07-29 2013-03-05 Qualcomm Incorporated Methods and apparatus for configuring a pilot symbol in a wireless communication system
US20080317142A1 (en) * 2005-07-29 2008-12-25 Qualcomm Incorporated System and method for frequency diversity
MX2007001166A (es) * 2004-07-29 2007-07-11 Qualcomm Inc Sistema y metodo para intercalacion.
CN101057438A (zh) 2004-10-12 2007-10-17 阿瓦雷公司 电信环境中的资源共享
CN101116249B (zh) * 2005-02-03 2010-10-13 松下电器产业株式会社 并行交织器、并行解交织器以及交织方法
JP2008537410A (ja) * 2005-04-15 2008-09-11 トレリスウェア テクノロジーズ インコーポレイテッド クラッシュフリーなイレギュラーリピートアキュムレート符号
US9042212B2 (en) * 2005-07-29 2015-05-26 Qualcomm Incorporated Method and apparatus for communicating network identifiers in a communication system
US9391751B2 (en) * 2005-07-29 2016-07-12 Qualcomm Incorporated System and method for frequency diversity
US7793190B1 (en) 2005-08-10 2010-09-07 Trellisware Technologies, Inc. Reduced clash GRA interleavers
EP1811674A1 (en) * 2006-01-23 2007-07-25 Motorola, Inc. Apparatus and methods for jointly decoding messages based on apriori knowledge of modified codeword transmission
EP2280506A3 (en) * 2006-01-23 2015-03-11 Motorola Mobility LLC Apparatus and methods for handling a message difference prior to decoding based on apriori knowledge of modified codeword transmission
US8271848B2 (en) * 2006-04-06 2012-09-18 Alcatel Lucent Method of decoding code blocks and system for concatenating code blocks
KR101736999B1 (ko) 2006-04-12 2017-05-19 티큐 델타, 엘엘씨 패킷 재전송 및 메모리 공유
AU2006204634B2 (en) * 2006-08-31 2009-10-29 Canon Kabushiki Kaisha Runlength encoding of leading ones and zeros
US7783936B1 (en) 2006-09-28 2010-08-24 L-3 Communications, Corp. Memory arbitration technique for turbo decoding
US7882416B2 (en) * 2006-10-10 2011-02-01 Broadcom Corporation General and algebraic-constructed contention-free memory mapping for parallel turbo decoding with algebraic interleave ARP (almost regular permutation) of all possible sizes
US7827473B2 (en) * 2006-10-10 2010-11-02 Broadcom Corporation Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors
US7831894B2 (en) * 2006-10-10 2010-11-09 Broadcom Corporation Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves
US8065587B2 (en) * 2006-10-10 2011-11-22 Broadcom Corporation Reduced complexity ARP (almost regular permutation) interleaves providing flexible granularity and parallelism adaptable to any possible turbo code block size
EP2089974A2 (en) * 2006-11-01 2009-08-19 QUALCOMM Incorporated Turbo interleaver for high data rates
JP4728203B2 (ja) * 2006-11-06 2011-07-20 富士通セミコンダクター株式会社 半導体回路のレイアウト方法、プログラム、設計支援システム
JP2008135813A (ja) * 2006-11-27 2008-06-12 Fujitsu Ltd ターボ復号器及びターボ復号方法
EP1942578A1 (en) * 2006-11-29 2008-07-09 Broadcom Corporation Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves
US20080133997A1 (en) * 2006-12-01 2008-06-05 Broadcom Corporation, A California Corporation Turbo decoder employing ARP (almost regular permutation) interleave and inverse thereof as de-interleave
US9686044B2 (en) * 2007-03-27 2017-06-20 Qualcomm Incorporated Rate matching with multiple code block sizes
US20080316995A1 (en) * 2007-06-20 2008-12-25 Motorola, Inc. Broadcast channel signal and apparatus for managing the transmission and receipt of broadcast channel information
US8189581B2 (en) 2007-06-20 2012-05-29 Motorola Mobility, Inc. Method, signal and apparatus for managing the transmission and receipt of broadcast channel information
US20080320255A1 (en) * 2007-06-25 2008-12-25 Sonics, Inc. Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets
US7899051B2 (en) 2007-12-31 2011-03-01 Motorola Mobility, Inc. Broadcast channel signal, apparatus and method for transmitting and decoding broadcast channel information
US8572332B2 (en) * 2008-03-28 2013-10-29 Qualcomm Incorporated De-interleaving mechanism involving a multi-banked LLR buffer
US8458536B2 (en) 2008-07-17 2013-06-04 Marvell World Trade Ltd. Data recovery in solid state memory devices
US7839310B2 (en) * 2009-02-19 2010-11-23 Nokia Corporation Extended turbo interleavers for parallel turbo decoding
EP2422452A4 (en) * 2009-04-24 2013-07-24 Nokia Corp DATA RENEWAL FOR THE DECODER
US8811452B2 (en) * 2009-12-08 2014-08-19 Samsung Electronics Co., Ltd. Method and apparatus for parallel processing turbo decoder
US20120030544A1 (en) * 2010-07-27 2012-02-02 Fisher-Jeffes Timothy Perrin Accessing Memory for Data Decoding
US8719658B2 (en) 2010-09-09 2014-05-06 Qualcomm Incorporated Accessing memory during parallel turbo decoding
US9015551B2 (en) * 2012-04-19 2015-04-21 Mediatek Inc. Decoding apparatus with de-interleaving efforts distributed to different decoding phases and related decoding method thereof
US9256531B2 (en) 2012-06-19 2016-02-09 Samsung Electronics Co., Ltd. Memory system and SoC including linear addresss remapping logic
US9128888B2 (en) * 2012-08-30 2015-09-08 Intel Deutschland Gmbh Method and apparatus for turbo decoder memory collision resolution
CN103812510A (zh) * 2012-11-15 2014-05-21 中兴通讯股份有限公司 译码方法及装置
US9124403B2 (en) * 2013-04-30 2015-09-01 Qualcomm Incorporated Puncturing scheme based decoder optimizations
US9413665B2 (en) * 2014-08-20 2016-08-09 Netronome Systems, Inc. CPP bus transaction value having a PAM/LAM selection code field
KR101558172B1 (ko) * 2014-10-14 2015-10-08 숭실대학교산학협력단 오류 분산을 위한 인터리빙 방법 및 장치, 이를 수행하기 위한 기록매체
US9824058B2 (en) * 2014-11-14 2017-11-21 Cavium, Inc. Bypass FIFO for multiple virtual channels
US9467252B2 (en) 2014-11-26 2016-10-11 Freescale Semiconductor, Inc. Turbo decoders with extrinsic addressing and associated methods
CN106788466A (zh) * 2016-12-13 2017-05-31 中国电子科技集团公司第二十研究所 用于小型化通信系统的Turbo码编译码芯片
CN109495207B (zh) * 2017-09-11 2021-08-10 上海诺基亚贝尔股份有限公司 用于在无线通信系统中交织数据的方法和设备
CN116318552B (zh) * 2023-03-15 2023-09-22 归芯科技(深圳)有限公司 Turbo码的交织或解交织方法及其器件、通信芯片和装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ZA947317B (en) * 1993-09-24 1995-05-10 Qualcomm Inc Multirate serial viterbi decoder for code division multiple access system applications
US6381728B1 (en) * 1998-08-14 2002-04-30 Qualcomm Incorporated Partitioned interleaver memory for map decoder
US6223319B1 (en) * 1998-08-20 2001-04-24 General Electric Company Turbo code decoder with controlled probability estimate feedback
JP3746426B2 (ja) * 1999-02-26 2006-02-15 富士通株式会社 ターボ復号装置
CN1124691C (zh) * 1999-09-13 2003-10-15 华为技术有限公司 一种串/并行级联卷积码译码器及其译码实现方法
CN1133276C (zh) * 1999-11-12 2003-12-31 深圳市中兴通讯股份有限公司 一种高速并行级联码的译码方法及译码器
US6307901B1 (en) * 2000-04-24 2001-10-23 Motorola, Inc. Turbo decoder with decision feedback equalization
US6392572B1 (en) * 2001-05-11 2002-05-21 Qualcomm Incorporated Buffer architecture for a turbo decoder

Also Published As

Publication number Publication date
JP3996514B2 (ja) 2007-10-24
CN101394189B (zh) 2012-10-10
US6392572B1 (en) 2002-05-21
CN100426680C (zh) 2008-10-15
TW543303B (en) 2003-07-21
EP1388213A1 (en) 2004-02-11
CN101394189A (zh) 2009-03-25
KR20040034607A (ko) 2004-04-28
CN1529943A (zh) 2004-09-15
KR100963718B1 (ko) 2010-06-14
WO2002093755A1 (en) 2002-11-21
JP2004531138A (ja) 2004-10-07

Similar Documents

Publication Publication Date Title
BR0209559A (pt) Arquitetura de buffer para um decodificador turbo
US11487676B2 (en) Address mapping in memory systems
WO2006057949A3 (en) Method and apparatus of multiple abbreviations of interleaved addressing of paged memories and intelligent memory banks therefor
KR20080020066A (ko) 동일한 픽셀 데이터 그룹에 포함되는 픽셀 데이터들을메모리의 동일한 뱅크 어드레스로 매핑하는 매핑 방법 및비디오 시스템
RU2007107350A (ru) Система и способ перемежения
KR20110059712A (ko) 메모리 모듈 및 메모리 모듈 제어 방법
WO2003085524A3 (en) Improved architecture with shared memory
CA2408481A1 (en) Autonomic reallocation of memory among buffer pools
US20120198121A1 (en) Method and apparatus for minimizing cache conflict misses
WO2003041119A3 (en) Improved architecture with shared memory
JP2001022638A (ja) 情報処理システム
US20220276795A1 (en) Hardware-software collaborative address mapping scheme for efficient processing-in-memory systems
US7221612B2 (en) SDRAM address mapping optimized for two-dimensional access
TWI473014B (zh) 增強型微處理器或微控制器
ATE468564T1 (de) Verbindungen in simd-prozessorarchitekturen
KR920008596A (ko) 컴퓨터 프로세서 내부의 유용한 레지스터수 증가장치
DE60139140D1 (de) Bit-parallele/bit-serielle inhaltsadressierbare (assoziative) verbundspeicheranordnungen
RU2008141459A (ru) Способ организации глобально-адресуемой общей памяти в многопроцессорной эвм
GB0405283D0 (en) Multi-port memory for flexible and space efficient corner turning networks in associative processors
Wang et al. Tile/line access cache memory based on a multi‐level Z‐order tiling data layout
RU2487398C1 (ru) Способ формирования виртуальной памяти и устройство для его реализации
CN104636268B (zh) 一种可重构缓存产品与方法
US7752398B2 (en) Multi-port memory architecture for storing multi-dimensional arrays I
Wang et al. A cache memory with unit tile and line accessibility
CN104407985B (zh) 存储器地址映射方法及存储器地址映射系统

Legal Events

Date Code Title Description
B08F Application fees: application dismissed [chapter 8.6 patent gazette]

Free format text: REFERENTE A 9A ANUIDADE(S).

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2108 DE 31/05/2011.