BR0114128A - Entrelaçador de modem fdd de terceira geração - Google Patents

Entrelaçador de modem fdd de terceira geração

Info

Publication number
BR0114128A
BR0114128A BR0114128-7A BR0114128A BR0114128A BR 0114128 A BR0114128 A BR 0114128A BR 0114128 A BR0114128 A BR 0114128A BR 0114128 A BR0114128 A BR 0114128A
Authority
BR
Brazil
Prior art keywords
words
block
elements
sequential
deinterlacing
Prior art date
Application number
BR0114128-7A
Other languages
English (en)
Inventor
Sharif M Shahrier
Original Assignee
Interdigital Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Interdigital Tech Corp filed Critical Interdigital Tech Corp
Publication of BR0114128A publication Critical patent/BR0114128A/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation
    • H03M13/2764—Circuits therefore
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

"ENTRELAçADOR DE MODEM FDD DE TERCEIRA GERAçãO". São descritos método e aparelho para o desentrelaçamento de blocos de dados entrelaçados expandidos, particularmente para utilização em sistemas de telecomunicações sem fio, tais como os fornecidos pelo padrão do Projeto de Parceria de Terceira Geração (3G). Os dados são processados em base de elementos seq³enciais, em que cada elemento contém quantidade previamente determinada de bits M, que estão contidos em um bloco de palavras de dados seq³enciais W<39>. Os elementos são extraídos do bloco de palavras W<39> em ordem seq³encial, com cada elemento sendo extraído a partir de uma ou duas palavras entrelaçadas seq³enciais dentro do conjunto de palavras W<39>. Os elementos são armazenados em locais seletivos dentro de um conjunto de palavras W de uma memória desentrelaçadora, de tal forma que, ao completar-se a extração e escrita de todos os elementos, as palavras W da memória desentrelaçadora podem ser lidas seq³encialmente para que correspondam a um bloco de dados original de bits a partir do qual foi criado o bloco de elementos entrelaçados. Processamento convencional adicional resulta na contração das palavras expandidas desentrelaçadas, para reproduzir o bloco de dados de bits em um receptor, conforme designado originalmente para transmissão em um transmissor.
BR0114128-7A 2000-09-13 2001-07-19 Entrelaçador de modem fdd de terceira geração BR0114128A (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US23222400P 2000-09-13 2000-09-13
US26093001P 2001-01-11 2001-01-11
PCT/US2001/022807 WO2002023740A1 (en) 2000-09-13 2001-07-19 Third generation fdd modem interleaver

Publications (1)

Publication Number Publication Date
BR0114128A true BR0114128A (pt) 2003-07-29

Family

ID=26925780

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0114128-7A BR0114128A (pt) 2000-09-13 2001-07-19 Entrelaçador de modem fdd de terceira geração

Country Status (16)

Country Link
US (2) US6947491B2 (pt)
EP (1) EP1320929A1 (pt)
JP (1) JP4824262B2 (pt)
KR (2) KR100797871B1 (pt)
CN (1) CN1272912C (pt)
AR (1) AR030634A1 (pt)
AU (1) AU2001280631A1 (pt)
BR (1) BR0114128A (pt)
CA (1) CA2421956C (pt)
HK (1) HK1060219A1 (pt)
IL (2) IL154858A0 (pt)
MX (1) MXPA03002200A (pt)
MY (1) MY135106A (pt)
NO (1) NO20031135L (pt)
TW (3) TWI239728B (pt)
WO (1) WO2002023740A1 (pt)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4029630B2 (ja) * 2002-02-27 2008-01-09 ソニー株式会社 インタリーブ処理装置とインタリーブ処理方法及びインタリーブ処理プログラム
KR100486284B1 (ko) * 2002-11-22 2005-04-29 삼성전자주식회사 연속되는 두 개의 디인터레이스 프레임들을 출력할 수있는 디인터레이스 장치 및 디인터레이스 방법
US8077743B2 (en) * 2003-11-18 2011-12-13 Qualcomm Incorporated Method and apparatus for offset interleaving of vocoder frames
US8325826B2 (en) * 2005-03-09 2012-12-04 Qualcomm Incorporated Methods and apparatus for transmitting signals facilitating antenna control
US8225186B2 (en) * 2006-07-14 2012-07-17 Qualcomm Incorporated Ecoding and decoding methods and apparatus for use in a wireless communication system
CN104390267B (zh) * 2014-10-31 2017-05-24 广东美的制冷设备有限公司 空调器及该空调器的送风方法
WO2019155468A1 (en) 2018-02-08 2019-08-15 Yissum Research Development Company Of The Hebrew University Of Jerusalem Ltd. Heteroaryl compounds, pharmaceutical compositions thereof, and their therapeutic use
US11540120B2 (en) * 2018-06-05 2022-12-27 Drexel University Physical layer key based interleaving for secure wireless communication
TWI685217B (zh) * 2018-07-23 2020-02-11 朱盈宇 可辨封包次序更正碼
SG11202113211PA (en) 2019-06-03 2021-12-30 Biotheryx Inc Non-hygroscopic crystalline salts of a pyrazole compound, and pharmaceutical compositions and use thereof
CN111478708B (zh) * 2020-03-31 2023-08-11 Oppo广东移动通信有限公司 电子设备、芯片、系统总线、译码模块、译码器及方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4394642A (en) * 1981-09-21 1983-07-19 Sperry Corporation Apparatus for interleaving and de-interleaving data
DK2302806T3 (da) * 1995-02-01 2013-06-17 Sony Corp Flerkanalstransmission med interleaving ved adressering på stedet af RAM-hukommelse
EP0749211B1 (de) * 1995-06-12 2003-05-02 Siemens Aktiengesellschaft Verfahren und Codiereinrichtung zur gesicherten Übertragung von Daten mittels Mehrkomponenten-Codierung
JPH10200502A (ja) * 1997-01-07 1998-07-31 N T T Ido Tsushinmo Kk Ｃｄｍａ移動通信システムにおけるデータ伝送方法およびｃｄｍａ移動通信システムと移動局装置と基地局装置
US5912898A (en) * 1997-02-27 1999-06-15 Integrated Device Technology, Inc. Convolutional interleaver/de-interleaver
DE69935356T2 (de) * 1998-04-27 2007-11-08 Matsushita Electric Industrial Co., Ltd., Kadoma Verfahren zur Faltungsentschachtelung
JP2000124816A (ja) * 1998-10-14 2000-04-28 Oki Electric Ind Co Ltd 符号化インタリーブ装置
US6233709B1 (en) * 1998-12-07 2001-05-15 Nokia Mobile Phones Ltd. Dynamic iterative decoding for balancing quality of service parameters
KR100350459B1 (ko) * 1998-12-26 2002-12-26 삼성전자 주식회사 통신시스템의인터리빙/디인터리빙장치및방법
WO2000062461A2 (en) * 1999-04-09 2000-10-19 Sony Electronics Inc. Interleavers and de-interleavers

Also Published As

Publication number Publication date
US6947491B2 (en) 2005-09-20
KR20030031186A (ko) 2003-04-18
NO20031135L (no) 2003-05-13
US20020083279A1 (en) 2002-06-27
MY135106A (en) 2008-02-29
KR20030097841A (ko) 2003-12-31
WO2002023740A1 (en) 2002-03-21
IL154858A (en) 2007-10-31
AR030634A1 (es) 2003-08-27
US7317762B2 (en) 2008-01-08
AU2001280631A1 (en) 2002-03-26
HK1060219A1 (en) 2004-07-30
TWI271954B (en) 2007-01-21
JP4824262B2 (ja) 2011-11-30
US20050273676A1 (en) 2005-12-08
CA2421956A1 (en) 2002-03-21
KR100797871B1 (ko) 2008-01-24
TW200419922A (en) 2004-10-01
CN1471762A (zh) 2004-01-28
CN1272912C (zh) 2006-08-30
CA2421956C (en) 2007-01-09
TWI239728B (en) 2005-09-11
TWI269548B (en) 2006-12-21
KR100541586B1 (ko) 2006-01-11
IL154858A0 (en) 2003-10-31
EP1320929A1 (en) 2003-06-25
NO20031135D0 (no) 2003-03-12
TW200300061A (en) 2003-05-01
JP2004509501A (ja) 2004-03-25
MXPA03002200A (es) 2007-10-02

Similar Documents

Publication Publication Date Title
BR0114128A (pt) Entrelaçador de modem fdd de terceira geração
AR023765A1 (es) Metodo para proveer un control de error mejorado y dispositivo de comunicacion
KR870003628A (ko) 회로망 멀티플렉스 구조물
BR0114399A (pt) estrutura de buffer de dados para canais fìsico e de transporte em um sistema cdma
BR9906479A (pt) Dispositivo decodificador de canal, e, processo de codificação de canal
KR870008454A (ko) 패킷발생용 장치
EP2290826A3 (en) Lost packet recovery method for packet transmission protocols
CO5611229A2 (es) Sistemas y metodos para la autenticacion acustica de dos factores
BR0209261A (pt) Método e dispositivo de comunicação para transmitir dados por uma pluralidade de canais de comunicação
GB2352594A (en) Method and system for multiplexing of multiple users for enhanced capacity radiocommunications
AU2003222939A1 (en) Computer representation of a data tree structure and the associated encoding/decoding methods
SE8302763L (sv) Digitaltransmissionssystem
DE69931751D1 (de) Vorrichtung und verfahren zur einfügung von vorher bekannten bits in die eingangsstufe eines kanalkodierers
ES2117560A1 (es) Decodificador y metodo para el mismo.
WO2001055916A3 (en) Method and apparatus for binary encoding logic circuits
ATE83104T1 (de) Anordnung zur kodierung und dekodierung von sequentiellen nachrichten in datenverarbeitungssystemen.
TW430818B (en) Address decoding scheme for DDR memory
MY112024A (en) Method and apparatus for encoding and decoding information in a digital communication system
BR9917496A (pt) Método, sistema e aparelho para reduzir tempo de sincronização e resincronização para sistemas com enchimento de pulso
CN105680983A (zh) 一种解速率匹配和解交织的方法和装置
GB9914876D0 (en) Data procesors
SE9802461D0 (sv) Bit stuffing for synchronous HDLC
Wayner A redundancy reducing cipher
KR960704433A (ko) 텔레텍스트 페이지 전송 방법(Method of transmitting teletext pages)
IL194050A (en) Method for encoded or encrypted bit stream synchronization

Legal Events

Date Code Title Description
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 8A , 9A E 10 ANUIDADES.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: REFERENTE AO DESPACHO 8.6 PUBLICADO NA RPI 2144 DE 07/02/2012.