BE843794A - Procede pour reduire ka duree de vie des porteurs minoritaires dans les semiconducteurs et dispositifs en resultant - Google Patents

Procede pour reduire ka duree de vie des porteurs minoritaires dans les semiconducteurs et dispositifs en resultant

Info

Publication number
BE843794A
BE843794A BE168641A BE168641A BE843794A BE 843794 A BE843794 A BE 843794A BE 168641 A BE168641 A BE 168641A BE 168641 A BE168641 A BE 168641A BE 843794 A BE843794 A BE 843794A
Authority
BE
Belgium
Prior art keywords
semiconductors
lifetime
procedure
reducing
resulting devices
Prior art date
Application number
BE168641A
Other languages
English (en)
French (fr)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of BE843794A publication Critical patent/BE843794A/xx

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00Ion implantation into wafers, substrates or parts of devices
    • H10P30/20Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137Collector regions of BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS
    • H10D84/854Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00Ion implantation into wafers, substrates or parts of devices
    • H10P30/20Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/024Defect control-gettering and annealing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/904Charge carrier lifetime control
BE168641A 1975-08-07 1976-07-05 Procede pour reduire ka duree de vie des porteurs minoritaires dans les semiconducteurs et dispositifs en resultant BE843794A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/602,710 US4053925A (en) 1975-08-07 1975-08-07 Method and structure for controllng carrier lifetime in semiconductor devices

Publications (1)

Publication Number Publication Date
BE843794A true BE843794A (fr) 1976-11-03

Family

ID=24412483

Family Applications (1)

Application Number Title Priority Date Filing Date
BE168641A BE843794A (fr) 1975-08-07 1976-07-05 Procede pour reduire ka duree de vie des porteurs minoritaires dans les semiconducteurs et dispositifs en resultant

Country Status (14)

Country Link
US (1) US4053925A (https=)
JP (2) JPS5221775A (https=)
AU (1) AU501673B2 (https=)
BE (1) BE843794A (https=)
CA (1) CA1048653A (https=)
CH (1) CH600571A5 (https=)
DE (1) DE2634500A1 (https=)
ES (1) ES450165A1 (https=)
FR (1) FR2320636A1 (https=)
GB (1) GB1492367A (https=)
IT (1) IT1063768B (https=)
NL (1) NL7608644A (https=)
SE (1) SE415062B (https=)
ZA (1) ZA764477B (https=)

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US4193079A (en) * 1978-01-30 1980-03-11 Xerox Corporation MESFET with non-uniform doping
US4276555A (en) * 1978-07-13 1981-06-30 International Business Machines Corporation Controlled avalanche voltage transistor and magnetic sensor
JPS5939904B2 (ja) * 1978-09-28 1984-09-27 株式会社東芝 半導体装置
US4274105A (en) * 1978-12-29 1981-06-16 International Business Machines Corporation MOSFET Substrate sensitivity control
US4291329A (en) * 1979-08-31 1981-09-22 Westinghouse Electric Corp. Thyristor with continuous recombination center shunt across planar emitter-base junction
US4249962A (en) * 1979-09-11 1981-02-10 Western Electric Company, Inc. Method of removing contaminating impurities from device areas in a semiconductor wafer
US4318750A (en) * 1979-12-28 1982-03-09 Westinghouse Electric Corp. Method for radiation hardening semiconductor devices and integrated circuits to latch-up effects
JPS56135960A (en) * 1980-03-28 1981-10-23 Nec Corp Semiconductor ic device
US4300152A (en) * 1980-04-07 1981-11-10 Bell Telephone Laboratories, Incorporated Complementary field-effect transistor integrated circuit device
US4432008A (en) * 1980-07-21 1984-02-14 The Board Of Trustees Of The Leland Stanford Junior University Gold-doped IC resistor region
JPS5814538A (ja) * 1981-07-17 1983-01-27 Fujitsu Ltd 半導体装置の製造方法
US4412868A (en) * 1981-12-23 1983-11-01 General Electric Company Method of making integrated circuits utilizing ion implantation and selective epitaxial growth
FR2534415A1 (fr) * 1982-10-07 1984-04-13 Cii Honeywell Bull Procede de fabrication de resistances electriques dans un materiau semi-conducteur polycristallin et dispositif a circuits integres resultant
US4716451A (en) * 1982-12-10 1987-12-29 Rca Corporation Semiconductor device with internal gettering region
JPS6031232A (ja) * 1983-07-29 1985-02-18 Toshiba Corp 半導体基体の製造方法
US4633289A (en) * 1983-09-12 1986-12-30 Hughes Aircraft Company Latch-up immune, multiple retrograde well high density CMOS FET
US4710477A (en) * 1983-09-12 1987-12-01 Hughes Aircraft Company Method for forming latch-up immune, multiple retrograde well high density CMOS FET
GB2171555A (en) * 1985-02-20 1986-08-28 Philips Electronic Associated Bipolar semiconductor device with implanted recombination region
JPS61264751A (ja) * 1985-05-17 1986-11-22 Nippon Telegr & Teleph Corp <Ntt> 相補性mis型電界効果トランジスタ装置
US4689667A (en) * 1985-06-11 1987-08-25 Fairchild Semiconductor Corporation Method of controlling dopant diffusion and dopant electrical activation by implanted inert gas atoms
US4806498A (en) * 1985-06-21 1989-02-21 Texas Instruments Incorporated Semiconductor charge-coupled device and process of fabrication thereof
US4701775A (en) * 1985-10-21 1987-10-20 Motorola, Inc. Buried n- channel implant for NMOS transistors
JPS62219636A (ja) * 1986-03-20 1987-09-26 Hitachi Ltd 半導体装置
JPS63254762A (ja) * 1987-04-13 1988-10-21 Nissan Motor Co Ltd Cmos半導体装置
JPH0821678B2 (ja) * 1987-05-29 1996-03-04 日産自動車株式会社 半導体装置
US4881107A (en) * 1987-07-03 1989-11-14 Nissan Motor Company, Ltd. IC device having a vertical MOSFET and an auxiliary component
US5102810A (en) * 1990-03-13 1992-04-07 General Instrument Corp. Method for controlling the switching speed of bipolar power devices
US5097308A (en) * 1990-03-13 1992-03-17 General Instrument Corp. Method for controlling the switching speed of bipolar power devices
US5554883A (en) * 1990-04-28 1996-09-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method therefor
JPH05198666A (ja) * 1991-11-20 1993-08-06 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5384477A (en) * 1993-03-09 1995-01-24 National Semiconductor Corporation CMOS latchup suppression by localized minority carrier lifetime reduction
US5358879A (en) * 1993-04-30 1994-10-25 Loral Federal Systems Company Method of making gate overlapped lightly doped drain for buried channel devices
EP0715770A1 (en) * 1993-09-03 1996-06-12 National Semiconductor Corporation Planar isolation method for use in fabrication of microelectronics
JP3135762B2 (ja) * 1993-10-29 2001-02-19 株式会社東芝 半導体集積回路装置
US5508211A (en) * 1994-02-17 1996-04-16 Lsi Logic Corporation Method of making integrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrate
JPH07335870A (ja) * 1994-06-14 1995-12-22 Mitsubishi Electric Corp 半導体装置およびその製造方法
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US6455903B1 (en) * 2000-01-26 2002-09-24 Advanced Micro Devices, Inc. Dual threshold voltage MOSFET by local confinement of channel depletion layer using inert ion implantation
DE10061191A1 (de) * 2000-12-08 2002-06-13 Ihp Gmbh Schichten in Substratscheiben
US20040176483A1 (en) * 2003-03-05 2004-09-09 Micron Technology, Inc. Cellular materials formed using surface transformation
US6836134B2 (en) * 2002-06-11 2004-12-28 Delphi Technologies, Inc. Apparatus and method for determining leakage current between a first semiconductor region and a second semiconductor region to be formed therein
DE10261307B4 (de) * 2002-12-27 2010-11-11 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Spannungsoberflächenschicht in einem Halbleiterelement
US7501329B2 (en) * 2003-05-21 2009-03-10 Micron Technology, Inc. Wafer gettering using relaxed silicon germanium epitaxial proximity layers
US7662701B2 (en) * 2003-05-21 2010-02-16 Micron Technology, Inc. Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers
US6929984B2 (en) * 2003-07-21 2005-08-16 Micron Technology Inc. Gettering using voids formed by surface transformation
US7550787B2 (en) * 2005-05-31 2009-06-23 International Business Machines Corporation Varied impurity profile region formation for varying breakdown voltage of devices
US8552616B2 (en) * 2005-10-25 2013-10-08 The Curators Of The University Of Missouri Micro-scale power source
US8492829B2 (en) 2008-09-01 2013-07-23 Rohm Co., Ltd. Semiconductor device having super junction metal oxide semiconductor structure and fabrication method for the same
JP2014090072A (ja) * 2012-10-30 2014-05-15 Fuji Electric Co Ltd 逆阻止mos型半導体装置及びその製造方法
DE102017130355B4 (de) * 2017-12-18 2025-11-20 Infineon Technologies Ag Verfahren zum Bilden eines Halbleiterbauelements
US10651281B1 (en) * 2018-12-03 2020-05-12 Globalfoundries Inc. Substrates with self-aligned buried dielectric and polycrystalline layers

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Also Published As

Publication number Publication date
AU1665476A (en) 1978-02-09
DE2634500A1 (de) 1977-02-17
SE7608635L (sv) 1977-02-08
ES450165A1 (es) 1977-06-16
ZA764477B (en) 1978-03-29
US4053925A (en) 1977-10-11
JPS5723425B2 (https=) 1982-05-18
IT1063768B (it) 1985-02-11
AU501673B2 (en) 1979-06-28
GB1492367A (en) 1977-11-16
SE415062B (sv) 1980-09-01
JPS57118667A (en) 1982-07-23
CA1048653A (en) 1979-02-13
JPS5221775A (en) 1977-02-18
FR2320636B1 (https=) 1978-05-19
NL7608644A (nl) 1977-02-09
JPS5942464B2 (ja) 1984-10-15
CH600571A5 (https=) 1978-06-15
FR2320636A1 (fr) 1977-03-04

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Legal Events

Date Code Title Description
RE Patent lapsed

Owner name: INTERNATIONAL BUSINESS MACHINES CORP.

Effective date: 19840705