EP0715770A1

EP0715770A1 - Planar isolation method for use in fabrication of microelectronics

Info

Publication number: EP0715770A1
Application number: EP94922567A
Authority: EP
Inventors: David A. Hanson; Sheldon Aronowitz; Esin K. Demirlioglu
Original assignee: National Semiconductor Corp
Current assignee: National Semiconductor Corp
Priority date: 1993-09-03
Filing date: 1994-07-15
Publication date: 1996-06-12
Also published as: WO1995006956A1; JPH09502303A

Abstract

A method of electrically isolating individual devices during the fabrication of microelectronic devices. The method is intended to replace oxide isolation methods currently used in the semiconductor industry. In a first embodiment of the present invention, the regions of a silicon substrate that are to be formed into isolation structures are exposed to a dose or doses of a noble gas implant. The noble gas implant can be preceded by a germanium implant in order to create an amorphous layer within the substrate, as a means of reducing the lateral damage caused by the noble gas implant. The noble gas implant is followed by a short time, low temperature furnace anneal which stabilizes the implanted regions. The noble gas implant suppresses epitaxial regrowth in the implanted regions, producing high resistivity and reducing leakage currents to a negligible level. In a second embodiment of the present invention, the regions of a silicon substrate that are to be formed into isolation structures are exposed to a dose or doses of germanium. The germanium implant is then followed by a short time, a low temperature furnace anneal. In either embodiment of the invention, the result is a highly effective, substantially planar isolation structure which overcomes many of the disadvantages of standard isolation techniques.

Description

Planar Isolation Method for Use in Fabrication of Microelectronics

TECHNICAL FIELD

The present invention is generally directed to the fabrication of microelectronics, and more specifically, to a method of electrically isolating individual devices in integrated circuits during such fabrication in a manner which produces a highly planar surface.

BACKGROUND OF THE INVENTION

Integrated circuits are produced by means of a fabrication process which converts a circuit design into an operable device. The fabrication process consists of a sequence of steps which transforms a substrate of semiconductor material, typically silicon, into a device with multiple layers, each having a specific pattern of structures and interconnections. A finished integrated circuit is often comprised of a multitude of smaller devices which are electrically connected in a desired manner. Other microelectronic devices such as hybrids, micro- mechanical motors, thin film magnetic heads, and miniature batteries can be produced in a similar fashion. In order for an integrated circuit to properly operate, it is necessary that the component devices initially be electrically isolated from each other. The devices can then be connected by means of standard interconnection techniques. Isolation techniques are thus a critical part of the fabrication process, because without them, properly functioning complex integrated circuits could not be constructed. The importance of device isolation to the fabrication of integrated circuits has lead to the development of a variety of processes which are designed to achieve that goal. A variety of isolation processes are required because different types of integrated circuits (e.g., N OS, CMOS, bipolar) have differing electrical and structural characteristics, and this can affect what structures are required for effective isolation. The isolation techniques vary in such attributes as minimum isolation spacing (the minimum separation required to isolate structures) , planarity of the final surface (which impacts the ease with which later fabrication steps can be carried out) , complexity of the isolation process, and the density of defects created during the process.

In "Silicon Processing for the VLSI Era, Volume 2: Process Integration" by S. Wolf, published by Lattice Press, Sunset Beach, California (1990) , the author discusses many of the isolation processes currently being used during the fabrication of integrated circuits. One of the most basic isolation processes is termed the direct isolation technique. This technique involves the formation of an oxide layer in the inactive (or field) regions of the substrate on which the devices are fabricated. The oxide is grown as a continuous film which is then selectively removed from the active regions by means of photolithographic techniques. This isolation process is used for MOS integrated circuits and is designed to prevent the formation of channels in the field oxide regions between individual devices, where such channels would serve to electrically connect the devices. In the direct isolation process the entire isolation oxide is grown above the surface of the silicon substrate. This produces a highly non-planar surface after the removal of the oxide from the active regions. For this reason, several variants of the direct isolation technique have been developed. These variants include the fully recessed isolation oxide process (which involves etching trenches into the substrate to a sufficient depth as to cause the final level of the oxide layer to be at the surface of the substrate) and the semirecessed local oxidation of silicon (LOCOS) isolation oxide process.

The variations of the direct isolation process were developed to address some of the problems inherent in the use of that isolation technique. For instance, the fully recessed process provides a highly planar final surface when compared to direct isolation processes. However, the fully recessed process has the disadvantage of being more complex than standard processes (as it requires additional etching steps) , and the growth of the oxide can result in the production of defects in the silicon substrate.

In a conventional LOCOS process the oxide layer is approximately twice as thick as the layer of silicon which is consumed to form the oxide. The growth of the oxide impacts the size and surface planarity of the finished devices, and hence can affect subsequent fabrication steps, as well as the density with which active layers of the device may be packed in the horizontal direction. Approximately 56% of the total oxide thickness grown is above the original surface of the substrate, while approximately 44% extends into the substrate. This reduces the step height of the oxide layer as compared to the situation where the entire oxide layer is above the substrate, but provides a greater step height than does the fully recessed process.

The semirecessed-oxide LOCOS process, like the fully recessed process, thus allows a more planar deposition of subsequent polysilicon and metal layers than can be obtained through the use of direct isolation processes. The semirecessed process is also less complex, and results in fewer process induced defects in the silicon substrate than does the fully recessed process. For these reasons it has become the preferred isolation technique for MOS devices having feature geometries of less than 5 μm. In addition to variants of the direct isolation process, non-oxide growth isolation techniques have been developed. One of these is termed the "trench etch and refill" isolation technique. According to the Wolf reference, this method has been used in the fabrication of several types of devices: the replacement of the LOCOS technique for devices having the same channel type within the same tub in CMOS, for isolation of bipolar devices, for isolation of n- channel from p-channel devices and to prevent latchup in CMOS, for use as trench-capacitor structures in dynamic random access memory devices (DRAMs) , and for use in load resistor structures in static random access memory devices (SRAMS) .

An overview of the semirecessed-oxide LOCOS process will be presented as a means of introducing the primary concepts and steps involved in a typical isolation process. These steps are discussed in more detail in the Wolf reference at pages 20-28.

A semiconductor wafer, typically silicon, is cleaned and a thin (20-60 nanometers) layer of oxide (Si0₂) is grown on the surface. This layer is called a pad or buffer oxide and is intended to provide a transition layer between the substrate and a subsequently deposited nitride layer. The buffer oxide reduces the high tensile stress placed on the substrate which is associated with the deposition of the nitride layer, and thereby reduces defect formation in the silicon substrate.

The next step is to deposit a 100-200 nanometer (nm) thick layer of silicon nitride on the buffer oxide. The nitride is used as an oxidation mask, allowing the active regions of the device to be ^• defined by means of standard photolithographic techniques used in the semiconductor industry. These techniques use photoresist and chrome images on glass known as masks to define the areas where active devices will be formed. After application of the resist layer and definition of the active device regions by use of the mask and an illumination source, the resist is developed (removing the resist from all but the active regions) and the unprotected nitride layer and buffer oxide are etched by appropriate processes. After the etch step, the remaining resist is left in place to serve as a mask during a channel-stop implant step. A channel-stop implant of a suitable ion

(typically Boron) is then carried out in the field regions of the device. This creates a doping layer which acts as a barrier, preventing a channel from forming outside of the active regions of the device. After the implant has been completed, the remaining resist is removed.

After the channel-stop implant step, field oxide is thermally grown by wet oxidation. The oxide layer grows in areas where there is no masking nitride layer, however, at the edges of the nitride some of the oxygen diffuses laterally, causing oxide to grow under and lift the edges of the nitride. This creates what is termed a "bird's beak" oxide and is an extension of the field oxide into the active regions of the device.

After the growth of the field oxide, the masking layer of nitride is removed. Since the top 20-30 nm of the nitride layer is converted to oxide during the field oxidation, this layer is etched off first. The remaining nitride and pad oxide layers are then etched by a suitable etch process, for instance a wet-chemical etch.

An issue of some concern when using LOCOS isolation techniques is the discovery by Kooi et al. that during the growth of the field oxide, a thin layer of silicon nitride can form on the surface of the silicon substrate at the pad oxide-silicon interface. This is a result of the interaction between NH₃ and silicon at the interface. The NH₃ is produced from the reaction between H₂0 and the masking nitride during the oxidation step. During the subsequent growth of a gate oxide layer, the gate oxide is impeded in areas where the silicon nitride has been formed. The gate oxide is thus thinner at these locations than it is elsewhere. This can cause a low voltage breakdown of the gate oxide, impacting the desired operation of the device. One way to reduce this problem is to grow a "sacrificial" gate oxide layer after stripping the masking nitride and pad oxide, and then remove this layer prior to growing the final gate oxide.

Although LOCOS isolation techniques have found wide application within the semiconductor industry, there are disadvantages to their use. The bird's beak oxide structure can cause unacceptable amounts of encroachment of the field oxide into the active regions of the device. This limits the packing density of the devices, and impacts later stages of the fabrication process. Another problem is that Boron atoms from the channel-stop implant of n- channel MOSFETs are redistributed during the growth of the field oxide and other high temperature processing steps. This can lead to unacceptable narrow width effects, and results in the preferential segregation into the oxide of the implanted Boron ions.

Another problem with LOCOS processes is that the surface topography which results from the application of the process may lack the degree of planarity desired for later stages of the fabrication process. To alleviate this problem a further planarization step may be required, which impacts the complexity of the fabrication process and the size of the finished product. Other problems associated with LOCOS processes relate to the complexity of the processes and the conditions under which the process steps are carried out. Lengthy field oxidation cycles increase the fabrication time, the use of a nitride oxidation mask increases the number of steps and raises alignment concerns, the Kooi effect can impact the operation of the device, and the use of a sacrificial gate oxide to counter the Kooi effect further increases the complexity of the process. This suggests that the development of an alternative to LOCOS isolation processes would be advantageous.

What is desired is an isolation process for use in electrically isolating individual devices during the fabrication of integrated circuits or microelectronic devices which provides a highly planar final surface and is not subject to the disadvantages of standard oxide isolation processes.

SUMMARY OF THE INVENTION

The present invention is directed to a method of electrically isolating devices during the fabrication of microelectronics, and is especially applicable to the fabrication of integrated circuits. One application of the method is intended to replace oxide growth, etch and refill, and blanket oxygen implantation for silicon-on-insulator (SOI) isolation methods currently used in the semiconductor industry.

In a first embodiment of the present invention, the regions of a silicon or compound semiconductor substrate or poly-silicon layer that are to be formed into isolation structures are instead implanted with a dose or doses of a noble gas. The noble gas implants can be preceded by a germanium implant in order to create an amorphous layer within the substrate, as a means of reducing the lateral damage caused by the noble gas implants.

A short time, low temperature furnace anneal is then performed to stabilize the implanted regions. The noble gas implant suppresses epitaxial regrowth in the implanted regions, producing high resistivity and reducing leakage currents to a negligible level.

In a second embodiment of the present invention, the regions of a silicon or SiGe substrate, or polycrystalline layer composed of Si or SiGe that are to be formed into isolation structures are instead implanted with a dose or doses of germanium. It has been discovered that germanium concentrations higher than seven (7) atomic percent suppress the epitaxial regrowth in the implanted regions of Si or SiGe alloys, producing regions of high resistivity. The resistivity of these regions can be further increased by additional oxygen or noble gas implants. Again, the implant is followed by a short time, low temperature anneal step. The result of either embodiment of the present

« invention is a highly effective, substantially planar isolation structure which overcomes many of the disadvantages of standard isolation techniques.

Further objects and advantages of the present invention will, become apparent from the following detailed description and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and IB are a plan and cross-sectional view, respectively, of an integrated circuit which is fabricated using a conventional LOCOS isolation technique.

FIG. 2 is a graph showing the concentration of a noble gas as a function of depth into a silicon substrate, where the nobel gas has been implanted in accordance with the method of the present invention.

FIG. 3 is a graph showing the concentration of germanium as a function of depth into a silicon substrate, where the germanium has been implanted in accordance with the method of the present invention. FIGS. 4A-4H show a typical process flow for the fabrication of a CMOS device having isolation regions formed according to the method of the present invention.

FIGS. 5A and 5B are a plan and cross-sectional view, respectively, of an integrated circuit which is fabricated using the isolation techniques of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to the figures, and in particular to Figs. 1A and IB, there are shown a plan and cross- sectional view, respectively, of an integrated circuit 1 which is fabricated using a conventional LOCOS isolation technique. Integrated circuit 1 is fabricated on substrate 10 which is typically made of silicon. A lithography step is used to define active regions 12 and 14 of the device. After definition of active regions 12 and 14, an implant of a suitable ion is performed. Typical dopants which are used include Boron and Boron Fluoride which are implanted at a dose of 1 to 10 x 10¹³ ions/cm² at an energy of 30 to 100 KeV. This implant is known as a channel-stop implant and creates a barrier to the formation of an electrical channel between the active regions. In Fig. IB, elements 16, 18, and 20 are channel-stop implants. The next step in the fabrication of integrated circuit 1 is to grow field oxide isolation structures in the inactive regions of the device. These areas are those which fall in between active regions 12 and 14, and are indicated by elements 22, 24, and 26 in Fig. IB. As is evident from Fig. IB, a portion of the field oxide which is grown is above the surface of substrate 10, creating a non-planar surface on which subsequent stages of the fabrication process must be carried out. The growth of the field oxide is followed by the growth of a gate oxide and the deposition of a gate material, as represented by polysilicon gate 30 in Figs. 1A and IB.

Several features of the isolation process which has been described impact its desirability and provide the motivation for the present invention. As mentioned, the growth of field oxide produces a non- planar surface in most cases because the oxidation process used results in some portion of the field oxide being above the surface of substrate 10. Although the use of the fully recessed isolation oxide process can produce a nearly planar final surface, the trenches which must be etched into the silicon substrate during such a process can result in the production of defects in the silicon when the field oxide is grown. Thus, the fully recessed process does not provide an optimal method for constructing isolation structures.

In addition, due to the formation of the "bird's beak" structure during the field oxidation stage, some encroachment of the field oxide regions into the active regions may occur. In order to prevent this encroachment from unduly impacting the operation of the finished device, the active regions must be adequately spaced. This results in an increase in the spacing required between devices as compared to what would be required if no encroachment occurred. The increased spacing reduces the packing density which can be achieved for the devices, and this can impact the size of the integrated circuit, or the degree of complexity which can be achieved for a given sized integrated circuit.

Another factor which affects the minimum spacing between adjacent active regions which can be achieved is the need to prevent leakage currents between the source/drain junctions of such regions. The significance of leakage currents is typically evaluated by measuring the breakdown voltage (drain to source) and the threshold voltage. Other factors affecting the minimum spacing include the non-linear dependence of the thickness of the oxide layer grown during field oxidation on the width of the active regions defined on the silicon nitride layer, the resolution achievable by the lithographic equipment used to define the active regions, and interactions which depend on the specific fabrication processes used. The net effect of these factors is to limit the minimum spacing, d, between active regions in Figs. 1A and IB to approximately 1 micron.

These and other disadvantages to the use of standard isolation processes are overcome by the isolation method of the present invention, which will now be explained with reference to the remaining figures. During the fabrication of an integrated circuit, regions between active areas defined on the silicon substrate are identified as locations for isolation structures. Instead of etching trenches and filling them with a dielectric material, or growing field oxide, in accordance with a first embodiment of the present invention these regions are implanted with a dose or doses of a noble gas. Noble gas implantation into silicon has been found to suppress epitaxial regrowth of the silicon, with the use of an implant equivalent to about one atomic percent of the heavier noble gases (those of atomic mass greater than helium) being preferred. At those dose levels the noble gas implant both amorphizes domains within the silicon and also prevents epitaxial regrowth of these regions. This suppression of epitaxial regrowth has been reported by P. Revesz et al. in "Epitaxial Regrowth of Ar- Implanted Amorphous Silicon", 49 J. Appl . Phys. 5199 (1978), M. Wittmer et al. in "Epitaxial Regrowth of Ne- and Kr- Implanted Amorphous Silicon", 49 J. Appl. Phys. 5207 (1978), and A. G. Cullis et al . in "Comparative Study of Annealed Neon-, Argon-, and Krypton-Ion Implantation Damage in Silicon, 49 J. Appl. Phys. 5188 (1978) .

The implant amorphizes the silicon by disrupting the silicon lattice. The high resistivity of amorphous silicon is then enhanced by the insulating character of the noble gas atoms. The presence of the noble gas also prevents the recrystallization of the lattice structure. The result is a very effective isolation structure which is capable of preventing the formation of leakage pathways within the substrate.

The isolation method of the present invention is primarily intended to be used with MOSFET devices having a nominal biasing voltage (V^) of 5 volts or less. It may also be used as an isolation technique for bipolar devices, however, junction isolation is also required for all but the most advanced devices. The method of the present invention is not limited to use with silicon but may also be used with compound semiconductors as well as mixed semiconductor structures formed in silicon, since the suppression of epitaxial regrowth is largely the result of the closed shell, non-bonding nature of the noble gases. The noble gas implant is performed by means of a standard ion implanter using techniques known in the semiconductor industry. The noble gas should be implanted to a depth sufficient to provide adequate device isolation. This depth can be roughly approximated as twice the source/drain junction depth, although it could also be deeper. As an example of the method, an Argon (Ar) implant to a depth of approximately 0.3 microns will be discussed.

A typical situation might involve two implants of Argon. Two implants are used because it is difficult to obtain a substantially uniform concentration of the noble gas with a single implant, and a uniform concentration of the implanted species is believed to assist in producing effective isolation structures. It is also possible to use other numbers of implants to achieve the desired degree of isolation. The doses and energies of the implanted species which are used depend on the concentration of the implant in the target material which is needed to produce permanent damage, and the depth of the implant required to produce adequate isolation.

A typical first implant would be at a dose of 3xl0¹⁷ Ar⁺ ions/cm² at an energy of 190 keV, followed by a second implant at a dose of lxlO¹⁷ Ar⁺ ions/cm² at an energy of 30 keV. The result of this implant sequence is shown in Fig. 2, which shows the concentration of Argon (Ar/cm³) with depth (in nanometers) into a silicon substrate.

The Argon implants can be preceded by Germanium (Ge) implants in order to preamorphize the silicon substrate and reduce the lateral damage to the silicon lattice caused by the ion implant. A possible sequence of Germanium implants would be three implants at a dose of 1 x 10¹⁵ Ge ions/cm² and energies of 100, 200, and 300 KeV. This is a useful means of preventing any damage to the silicon lattice resulting from the noble gas implant from propagating to other regions of the lattice.

The noble gas (and if desired Ge) implants are followed by a short time, low temperature furnace anneal (900 C for 30 minutes in Argon, for example) or an appropriate rapid thermal anneal (RTA) that maximizes epitaxial regrowth and minimizes outgassing of the noble gas. If desired, a shallow field oxide layer could be deposited to provide additional isolation. If the oxide layer is grown, it should be grown in dry oxygen to limit the rate of oxide formation. Capping layers of deposited silicon nitride or oxide may also be used to prevent outgassing and to protect the implanted regions. Fig. 2, which shows the concentration of an Argon gas implant as a function of depth into a silicon substrate, will be used to illustrate how the method of the present invention achieves such a high degree of device isolation. The smallest quantity of Argon is at the surface of the substrate, where it has an atomic fraction of approximately 4.4%. At a depth of 10.86 A (equal to two lattice constants) , the Argon concentration has increased by approximately 20%. Assuming the surface concentration is extended for two lattice spacings, approximately one (1) in twenty-five (25) silicon atoms in the substrate are displaced.

There are effectively eight (8) silicon atoms per unit cell in the bulk material. A domain can be defined as comprised of eight unit cells linked together to form a cube of length 10.86 A on a side. The depth dimension can be ignored because the Argon concentration rises quickly (by over an order of magnitude) in the first 30 nm of the surface. If the length of the desired isolation region is 700 nm, and this represents the shortest pathway across the region, then there are approximately 645 domains contained within this length. The probability that a leakage pathway can remain intact in this region is given by the product:

P = (1 - .044)⁶⁴⁵ = (0.956)⁶⁴⁵ = 2.485 x 10^"13. This corresponds to a relative resistivity factor with respect to the undamaged (unimplanted) region of:

f_/> = damaged / P undamaged = l / ^p = . 0 X 10 .

This implies that at low potentials, leakage currents can be expected to be negligible.

Although an Argon implant has been used as an example in describing one of the embodiments of the present invention, mixed noble gas implants are also possible. For example, Argon can be used for the deeper portions of the isolation regions and Krypton can be implanted near the surface to act as a more permanent amorphizer and to block the out-flow of Argon. Other species, such as Oxygen or Nitrogen, may also be used to alter the properties of the permanent amorphous region.

Another method for producing highly planar isolation regions will now be discussed with reference to Figure 3, which depicts a second embodiment of the present invention. It has been discovered that germanium concentrations higher than seven (7) atomic percent suppress the epitaxial regrowth in the implanted regions of Si or SiGe alloys, producing regions of high resistivity. This phenomenon has been investigated and reported by E.

Demirlioglu et al . in "Residual Damage in Heavily Ge- Doped Silicon", MRS 1992 Fall Meeting, by S . Im et al . in "Defect-Minimized SiGe Layer Forming in Ion Beam Synthesis", MRS 1992 Fall Meeting, and by Q. Z. Hong et al . in "Solid Phase Epitaxy of Stressed and Stress-Relaxed Ge-Si Alloys", J. Appl. Phys. 1768 (1992) . The resistivity of these regions can be further increased by additional oxygen or noble gas implants.

The germanium implant is performed by means of a standard ion implanter using techniques known in the semiconductor industry. Germanium should be implanted to a depth sufficient to provide adequate device isolation. This depth can be roughly approximated as twice the source/drain junction depth, although it could also be deeper. As an example of this embodiment of the present invention, a germanium implantation that is capable of providing a 0.2 micron isolation depth will be discussed.

The energy and dosages of the germanium implants should be adjusted so that the germanium concentration at the isolation depth is equal to or higher than seven atomic percent, and the germanium concentration between the surface and the isolation depth should be between one and seven atomic percent. In order to satisfy these requirements, two germanium implants may be used. It is also possible to use other numbers of implants to obtain the desired concentration distribution of germanium.

A typical first germanium implant would be one at a dose of 6 x 10¹⁶ Ge ions/cm² with an energy of 280 KeV, followed by a second implant at a dose of 1 x 10 Ge ions/cm with an energy of 30 KeV. The result of these implants is shown in Figure 3, which is a graph showing the concentration of germanium as a function of depth into a silicon substrate, where the germanium has been implanted in accordance with the method of the present invention.

The germanium implants can be followed by noble gas or oxygen implants in order to increase the resistivity of the isolation region. The energy of these subsequent noble gas or oxygen implants should be adjusted so that the implanted species is confined to the isolation region. Since noble gas or oxygen concentrations of one-half to one (0.5 to 1) atomic percent are expected to be sufficient to achieve the desired high level of resistivity, the doses of these implants should be adjusted accordingly. For example, a typical Argon implant would be done at a

1A _? dose of 1 x 10 At ions/cm with an energy of 60 KeV. This implantation is shown as a dotted line in Figure 3.

After the implants, a thin cap layer, such as a 50 nanometer thick silicon nitride layer may be deposited over the implanted region(s) to protect them during later heat treatments. The cap layer should be a non- or slowly-oxidizing material which acts to block the diffusion of oxygen to the surface of the isolation region. This is because oxidation of germanium-implanted silicon would consume the silicon only, leaving conductive germanium at the surface and thereby destroying the isolation properties of the region.

Figures 4A-4H show a typical process flow for the fabrication of a CMOS device having isolation regions which are formed according to either embodiment of the present invention. Figure 4A shows a substrate 100 on which has been grown a thin layer of pad or buffer oxide 105. Standard techniques based on the use of photoresist and a photolithographic mask are then used to define the location for the subsequent implant of a dopant 110 which will be used to form an n-well for the device. The remaining resist 115 is then removed. This is followed, as shown in Fig. 4B, by a drive-in step which results in the formation of the desired n-well 120 structure. A new layer of photoresist is then applied as shown in Fig. 4C, followed by the use of standard photolithographic techniques to define one or more isolation regions 125. This is followed by one or more noble gas and/or germanium implants 130, performed in accordance with the method of the present invention. The remaining photoresist 122 is then removed. The noble gas and/or germanium implant (s) 130 are followed by the application of another layer of photoresist which is again patterned by means of standard photolithographic techniques to define the location(s) for p-well or field dopant implants 135, as shown in Fig. 4D. The remaining resist 140 is then removed from substrate 100. A cap layer 145 may then be applied (Fig. 4E) , followed by the use of standard photolithographic techniques to define the cap layer over the isolation region(s), as shown in Fig. 4F. A layer of gate dielectric (not shown) is then grown or deposited. A drive-in or anneal step may then follow, causing the diffusion of the p-type dopants into substrate 100, resulting in the formation of the desired p-well 150 structure, as shown in Fig. 4F. Photolithographic techniques are then used to define those regions in which gate structures will be formed. One or more gate structures are then formed by the deposition of polysilicon 155, as shown in Fig. 4G. The final CMOS device architecture shown in Fig. 4H results by using the standard steps to isolate the source and drain contacts and form the source and drain regions.

Figures 5A and 5B are a plan and cross- sectional view, respectively, of an integrated circuit 1 which has been fabricated using the isolation technique of the present invention. As discussed with reference to Figures 4A-4H, the integrated circuit is fabricated on a substrate 10 which is typically made of silicon. A lithography step is again used to define active regions 12 and 14 of the device. After definition of active regions 12 and 14, a channel-stop implant is performed. Again, as was discussed with reference to Figures 1A and IB, typical dopants are Boron and Boron Fluoride which are implanted at a dose of 1 to 10 x 10¹³ ions/cm² at an energy of 30 to 100 KeV. As in Figure IB, elements 16, 18, and 20 are channel-stop implants. However, now instead of growing field oxide in the regions between the active regions, an implant of a noble gas (which as noted, may be preceded by an implant of germanium) or germanium is performed in accordance with the method of the present invention. The noble gas or germanium implant results in the production of isolation structures beneath the surface of substrate 10. These isolation structures are depicted as elements 32, 34, and 36 in Figure 5B. Because the isolation method of the present invention does not require the growth of an oxide structure above the surface of substrate 10, the result is a highly planar surface on which subsequent fabrication steps may easily be carried out. The production of the isolation structures is followed by the growth of a gate oxide and the deposition of a gate material, as represented by polysilicon gate 30 in Figures 5A and 5B. The isolation methods of the present invention provides several advantages over other, currently used methods. The lengthy field oxidation cycles associated with standard oxide isolation techniques are avoided; this reduces the total thermal budget for the fabrication process as well as the fabrication time. Other aspects of conventional isolation processes are also avoided: the use of a nitride oxidation mask, the existence of the Kooi effect, and the use of a sacrificial gate oxide layer. In addition, higher dose (1 to 10 x 10¹⁸ ions/cm²) oxygen implants and very high temperature (1200 to 1300 degrees C) anneals used in silicon-on- insulator processes are avoided.

Another benefit is that the regions implanted with noble gas act as gettering centers, preventing leakage currents due to the presence of heavy metals, interstitials, and dopants. In addition, the problem of Boron segregation into the isolation regions in NFET and NPN bipolar devices is eliminated because there is no longer an oxide growth step which depletes the implanted Boron.

A final and perhaps greatest benefit to the methods of the present invention over LOCOS isolation processes is that the separation distance between active device regions, d* in Figures 5A and 5B, can be reduced to the limit of the capabilities of the lithographic equipment employed in the process. This is in contrast to a minimum separation distance which depends on both the lithographic equipment and the amount of encroachment of the isolation regions into the active device regions, such as is the case with LOCOS isolation processes. This allows the packing density of devices to be increased over that obtainable using conventional LOCOS isolation techniques.

The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding equivalents of the features shown and described, or portions thereof, it being recognized that various modifications are possible within the scope of the invention claimed.

Claims

We claim:

1. A method for electrically isolating individual active device regions of an integrated circuit, wherein the active device regions are fabricated on a substrate, the method comprising: identifying isolation regions on the substrate in which isolation structures are to be formed, wherein the isolation structures are intended to prevent the formation of electrical connections between the active device regions; implanting a noble gas into the isolation regions which are to be formed into isolation structures, wherein the noble gas implant is performed so as to produce a concentration of approximately one atomic percent or greater of the noble gas within the substrate, and further, wherein the noble gas has an atomic mass greater than helium; and performing an anneal step on the substrate, wherein the anneal step maximizes epitaxial regrowth and minimizes outgassing of the noble gas implant.

2. The isolation method of claim 1, wherein prior to the implant of the noble gas, the method further comprises: implanting germanium into the identified isolation regions of the substrate to preamorphize the substrate material.

3. The isolation method of claim 1, wherein the noble gas is selected from the group consisting of Argon, Neon, Krypton, and Xenon.

4. The isolation method of claim 1, wherein the anneal step is a short time, low temperature furnace anneal that maximizes epitaxial regrowth and minimizes outgassing of the noble gas.

5. The isolation method of claim 1, wherein the anneal step is a rapid thermal anneal that maximizes epitaxial regrowth and minimizes outgassing of the noble gas.

6. The isolation method of claim 1, wherein the noble gas is implanted to a depth equal to approximately twice the desired source-drain junction depth of the device.

7. The isolation method of claim 1, wherein a plurality of noble gas implants are used.

8. A method for electrically isolating individual microelectronic devices, wherein the devices are fabricated on a substrate, the method comprising: identifying isolation regions on the substrate in which isolation structures are to be formed, wherein the isolation structures are intended to prevent the formation of electrical connections between the individual devices; implanting a noble gas into the isolation regions which are to be formed into isolation structures, wherein the noble gas implant is performed so as to produce a concentration of approximately one atomic percent or greater of the noble gas within the substrate, and further, wherein the noble gas has an atomic mass greater than helium; and perfor ing an anneal step on the substrate, wherein the anneal step maximizes epitaxial regrowth and minimizes outgassing of the noble gas implant.

9. The isolation method of claim 8, wherein prior to the implant of the noble gas, the method further comprises: implanting germanium into the identified isolation regions of the substrate to preamorphize the substrate material.

10. The isolation method of claim 8, wherein the noble gas is selected from the group consisting of Argon, Neon, Krypton, and Xenon.

11. The isolation method of claim 8, wherein the anneal step is a short time, low temperature furnace anneal that maximizes epitaxial regrowth and minimizes outgassing of the noble gas.

12. The isolation method of claim 8, wherein the anneal step is a rapid thermal anneal that maximizes epitaxial regrowth and minimizes outgassing of the noble gas.

13. The isolation method of claim 8, wherein a plurality of noble gas implants are used.

14. A method for electrically isolating individual active device regions of an integrated circuit, wherein the active device regions are fabricated on a substrate, the method comprising: identifying isolation regions on the substrate in which isolation structures are to be formed, wherein the isolation structures are intended to prevent the formation of electrical connections between the active device regions; implanting germanium into the isolation regions which are to be formed into isolation structures, wherein the germanium implant is performed so as to produce a concentration of approximately seven atomic percent or greater of germanium within the substrate at the depth of the isolation structure; and performing an anneal step on the substrate, wherein the anneal step maximizes epitaxial regrowth.

15. The isolation method of claim 14, wherein the anneal step is a short time, low temperature furnace anneal that maximizes epitaxial regrowth.

16. The isolation method of claim 14, wherein the anneal step is a rapid thermal anneal that maximizes epitaxial regrowth.

17. The isolation method of claim 14, wherein the germanium is implanted to a depth equal to approximately twice the source/drain junction depth of the device.

18. The isolation method of claim 14, wherein a plurality of germanium implants are used.

19. A method for electrically isolating individual microelectronic devices, wherein the devices are fabricated on a substrate, the method comprising: identifying isolation regions on the substrate in which isolation structures are to be formed, wherein the isolation structures are intended to prevent the formation of electrical connections between the individual devices; implanting germanium into the isolation regions which are to be formed into isolation structures, wherein the germanium implant is performed so as to produce a concentration of approximately seven atomic percent or greater of germanium within the substrate at the depth of the isolation structure, and performing an anneal step on the substrate, wherein the anneal step maximizes epitaxial regrowth and minimizes outgassing of the noble gas implant.

20. The isolation method of claim 19, wherein the anneal step is a short time, low temperature furnace anneal that maximizes epitaxial regrowth.

21. The isolation method of claim 19, wherein the anneal step is a rapid thermal anneal that maximizes epitaxial regrowth.

22. The isolation method of claim 19, wherein a plurality of germanium implants are used.