AU5560499A - Integrated circuit trenched features and method of producing same - Google Patents

Integrated circuit trenched features and method of producing same

Info

Publication number
AU5560499A
AU5560499A AU55604/99A AU5560499A AU5560499A AU 5560499 A AU5560499 A AU 5560499A AU 55604/99 A AU55604/99 A AU 55604/99A AU 5560499 A AU5560499 A AU 5560499A AU 5560499 A AU5560499 A AU 5560499A
Authority
AU
Australia
Prior art keywords
trenched
features
integrated circuit
producing same
producing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU55604/99A
Other languages
English (en)
Inventor
Avery N. Goldstein
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of AU5560499A publication Critical patent/AU5560499A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
AU55604/99A 1998-08-14 1999-08-13 Integrated circuit trenched features and method of producing same Abandoned AU5560499A (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US9661698P 1998-08-14 1998-08-14
US60096616 1998-08-14
US09/373,295 US6277740B1 (en) 1998-08-14 1999-08-12 Integrated circuit trenched features and method of producing same
US09373295 1999-08-12
PCT/US1999/018430 WO2000010197A1 (en) 1998-08-14 1999-08-13 Integrated circuit trenched features and method of producing same

Publications (1)

Publication Number Publication Date
AU5560499A true AU5560499A (en) 2000-03-06

Family

ID=26791884

Family Applications (1)

Application Number Title Priority Date Filing Date
AU55604/99A Abandoned AU5560499A (en) 1998-08-14 1999-08-13 Integrated circuit trenched features and method of producing same

Country Status (5)

Country Link
US (3) US6277740B1 (https=)
JP (1) JP2002522920A (https=)
KR (1) KR100653337B1 (https=)
AU (1) AU5560499A (https=)
WO (1) WO2000010197A1 (https=)

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JP2001513697A (ja) 1997-02-24 2001-09-04 スーペリア マイクロパウダーズ リミテッド ライアビリティ カンパニー エアロゾル法及び装置、粒子製品、並びに該粒子製品から製造される電子装置
US6277740B1 (en) * 1998-08-14 2001-08-21 Avery N. Goldstein Integrated circuit trenched features and method of producing same
US6780765B2 (en) * 1998-08-14 2004-08-24 Avery N. Goldstein Integrated circuit trenched features and method of producing same
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US20060163744A1 (en) * 2005-01-14 2006-07-27 Cabot Corporation Printable electrical conductors
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US20060190917A1 (en) * 2005-01-14 2006-08-24 Cabot Corporation System and process for manufacturing application specific printable circuits (ASPC'S) and other custom electronic devices
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US20060213957A1 (en) * 2005-03-26 2006-09-28 Addington Cary G Conductive trace formation via wicking action
US7655081B2 (en) * 2005-05-13 2010-02-02 Siluria Technologies, Inc. Plating bath and surface treatment compositions for thin film deposition
US7902639B2 (en) * 2005-05-13 2011-03-08 Siluria Technologies, Inc. Printable electric circuits, electronic components and method of forming the same
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US7625814B2 (en) * 2006-03-29 2009-12-01 Asm Nutool, Inc. Filling deep features with conductors in semiconductor manufacturing
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US8506849B2 (en) * 2008-03-05 2013-08-13 Applied Nanotech Holdings, Inc. Additives and modifiers for solvent- and water-based metallic conductive inks
US9730333B2 (en) 2008-05-15 2017-08-08 Applied Nanotech Holdings, Inc. Photo-curing process for metallic inks
US8647979B2 (en) 2009-03-27 2014-02-11 Applied Nanotech Holdings, Inc. Buffer layer to enhance photo and/or laser sintering
US8422197B2 (en) 2009-07-15 2013-04-16 Applied Nanotech Holdings, Inc. Applying optical energy to nanoparticles to produce a specified nanostructure
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Also Published As

Publication number Publication date
US6774036B2 (en) 2004-08-10
US6277740B1 (en) 2001-08-21
JP2002522920A (ja) 2002-07-23
KR100653337B1 (ko) 2006-12-01
US20020006723A1 (en) 2002-01-17
US20040023488A1 (en) 2004-02-05
KR20010072473A (ko) 2001-07-31
WO2000010197A1 (en) 2000-02-24

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase