US4593363A
(en)
|
1983-08-12 |
1986-06-03 |
International Business Machines Corporation |
Simultaneous placement and wiring for VLSI chips
|
US4615011A
(en)
*
|
1983-12-19 |
1986-09-30 |
Ibm |
Iterative method for establishing connections and resulting product
|
JPS63225869A
(ja)
|
1986-10-09 |
1988-09-20 |
Nec Corp |
配線経路探索方式
|
US5097422A
(en)
|
1986-10-10 |
1992-03-17 |
Cascade Design Automation Corporation |
Method and apparatus for designing integrated circuits
|
DE58907307D1
(de)
|
1988-11-02 |
1994-04-28 |
Siemens Ag |
Verfahren zur plazierung von modulen auf einem träger.
|
JPH03188650A
(ja)
|
1989-12-18 |
1991-08-16 |
Hitachi Ltd |
配線経路処理方法、配線経路処理システム、及び半導体集積回路
|
US5598344A
(en)
|
1990-04-06 |
1997-01-28 |
Lsi Logic Corporation |
Method and system for creating, validating, and scaling structural description of electronic device
|
US5634093A
(en)
|
1991-01-30 |
1997-05-27 |
Kabushiki Kaisha Toshiba |
Method and CAD system for designing wiring patterns using predetermined rules
|
US5532934A
(en)
|
1992-07-17 |
1996-07-02 |
Lsi Logic Corporation |
Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions
|
US5618744A
(en)
|
1992-09-22 |
1997-04-08 |
Fujitsu Ltd. |
Manufacturing method and apparatus of a semiconductor integrated circuit device
|
US5566078A
(en)
|
1993-05-26 |
1996-10-15 |
Lsi Logic Corporation |
Integrated circuit cell placement using optimization-driven clustering
|
SG68564A1
(en)
|
1994-01-25 |
1999-11-16 |
Advantage Logic Inc |
Apparatus and method for partitioning resources for interconnections
|
US5914887A
(en)
|
1994-04-19 |
1999-06-22 |
Lsi Logic Corporation |
Congestion based cost factor computing apparatus for integrated circuit physical design automation system
|
US5495419A
(en)
|
1994-04-19 |
1996-02-27 |
Lsi Logic Corporation |
Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing
|
US6155725A
(en)
|
1994-04-19 |
2000-12-05 |
Lsi Logic Corporation |
Cell placement representation and transposition for integrated circuit physical design automation system
|
JP2687879B2
(ja)
|
1994-05-26 |
1997-12-08 |
日本電気株式会社 |
自動配線方法
|
JP3113153B2
(ja)
|
1994-07-26 |
2000-11-27 |
株式会社東芝 |
多層配線構造の半導体装置
|
JPH0851159A
(ja)
|
1994-08-05 |
1996-02-20 |
Mitsubishi Electric Corp |
半導体集積回路
|
US5587923A
(en)
|
1994-09-07 |
1996-12-24 |
Lsi Logic Corporation |
Method for estimating routability and congestion in a cell placement for integrated circuit chip
|
US5777360A
(en)
|
1994-11-02 |
1998-07-07 |
Lsi Logic Corporation |
Hexagonal field programmable gate array architecture
|
US6407434B1
(en)
*
|
1994-11-02 |
2002-06-18 |
Lsi Logic Corporation |
Hexagonal architecture
|
US5973376A
(en)
|
1994-11-02 |
1999-10-26 |
Lsi Logic Corporation |
Architecture having diamond shaped or parallelogram shaped cells
|
US5742086A
(en)
|
1994-11-02 |
1998-04-21 |
Lsi Logic Corporation |
Hexagonal DRAM array
|
US5822214A
(en)
|
1994-11-02 |
1998-10-13 |
Lsi Logic Corporation |
CAD for hexagonal architecture
|
US5578840A
(en)
|
1994-11-02 |
1996-11-26 |
Lis Logic Corporation |
Microelectronic integrated circuit structure and method using three directional interconnect routing based on hexagonal geometry
|
US5811863A
(en)
|
1994-11-02 |
1998-09-22 |
Lsi Logic Corporation |
Transistors having dynamically adjustable characteristics
|
JP3351651B2
(ja)
|
1995-04-07 |
2002-12-03 |
富士通株式会社 |
会話型回路設計装置
|
US5650653A
(en)
|
1995-05-10 |
1997-07-22 |
Lsi Logic Corporation |
Microelectronic integrated circuit including triangular CMOS "nand" gate device
|
US5981384A
(en)
|
1995-08-14 |
1999-11-09 |
Micron Technology, Inc. |
Method of intermetal dielectric planarization by metal features layout modification
|
US5637920A
(en)
|
1995-10-04 |
1997-06-10 |
Lsi Logic Corporation |
High contact density ball grid array package for flip-chips
|
US5757656A
(en)
|
1995-12-20 |
1998-05-26 |
Mentor Graphics |
Method for routing breakouts
|
US5663891A
(en)
|
1996-04-03 |
1997-09-02 |
Cadence Design Systems, Inc. |
Optimization of multiple performance criteria of integrated circuits by expanding a constraint graph with subgraphs derived from multiple PWL convex cost functions
|
US5838583A
(en)
|
1996-04-12 |
1998-11-17 |
Cadence Design Systems, Inc. |
Optimized placement and routing of datapaths
|
US5798936A
(en)
|
1996-06-21 |
1998-08-25 |
Avant| Corporation |
Congestion-driven placement method and computer-implemented integrated-circuit design tool
|
US6067409A
(en)
|
1996-06-28 |
2000-05-23 |
Lsi Logic Corporation |
Advanced modular cell placement system
|
US6035108A
(en)
|
1996-10-17 |
2000-03-07 |
Nec Corporation |
Figure layout compaction method and compaction device
|
US6209123B1
(en)
|
1996-11-01 |
2001-03-27 |
Motorola, Inc. |
Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors
|
US5980093A
(en)
|
1996-12-04 |
1999-11-09 |
Lsi Logic Corporation |
Integrated circuit layout routing using multiprocessing
|
US5898597A
(en)
|
1997-02-11 |
1999-04-27 |
Lsi Logic Corporation |
Integrated circuit floor plan optimization system
|
JP3063828B2
(ja)
|
1997-03-27 |
2000-07-12 |
日本電気株式会社 |
集積回路の自動概略配線方法
|
US6070108A
(en)
|
1997-08-06 |
2000-05-30 |
Lsi Logic Corporation |
Method and apparatus for congestion driven placement
|
US6123736A
(en)
|
1997-08-06 |
2000-09-26 |
Lsi Logic Corporation |
Method and apparatus for horizontal congestion removal
|
US6058254A
(en)
|
1997-08-06 |
2000-05-02 |
Lsi Logic Corporation |
Method and apparatus for vertical congestion removal
|
US6068662A
(en)
|
1997-08-06 |
2000-05-30 |
Lsi Logig Corporation |
Method and apparatus for congestion removal
|
US6330707B1
(en)
|
1997-09-29 |
2001-12-11 |
Matsushita Electric Industrial Co., Ltd. |
Automatic routing method
|
JP4128251B2
(ja)
|
1997-10-23 |
2008-07-30 |
富士通株式会社 |
配線密度予測方法およびセル配置装置
|
US6128767A
(en)
|
1997-10-30 |
2000-10-03 |
Chapman; David C. |
Polygon representation in an integrated circuit layout
|
US6134702A
(en)
|
1997-12-16 |
2000-10-17 |
Lsi Logic Corporation |
Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints
|
US6249902B1
(en)
|
1998-01-09 |
2001-06-19 |
Silicon Perspective Corporation |
Design hierarchy-based placement
|
US6286128B1
(en)
|
1998-02-11 |
2001-09-04 |
Monterey Design Systems, Inc. |
Method for design optimization using logical and physical information
|
JP3120838B2
(ja)
|
1998-03-24 |
2000-12-25 |
日本電気株式会社 |
図形レイアウト圧縮システム及び図形レイアウト圧縮方法
|
JP3070679B2
(ja)
|
1998-03-24 |
2000-07-31 |
日本電気株式会社 |
図形レイアウト圧縮システム及び図形レイアウト圧縮方法
|
US6289495B1
(en)
|
1998-04-17 |
2001-09-11 |
Lsi Logic Corporation |
Method and apparatus for local optimization of the global routing
|
US6175950B1
(en)
|
1998-04-17 |
2001-01-16 |
Lsi Logic Corporation |
Method and apparatus for hierarchical global routing descend
|
US6253363B1
(en)
|
1998-04-17 |
2001-06-26 |
Lsi Logic Corporation |
Net routing using basis element decomposition
|
US6247167B1
(en)
|
1998-04-17 |
2001-06-12 |
Lsi Logic Corporation |
Method and apparatus for parallel Steiner tree routing
|
US6324674B2
(en)
|
1998-04-17 |
2001-11-27 |
Lsi Logic Corporation |
Method and apparatus for parallel simultaneous global and detail routing
|
US6230306B1
(en)
|
1998-04-17 |
2001-05-08 |
Lsi Logic Corporation |
Method and apparatus for minimization of process defects while routing
|
JP3564295B2
(ja)
|
1998-05-22 |
2004-09-08 |
富士通株式会社 |
セル配置装置及び方法並びにセル配置プログラムを記録したコンピュータ読取り可能な記録媒体
|
US6442743B1
(en)
|
1998-06-12 |
2002-08-27 |
Monterey Design Systems |
Placement method for integrated circuit design using topo-clustering
|
US6262487B1
(en)
|
1998-06-23 |
2001-07-17 |
Kabushiki Kaisha Toshiba |
Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method
|
US6412102B1
(en)
|
1998-07-22 |
2002-06-25 |
Lsi Logic Corporation |
Wire routing optimization
|
US6324675B1
(en)
|
1998-12-18 |
2001-11-27 |
Synopsys, Inc. |
Efficient iterative, gridless, cost-based fine router for computer controlled integrated circuit design
|
JP4227304B2
(ja)
|
1998-12-22 |
2009-02-18 |
富士通株式会社 |
概略配線方法及び装置並びに概略配線プログラムを格納した記録媒体
|
JP3077757B2
(ja)
|
1999-02-02 |
2000-08-14 |
日本電気株式会社 |
レイアウトコンパクション方法及びレイアウトコンパクション装置
|
US6295634B1
(en)
|
1999-04-02 |
2001-09-25 |
International Business Machines Corporation |
Wiring design apparatus, wiring determination apparatus and methods thereof
|
US6327693B1
(en)
|
1999-04-08 |
2001-12-04 |
Chung-Kuan Cheng |
Interconnect delay driven placement and routing of an integrated circuit design
|
JP2001024153A
(ja)
|
1999-07-06 |
2001-01-26 |
Mitsubishi Electric Corp |
集積回路装置におけるセルの配置方法
|
US6415422B1
(en)
|
1999-09-17 |
2002-07-02 |
International Business Machines Corporation |
Method and system for performing capacitance estimations on an integrated circuit design routed by a global routing tool
|
US6405358B1
(en)
|
1999-10-08 |
2002-06-11 |
Agilent Technologies, Inc. |
Method for estimating and displaying wiring congestion
|
JP3822009B2
(ja)
|
1999-11-17 |
2006-09-13 |
株式会社東芝 |
自動設計方法、露光用マスクセット、半導体集積回路装置、半導体集積回路装置の製造方法、および自動設計プログラムを記録した記録媒体
|
US6401234B1
(en)
|
1999-12-17 |
2002-06-04 |
International Business Machines Corporation |
Method and system for re-routing interconnects within an integrated circuit design having blockages and bays
|
JP3548070B2
(ja)
|
2000-01-26 |
2004-07-28 |
インターナショナル・ビジネス・マシーンズ・コーポレーション |
多端子ネットを自動的に発生する方法及び装置並びに多端子ネット自動発生方法を実行するためのプログラムを記憶したプログラム記憶媒体
|
US6519751B2
(en)
|
2000-03-31 |
2003-02-11 |
Intel Corporation |
Method and apparatus for accurate crosspoint allocation in VLSI area routing
|
US6405357B1
(en)
*
|
2000-05-02 |
2002-06-11 |
Advanced Semiconductor Engineering, Inc. |
Method for positioning bond pads in a semiconductor die
|
US6473891B1
(en)
|
2000-05-03 |
2002-10-29 |
Lsi Logic Corporation |
Wire routing to control skew
|
US6543043B1
(en)
|
2000-06-01 |
2003-04-01 |
Cadence Design Systems, Inc. |
Inter-region constraint-based router for use in electronic design automation
|
US6567967B2
(en)
|
2000-09-06 |
2003-05-20 |
Monterey Design Systems, Inc. |
Method for designing large standard-cell base integrated circuits
|
US7024650B2
(en)
|
2000-12-06 |
2006-04-04 |
Cadence Design Systems, Inc. |
Method and apparatus for considering diagonal wiring in placement
|
US7055120B2
(en)
|
2000-12-06 |
2006-05-30 |
Cadence Design Systems, Inc. |
Method and apparatus for placing circuit modules
|
US7003754B2
(en)
*
|
2000-12-07 |
2006-02-21 |
Cadence Design Systems, Inc. |
Routing method and apparatus that use of diagonal routes
|
US6957410B2
(en)
|
2000-12-07 |
2005-10-18 |
Cadence Design Systems, Inc. |
Method and apparatus for adaptively selecting the wiring model for a design region
|
US6516455B1
(en)
*
|
2000-12-06 |
2003-02-04 |
Cadence Design Systems, Inc. |
Partitioning placement method using diagonal cutlines
|
US7080336B2
(en)
|
2000-12-06 |
2006-07-18 |
Cadence Design Systems, Inc. |
Method and apparatus for computing placement costs
|
US6826737B2
(en)
|
2000-12-06 |
2004-11-30 |
Cadence Design Systems, Inc. |
Recursive partitioning placement method and apparatus
|
US7073150B2
(en)
|
2000-12-07 |
2006-07-04 |
Cadence Design Systems, Inc. |
Hierarchical routing method and apparatus that use diagonal routes
|
US6738960B2
(en)
*
|
2001-01-19 |
2004-05-18 |
Cadence Design Systems, Inc. |
Method and apparatus for producing sub-optimal routes for a net by generating fake configurations
|
US6915501B2
(en)
|
2001-01-19 |
2005-07-05 |
Cadence Design Systems, Inc. |
LP method and apparatus for identifying routes
|
US6480991B1
(en)
|
2001-04-11 |
2002-11-12 |
International Business Machines Corporation |
Timing-driven global placement based on geometry-aware timing budgets
|
JP2002312414A
(ja)
|
2001-04-13 |
2002-10-25 |
Toshiba Corp |
半導体集積回路装置のレイアウト設計システム、配線設計方法、配線設計プログラム及び半導体集積回路装置の製造方法
|
US6590289B2
(en)
|
2001-05-17 |
2003-07-08 |
Lsi Logic Corporation |
Hexadecagonal routing
|
US6795958B2
(en)
|
2001-08-23 |
2004-09-21 |
Cadence Design Systems, Inc. |
Method and apparatus for generating routes for groups of related node configurations
|
US7143382B2
(en)
|
2001-08-23 |
2006-11-28 |
Cadence Design Systems, Inc. |
Method and apparatus for storing routes
|
US7398498B2
(en)
|
2001-08-23 |
2008-07-08 |
Cadence Design Systems, Inc. |
Method and apparatus for storing routes for groups of related net configurations
|
US6931616B2
(en)
*
|
2001-08-23 |
2005-08-16 |
Cadence Design Systems, Inc. |
Routing method and apparatus
|
US6618849B2
(en)
*
|
2001-08-23 |
2003-09-09 |
Cadence Design Systems, Inc. |
Method and apparatus for identifying routes for nets
|
US7155697B2
(en)
*
|
2001-08-23 |
2006-12-26 |
Cadence Design Systems, Inc. |
Routing method and apparatus
|