AU2001266798A1 - Method for etching dual damascene structures in organosilicate glass - Google Patents
Method for etching dual damascene structures in organosilicate glassInfo
- Publication number
- AU2001266798A1 AU2001266798A1 AU2001266798A AU6679801A AU2001266798A1 AU 2001266798 A1 AU2001266798 A1 AU 2001266798A1 AU 2001266798 A AU2001266798 A AU 2001266798A AU 6679801 A AU6679801 A AU 6679801A AU 2001266798 A1 AU2001266798 A1 AU 2001266798A1
- Authority
- AU
- Australia
- Prior art keywords
- dual damascene
- organosilicate glass
- damascene structures
- etching dual
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000009977 dual effect Effects 0.000 title 1
- 238000005530 etching Methods 0.000 title 1
- 239000011521 glass Substances 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/318—Inorganic layers composed of nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/318—Inorganic layers composed of nitrides
- H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09608119 | 2000-06-30 | ||
US09/608,119 US6410437B1 (en) | 2000-06-30 | 2000-06-30 | Method for etching dual damascene structures in organosilicate glass |
PCT/US2001/018626 WO2002003454A2 (en) | 2000-06-30 | 2001-06-08 | Method for etching dual damascene structures in organosilicate glass |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2001266798A1 true AU2001266798A1 (en) | 2002-01-14 |
Family
ID=24435120
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001266798A Abandoned AU2001266798A1 (en) | 2000-06-30 | 2001-06-08 | Method for etching dual damascene structures in organosilicate glass |
Country Status (9)
Country | Link |
---|---|
US (1) | US6410437B1 (ko) |
EP (1) | EP1295330A2 (ko) |
JP (1) | JP5178983B2 (ko) |
KR (1) | KR100787847B1 (ko) |
CN (2) | CN100481432C (ko) |
AU (1) | AU2001266798A1 (ko) |
SG (1) | SG145555A1 (ko) |
TW (1) | TW516176B (ko) |
WO (1) | WO2002003454A2 (ko) |
Families Citing this family (39)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4381526B2 (ja) * | 1999-10-26 | 2009-12-09 | 東京エレクトロン株式会社 | プラズマエッチング方法 |
US6764958B1 (en) * | 2000-07-28 | 2004-07-20 | Applied Materials Inc. | Method of depositing dielectric films |
US6531407B1 (en) * | 2000-08-31 | 2003-03-11 | Micron Technology, Inc. | Method, structure and process flow to reduce line-line capacitance with low-K material |
US20020064951A1 (en) * | 2000-11-30 | 2002-05-30 | Eissa Mona M. | Treatment of low-k dielectric films to enable patterning of deep submicron features |
EP1233449A3 (en) * | 2001-02-15 | 2006-03-01 | Interuniversitair Micro-Elektronica Centrum | A method of fabricating a semiconductor device |
US6537733B2 (en) * | 2001-02-23 | 2003-03-25 | Applied Materials, Inc. | Method of depositing low dielectric constant silicon carbide layers |
US7311852B2 (en) * | 2001-03-30 | 2007-12-25 | Lam Research Corporation | Method of plasma etching low-k dielectric materials |
US6605540B2 (en) * | 2001-07-09 | 2003-08-12 | Texas Instruments Incorporated | Process for forming a dual damascene structure |
US7183201B2 (en) * | 2001-07-23 | 2007-02-27 | Applied Materials, Inc. | Selective etching of organosilicate films over silicon oxide stop etch layers |
US6762127B2 (en) * | 2001-08-23 | 2004-07-13 | Yves Pierre Boiteux | Etch process for dielectric materials comprising oxidized organo silane materials |
US6656837B2 (en) | 2001-10-11 | 2003-12-02 | Applied Materials, Inc. | Method of eliminating photoresist poisoning in damascene applications |
US6573175B1 (en) * | 2001-11-30 | 2003-06-03 | Micron Technology, Inc. | Dry low k film application for interlevel dielectric and method of cleaning etched features |
US20030181034A1 (en) * | 2002-03-19 | 2003-09-25 | Ping Jiang | Methods for forming vias and trenches with controlled SiC etch rate and selectivity |
JP3516446B2 (ja) | 2002-04-26 | 2004-04-05 | 東京応化工業株式会社 | ホトレジスト剥離方法 |
KR100462759B1 (ko) * | 2002-05-06 | 2004-12-20 | 동부전자 주식회사 | 확산 장벽층을 갖는 금속 배선 및 그 제조 방법 |
US6525428B1 (en) * | 2002-06-28 | 2003-02-25 | Advance Micro Devices, Inc. | Graded low-k middle-etch stop layer for dual-inlaid patterning |
JP4282054B2 (ja) * | 2002-09-09 | 2009-06-17 | 東京応化工業株式会社 | デュアルダマシン構造形成プロセスに用いられる洗浄液および基板の処理方法 |
US6913994B2 (en) * | 2003-04-09 | 2005-07-05 | Agency For Science, Technology And Research | Method to form Cu/OSG dual damascene structure for high performance and reliable interconnects |
JP4571785B2 (ja) * | 2003-05-30 | 2010-10-27 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US7276409B2 (en) * | 2003-06-24 | 2007-10-02 | Micron Technology, Inc. | Method of forming a capacitor |
US7256134B2 (en) * | 2003-08-01 | 2007-08-14 | Applied Materials, Inc. | Selective etching of carbon-doped low-k dielectrics |
US20050077629A1 (en) * | 2003-10-14 | 2005-04-14 | International Business Machines Corporation | Photoresist ash process with reduced inter-level dielectric ( ILD) damage |
US7081407B2 (en) * | 2003-12-16 | 2006-07-25 | Lam Research Corporation | Method of preventing damage to porous low-k materials during resist stripping |
US7153778B2 (en) * | 2004-02-20 | 2006-12-26 | Micron Technology, Inc. | Methods of forming openings, and methods of forming container capacitors |
US7078350B2 (en) * | 2004-03-19 | 2006-07-18 | Lam Research Corporation | Methods for the optimization of substrate etching in a plasma processing system |
JP4515309B2 (ja) * | 2005-03-31 | 2010-07-28 | 東京エレクトロン株式会社 | エッチング方法 |
DE102005020060B4 (de) | 2005-04-29 | 2012-02-23 | Advanced Micro Devices, Inc. | Verfahren zum Strukturieren eines Dielektrikums mit kleinem ε unter Anwendung einer Hartmaske |
US7279411B2 (en) * | 2005-11-15 | 2007-10-09 | International Business Machines Corporation | Process for forming a redundant structure |
US7358182B2 (en) * | 2005-12-22 | 2008-04-15 | International Business Machines Corporation | Method of forming an interconnect structure |
KR100720490B1 (ko) * | 2005-12-28 | 2007-05-22 | 동부일렉트로닉스 주식회사 | 반도체 소자의 구리 배선 형성 방법 |
US20070232048A1 (en) * | 2006-03-31 | 2007-10-04 | Koji Miyata | Damascene interconnection having a SiCOH low k layer |
US8512849B2 (en) * | 2007-08-09 | 2013-08-20 | International Business Machines Corporation | Corrugated interfaces for multilayered interconnects |
KR100950553B1 (ko) * | 2007-08-31 | 2010-03-30 | 주식회사 하이닉스반도체 | 반도체 소자의 콘택 형성 방법 |
JP2012156356A (ja) * | 2011-01-27 | 2012-08-16 | Elpida Memory Inc | 半導体装置の製造方法 |
GB201217712D0 (en) | 2012-10-03 | 2012-11-14 | Spts Technologies Ltd | methods of plasma etching |
CN103646911A (zh) * | 2013-11-08 | 2014-03-19 | 上海华力微电子有限公司 | 减小金属层刻蚀损伤的方法 |
US9299577B2 (en) * | 2014-01-24 | 2016-03-29 | Applied Materials, Inc. | Methods for etching a dielectric barrier layer in a dual damascene structure |
US9917027B2 (en) * | 2015-12-30 | 2018-03-13 | Globalfoundries Singapore Pte. Ltd. | Integrated circuits with aluminum via structures and methods for fabricating the same |
CN108511448A (zh) * | 2018-03-23 | 2018-09-07 | 上海华虹宏力半导体制造有限公司 | 半导体结构的形成方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2962408D1 (en) | 1978-01-30 | 1982-05-19 | Cin Ind Investments Limited | Synthetic resin/glass laminates and process for producing these laminates |
DE3230714A1 (de) | 1982-08-18 | 1984-02-23 | Siemens AG, 1000 Berlin und 8000 München | Halbleiter mit einem abschaltbaren thyristor und einem abschaltstrompfad |
US5739579A (en) * | 1992-06-29 | 1998-04-14 | Intel Corporation | Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections |
JP3677755B2 (ja) * | 1995-09-26 | 2005-08-03 | 富士通株式会社 | 半導体装置及びその製造方法 |
US5998244A (en) | 1996-08-22 | 1999-12-07 | Micron Technology, Inc. | Memory cell incorporating a chalcogenide element and method of making same |
TW468273B (en) * | 1997-04-10 | 2001-12-11 | Hitachi Ltd | Semiconductor integrated circuit device and method for manufacturing the same |
JP3300643B2 (ja) * | 1997-09-09 | 2002-07-08 | 株式会社東芝 | 半導体装置の製造方法 |
US6054379A (en) * | 1998-02-11 | 2000-04-25 | Applied Materials, Inc. | Method of depositing a low k dielectric with organo silane |
JP3469771B2 (ja) * | 1998-03-24 | 2003-11-25 | 富士通株式会社 | 半導体装置およびその製造方法 |
US6387287B1 (en) * | 1998-03-27 | 2002-05-14 | Applied Materials, Inc. | Process for etching oxide using a hexafluorobutadiene and manifesting a wide process window |
US6211092B1 (en) * | 1998-07-09 | 2001-04-03 | Applied Materials, Inc. | Counterbore dielectric plasma etch process particularly useful for dual damascene |
US6380096B2 (en) * | 1998-07-09 | 2002-04-30 | Applied Materials, Inc. | In-situ integrated oxide etch process particularly useful for copper dual damascene |
JP3815889B2 (ja) * | 1998-08-10 | 2006-08-30 | シャープ株式会社 | 多層配線の形成方法 |
JP3657788B2 (ja) * | 1998-10-14 | 2005-06-08 | 富士通株式会社 | 半導体装置及びその製造方法 |
US6168726B1 (en) * | 1998-11-25 | 2001-01-02 | Applied Materials, Inc. | Etching an oxidized organo-silane film |
US6030901A (en) * | 1999-06-24 | 2000-02-29 | Advanced Micro Devices, Inc. | Photoresist stripping without degrading low dielectric constant materials |
JP4173307B2 (ja) * | 1999-06-24 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体集積回路の製造方法 |
US6251770B1 (en) * | 1999-06-30 | 2001-06-26 | Lam Research Corp. | Dual-damascene dielectric structures and methods for making the same |
-
2000
- 2000-06-30 US US09/608,119 patent/US6410437B1/en not_active Expired - Lifetime
-
2001
- 2001-06-08 EP EP01944382A patent/EP1295330A2/en not_active Withdrawn
- 2001-06-08 KR KR1020027017338A patent/KR100787847B1/ko not_active IP Right Cessation
- 2001-06-08 CN CNB2005100543314A patent/CN100481432C/zh not_active Expired - Fee Related
- 2001-06-08 CN CNB018148905A patent/CN1199258C/zh not_active Expired - Lifetime
- 2001-06-08 AU AU2001266798A patent/AU2001266798A1/en not_active Abandoned
- 2001-06-08 SG SG200500953-5A patent/SG145555A1/en unknown
- 2001-06-08 JP JP2002507435A patent/JP5178983B2/ja not_active Expired - Fee Related
- 2001-06-08 WO PCT/US2001/018626 patent/WO2002003454A2/en active Application Filing
- 2001-06-13 TW TW090114338A patent/TW516176B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN100481432C (zh) | 2009-04-22 |
US6410437B1 (en) | 2002-06-25 |
CN1645605A (zh) | 2005-07-27 |
KR20030020301A (ko) | 2003-03-08 |
TW516176B (en) | 2003-01-01 |
WO2002003454A2 (en) | 2002-01-10 |
KR100787847B1 (ko) | 2007-12-27 |
JP2004503088A (ja) | 2004-01-29 |
CN1449578A (zh) | 2003-10-15 |
CN1199258C (zh) | 2005-04-27 |
SG145555A1 (en) | 2008-09-29 |
WO2002003454B1 (en) | 2002-06-27 |
WO2002003454A3 (en) | 2002-05-23 |
EP1295330A2 (en) | 2003-03-26 |
JP5178983B2 (ja) | 2013-04-10 |
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