AU1099700A - Deposited thin build-up layer dimensions as a method of relieving stress in highdensity interconnect printed wiring board substrates - Google Patents

Deposited thin build-up layer dimensions as a method of relieving stress in highdensity interconnect printed wiring board substrates

Info

Publication number
AU1099700A
AU1099700A AU10997/00A AU1099700A AU1099700A AU 1099700 A AU1099700 A AU 1099700A AU 10997/00 A AU10997/00 A AU 10997/00A AU 1099700 A AU1099700 A AU 1099700A AU 1099700 A AU1099700 A AU 1099700A
Authority
AU
Australia
Prior art keywords
highdensity
wiring board
printed wiring
deposited thin
relieving stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU10997/00A
Other languages
English (en)
Inventor
James L. Lykins
Jan I. Strandberg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kulicke and Soffa Holdings Inc
Original Assignee
Kulicke and Soffa Holdings Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kulicke and Soffa Holdings Inc filed Critical Kulicke and Soffa Holdings Inc
Publication of AU1099700A publication Critical patent/AU1099700A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0209—Inorganic, non-metallic particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09236—Parallel layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/093—Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0756—Uses of liquids, e.g. rinsing, coating, dissolving
    • H05K2203/0759—Forming a polymer layer by liquid coating, e.g. a non-metallic protective coating or an organic bonding layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
AU10997/00A 1998-10-13 1999-10-12 Deposited thin build-up layer dimensions as a method of relieving stress in highdensity interconnect printed wiring board substrates Abandoned AU1099700A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09172178 1998-10-13
US09/172,178 US6440641B1 (en) 1998-07-31 1998-10-13 Deposited thin film build-up layer dimensions as a method of relieving stress in high density interconnect printed wiring board substrates
PCT/US1999/022946 WO2000022899A1 (en) 1998-10-13 1999-10-12 Deposited thin build-up layer dimensions as a method of relieving stress in high density interconnect printed wiring board substrates

Publications (1)

Publication Number Publication Date
AU1099700A true AU1099700A (en) 2000-05-01

Family

ID=22626669

Family Applications (1)

Application Number Title Priority Date Filing Date
AU10997/00A Abandoned AU1099700A (en) 1998-10-13 1999-10-12 Deposited thin build-up layer dimensions as a method of relieving stress in highdensity interconnect printed wiring board substrates

Country Status (7)

Country Link
US (1) US6440641B1 (ko)
EP (1) EP1133904A1 (ko)
JP (1) JP2002527915A (ko)
KR (1) KR20010088866A (ko)
AU (1) AU1099700A (ko)
TW (1) TW449887B (ko)
WO (1) WO2000022899A1 (ko)

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US6465084B1 (en) * 2001-04-12 2002-10-15 International Business Machines Corporation Method and structure for producing Z-axis interconnection assembly of printed wiring board elements
JP4488684B2 (ja) * 2002-08-09 2010-06-23 イビデン株式会社 多層プリント配線板
US8569142B2 (en) 2003-11-28 2013-10-29 Blackberry Limited Multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same
US7224040B2 (en) 2003-11-28 2007-05-29 Gennum Corporation Multi-level thin film capacitor on a ceramic substrate
KR20120104641A (ko) * 2004-02-04 2012-09-21 이비덴 가부시키가이샤 다층프린트배선판
WO2007130471A2 (en) * 2006-05-01 2007-11-15 The Charles Stark Draper Laboratory, Inc. Systems and methods for high density multi-component modules
JP2008091552A (ja) * 2006-09-29 2008-04-17 Fujitsu Ltd プリント配線板およびプリント基板ユニット並びに電子機器
US8273603B2 (en) 2008-04-04 2012-09-25 The Charles Stark Draper Laboratory, Inc. Interposers, electronic modules, and methods for forming the same
US8017451B2 (en) 2008-04-04 2011-09-13 The Charles Stark Draper Laboratory, Inc. Electronic modules and methods for forming the same
TWI347809B (en) * 2008-04-10 2011-08-21 Ase Electronics Inc Method of forming measuring target for measuring dimensions of substrate in the substrate process
TWI419275B (zh) * 2009-03-25 2013-12-11 Unimicron Technology Corp 封裝基板結構及其製法
US9613843B2 (en) * 2014-10-13 2017-04-04 General Electric Company Power overlay structure having wirebonds and method of manufacturing same
CN111508893B (zh) * 2019-01-31 2023-12-15 奥特斯(中国)有限公司 部件承载件及制造部件承载件的方法

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US4695868A (en) 1985-12-13 1987-09-22 Rca Corporation Patterned metallization for integrated circuits
JPH0716094B2 (ja) 1986-03-31 1995-02-22 日立化成工業株式会社 配線板の製造法
US4761303A (en) * 1986-11-10 1988-08-02 Macdermid, Incorporated Process for preparing multilayer printed circuit boards
US4847146A (en) 1988-03-21 1989-07-11 Hughes Aircraft Company Process for fabricating compliant layer board with selectively isolated solder pads
JP2548602B2 (ja) 1988-04-12 1996-10-30 株式会社日立製作所 半導体実装モジュール
US4871316A (en) 1988-10-17 1989-10-03 Microelectronics And Computer Technology Corporation Printed wire connector
US5108825A (en) 1989-12-21 1992-04-28 General Electric Company Epoxy/polyimide copolymer blend dielectric and layered circuits incorporating it
US5126192A (en) 1990-01-26 1992-06-30 International Business Machines Corporation Flame retardant, low dielectric constant microsphere filled laminate
US5514624A (en) 1990-08-07 1996-05-07 Seiko Epson Corporation Method of manufacturing a microelectronic interlayer dielectric structure
JP3128811B2 (ja) 1990-08-07 2001-01-29 セイコーエプソン株式会社 半導体装置の製造方法
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Also Published As

Publication number Publication date
EP1133904A1 (en) 2001-09-19
TW449887B (en) 2001-08-11
JP2002527915A (ja) 2002-08-27
US6440641B1 (en) 2002-08-27
KR20010088866A (ko) 2001-09-28
WO2000022899A1 (en) 2000-04-20

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase