ATE86772T1 - Schnittstelle und verfahren fuer buszugriff in einem rechner. - Google Patents

Schnittstelle und verfahren fuer buszugriff in einem rechner.

Info

Publication number
ATE86772T1
ATE86772T1 AT86308026T AT86308026T ATE86772T1 AT E86772 T1 ATE86772 T1 AT E86772T1 AT 86308026 T AT86308026 T AT 86308026T AT 86308026 T AT86308026 T AT 86308026T AT E86772 T1 ATE86772 T1 AT E86772T1
Authority
AT
Austria
Prior art keywords
signal
bus
access
generated
priority
Prior art date
Application number
AT86308026T
Other languages
English (en)
Inventor
Peter G Marshall
Robert Feldstein
Original Assignee
Data General Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Data General Corp filed Critical Data General Corp
Application granted granted Critical
Publication of ATE86772T1 publication Critical patent/ATE86772T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/378—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a parallel poll method
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
  • Small-Scale Networks (AREA)
  • Information Transfer Systems (AREA)
  • Medicines That Contain Protein Lipid Enzymes And Other Medicines (AREA)
AT86308026T 1985-11-15 1986-10-16 Schnittstelle und verfahren fuer buszugriff in einem rechner. ATE86772T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/798,595 US4908749A (en) 1985-11-15 1985-11-15 System for controlling access to computer bus having address phase and data phase by prolonging the generation of request signal
EP86308026A EP0222520B1 (de) 1985-11-15 1986-10-16 Schnittstelle und Verfahren für Buszugriff in einem Rechner

Publications (1)

Publication Number Publication Date
ATE86772T1 true ATE86772T1 (de) 1993-03-15

Family

ID=25173804

Family Applications (1)

Application Number Title Priority Date Filing Date
AT86308026T ATE86772T1 (de) 1985-11-15 1986-10-16 Schnittstelle und verfahren fuer buszugriff in einem rechner.

Country Status (7)

Country Link
US (1) US4908749A (de)
EP (1) EP0222520B1 (de)
JP (1) JPS62163160A (de)
AT (1) ATE86772T1 (de)
AU (1) AU590626B2 (de)
CA (1) CA1273117A (de)
DE (1) DE3687947T2 (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4796176A (en) 1985-11-15 1989-01-03 Data General Corporation Interrupt handling in a multiprocessor computing system
EP0606102A1 (de) * 1986-09-19 1994-07-13 International Business Machines Corporation Ein-Ausgabeschnittstellensteuerung zum Verbinden eines synchronen Busses mit einem asynchronen Bus und Verfahren zur Operationsausführung auf den Bussen
US5034883A (en) * 1987-05-01 1991-07-23 Digital Equipment Corporation Lockhead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers
US4947368A (en) * 1987-05-01 1990-08-07 Digital Equipment Corporation Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers
US5111424A (en) * 1987-05-01 1992-05-05 Digital Equipment Corporation Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfer
US4845663A (en) * 1987-09-03 1989-07-04 Minnesota Mining And Manufacturing Company Image processor with free flow pipeline bus
JPH0215378A (ja) * 1988-03-23 1990-01-19 Du Pont Pixel Syst Ltd グラフィックス処理システムおよびその方法
GB8808353D0 (en) * 1988-04-09 1988-05-11 Int Computers Ltd Data processing system
CA1320767C (en) * 1988-05-11 1993-07-27 Robert C. Frame Atomic sequence for phase transitions
US5230067A (en) * 1988-05-11 1993-07-20 Digital Equipment Corporation Bus control circuit for latching and maintaining data independently of timing event on the bus until new data is driven onto
US5261057A (en) * 1988-06-30 1993-11-09 Wang Laboratories, Inc. I/O bus to system interface
US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
GB8820183D0 (en) * 1988-08-25 1988-09-28 Int Computers Ltd Data processing apparatus
US4979099A (en) * 1988-10-25 1990-12-18 Apollo Computer Inc. Quasi-fair arbitration scheme with default owner speedup
US5167022A (en) * 1988-10-25 1992-11-24 Hewlett-Packard Company Multiprocessor bus locking system with a winning processor broadcasting an ownership signal causing all processors to halt their requests
US5239638A (en) * 1988-12-30 1993-08-24 Intel Corporation Two strobed memory access
US5088024A (en) * 1989-01-31 1992-02-11 Wisconsin Alumni Research Foundation Round-robin protocol method for arbitrating access to a shared bus arbitration providing preference to lower priority units after bus access by a higher priority unit
US5127089A (en) * 1989-07-03 1992-06-30 Motorola, Inc. Synchronous bus lock mechanism permitting bus arbiter to change bus master during a plurality of successive locked operand transfer sequences after completion of current sequence
EP0514428B1 (de) * 1990-01-19 1999-07-07 Codex Corporation Entscheidung zwischen mehreren benutzern bei einem gemeinsamen betriebsmittel
US5263163A (en) * 1990-01-19 1993-11-16 Codex Corporation Arbitration among multiple users of a shared resource
EP0453268B1 (de) * 1990-04-20 1997-10-22 Hitachi, Ltd. Mikroprozessor zur Buszykluseinfügung zwecks Informationslieferung für eine Emulation
EP0468553A3 (en) * 1990-06-08 1992-10-21 N.V. Philips' Gloeilampenfabrieken Instrumentation system and instrumentation devices adapted for use in such a system
DE69118781T2 (de) * 1990-08-31 1996-10-31 Advanced Micro Devices Inc Übertragungssteuerungssystem für einen Rechner und Peripheriegeräte
JPH04141757A (ja) * 1990-10-03 1992-05-15 Fujitsu Ltd バス制御方式
US5301330A (en) * 1990-10-12 1994-04-05 Advanced Micro Devices, Inc. Contention handling apparatus for generating user busy signal by logically summing wait output of next higher priority user and access requests of higher priority users
US5301282A (en) * 1991-10-15 1994-04-05 International Business Machines Corp. Controlling bus allocation using arbitration hold
US5263139A (en) * 1992-05-19 1993-11-16 Sun Microsystems, Inc. Multiple bus architecture for flexible communication among processor modules and memory subsystems and specialized subsystems
US5430848A (en) * 1992-08-14 1995-07-04 Loral Fairchild Corporation Distributed arbitration with programmable priorities
US5379403A (en) * 1992-11-27 1995-01-03 Ncr Corporation Method and interface adapter for interfacing an ISA board to an MCA system by the issuance of an ILLINI-CDCHRDY signal from the interface adapter
CA2109043A1 (en) * 1993-01-29 1994-07-30 Charles R. Moore System and method for transferring data between multiple buses
US5832253A (en) * 1993-12-06 1998-11-03 Cpu Technology, Inc. Multiprocessors system for selectively wire-oring a combination of signal lines and thereafter using one line to control the running or stalling of a selected processor
US6256694B1 (en) * 1994-06-30 2001-07-03 Compaq Computer Corporation Distributed early arbitration
US5502835A (en) * 1994-08-31 1996-03-26 Motorola, Inc. Method for synchronously accessing memory
US7043656B2 (en) * 2003-01-28 2006-05-09 Hewlett-Packard Development Company, L.P. Methods and apparatus for extending a phase on an interconnect
US7765350B2 (en) * 2005-09-14 2010-07-27 Koninklijke Philips Electronics N.V. Method and system for bus arbitration
US10606596B2 (en) * 2013-07-15 2020-03-31 Texas Instruments Incorporated Cache preload operations using streaming engine

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3551894A (en) * 1967-12-28 1970-12-29 Ibm Serial cross-bar bussing system
US3603935A (en) * 1969-05-12 1971-09-07 Xerox Corp Memory port priority access system with inhibition of low priority lock-out
US4090238A (en) * 1976-10-04 1978-05-16 Rca Corporation Priority vectored interrupt using direct memory access
US4281380A (en) * 1978-12-27 1981-07-28 Harris Corporation Bus collision avoidance system for distributed network data processing communications system
US4371925A (en) * 1980-02-11 1983-02-01 Data General Corporation Data processing system having unique bus control operation
JPS6019819B2 (ja) * 1980-04-02 1985-05-18 富士電機株式会社 バス使用権制御方式
NL8002346A (nl) * 1980-04-23 1981-11-16 Philips Nv Multi databron- en dataontvangersysteem met communicatiebus.
US4390944A (en) * 1980-05-13 1983-06-28 Bti Computer Systems System for controlling access to a common bus in a computer system
JPS5723132A (en) * 1980-07-18 1982-02-06 Nippon Telegr & Teleph Corp <Ntt> Acquisition system for priority right of interruption
US4375639A (en) * 1981-01-12 1983-03-01 Harris Corporation Synchronous bus arbiter
US4442502A (en) * 1981-03-30 1984-04-10 Datapoint Corporation Digital information switching system
FR2503898B1 (fr) * 1981-04-08 1986-02-28 Thomson Csf Procede et dispositif d'allocation d'une ressource dans un systeme comportant des unites de traitement de donnees autonomes
US4573118A (en) * 1983-03-31 1986-02-25 Fairchild Camera & Instrument Corporation Microprocessor with branch control
US4620278A (en) * 1983-08-29 1986-10-28 Sperry Corporation Distributed bus arbitration according each bus user the ability to inhibit all new requests to arbitrate the bus, or to cancel its own pending request, and according the highest priority user the ability to stop the bus
US4627018A (en) * 1983-09-08 1986-12-02 Sperry Corporation Priority requestor accelerator
JPS6097459A (ja) * 1983-10-18 1985-05-31 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション デ−タ処理システム同期方法
US4594590A (en) * 1983-11-04 1986-06-10 Control Data Corporation Demand driven access mechanism
US4570220A (en) * 1983-11-25 1986-02-11 Intel Corporation High speed parallel bus and data transfer method

Also Published As

Publication number Publication date
EP0222520A3 (en) 1989-02-08
CA1273117A (en) 1990-08-21
DE3687947T2 (de) 1993-10-21
AU6394586A (en) 1987-05-21
DE3687947D1 (de) 1993-04-15
US4908749A (en) 1990-03-13
AU590626B2 (en) 1989-11-09
JPS62163160A (ja) 1987-07-18
EP0222520A2 (de) 1987-05-20
EP0222520B1 (de) 1993-03-10

Similar Documents

Publication Publication Date Title
ATE86772T1 (de) Schnittstelle und verfahren fuer buszugriff in einem rechner.
US4449183A (en) Arbitration scheme for a multiported shared functional device for use in multiprocessing systems
ATE256311T1 (de) Mehrprozessor-anordnung mit geteiltem speicherzugriff unter vorrang-kontrolle
DE69307717D1 (de) Priorisierung von mikroprozessoren in multiprozessorrechnersystemen
GB2143060A (en) Data processing system
DE69322248D1 (de) Reservierung, die den normalen vorrang von mikroprozessoren in multiprozessorrechnersystemen annulliert
CA2124031A1 (en) System Direct Memory Access (DMA) Support Logic for PCI Based Computer System
DE69701078D1 (de) Mikroprozessorarchitektur mit der Möglichkeit zur Unterstützung mehrerer verschiedener Prozessoren
ATE73242T1 (de) Datenverarbeitungssystem und -verfahren.
EP0111840A3 (de) Zugriffsteuerungsverfahren für Multiprozessorsysteme
ATE207218T1 (de) Bus-master-arbitrierungsschaltung mit wiederholungsmechanismus
SE8405456L (sv) Mycket snabbt minnes- och minnesforvaltningssystem
GB1520485A (en) Data processing system
KR950012175A (ko) 복수의 프로세서로부터의 액세스 요청을 조정하는 장치
EP0242879A2 (de) Datenprozessor mit Wartesteuerung, die Hochgeschwindigkeitszugriff gestattet
JPH0354660A (ja) マルチプロセッサシステムにおける共有メモリ管理方式
Alberi A method of interprocessor communication for a multiprocessor environment
SE9203016D0 (sv) Signalbehandlingssystem med delat dataminne
JPS6120172A (ja) マルチマイクロプロセツサシステム
JPS62127962A (ja) マイクロコンピユ−タ
JPH0575140B2 (de)
JPS57130137A (en) Data processor
JPS6082349U (ja) 共有メモリのアクセス制御装置
JPS5553720A (en) Data transfer control system
JPS598184A (ja) メモリ

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties