ATE81738T1 - Cmos-verriegelungsschaltungen. - Google Patents

Cmos-verriegelungsschaltungen.

Info

Publication number
ATE81738T1
ATE81738T1 AT88307656T AT88307656T ATE81738T1 AT E81738 T1 ATE81738 T1 AT E81738T1 AT 88307656 T AT88307656 T AT 88307656T AT 88307656 T AT88307656 T AT 88307656T AT E81738 T1 ATE81738 T1 AT E81738T1
Authority
AT
Austria
Prior art keywords
channel
latch circuit
transistor
true
complementary
Prior art date
Application number
AT88307656T
Other languages
English (en)
Inventor
Donald Monroe Walters Jr
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE81738T1 publication Critical patent/ATE81738T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors

Landscapes

  • Logic Circuits (AREA)
  • Supporting Of Heads In Record-Carrier Devices (AREA)
  • Electronic Switches (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
AT88307656T 1987-11-02 1988-08-18 Cmos-verriegelungsschaltungen. ATE81738T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/115,279 US4800300A (en) 1987-11-02 1987-11-02 High-performance, CMOS latch for improved reliability
EP88307656A EP0315301B1 (de) 1987-11-02 1988-08-18 CMOS-Verriegelungsschaltungen

Publications (1)

Publication Number Publication Date
ATE81738T1 true ATE81738T1 (de) 1992-11-15

Family

ID=22360340

Family Applications (1)

Application Number Title Priority Date Filing Date
AT88307656T ATE81738T1 (de) 1987-11-02 1988-08-18 Cmos-verriegelungsschaltungen.

Country Status (7)

Country Link
US (1) US4800300A (de)
EP (1) EP0315301B1 (de)
JP (1) JP2733578B2 (de)
AT (1) ATE81738T1 (de)
DE (1) DE3875450T2 (de)
ES (1) ES2035303T3 (de)
GR (1) GR3006154T3 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05243956A (ja) * 1991-06-28 1993-09-21 Texas Instr Inc <Ti> Ｅｃｌ型信号をｃｍｏｓ信号に変換する装置および方法
US5361229A (en) * 1993-04-08 1994-11-01 Xilinx, Inc. Precharging bitlines for robust reading of latch data
US5461331A (en) * 1994-07-28 1995-10-24 International Business Machines Corporation Dynamic to static logic translator or pulse catcher
JP3229164B2 (ja) * 1994-07-28 2001-11-12 インターナショナル・ビジネス・マシーンズ・コーポレーション ラッチ回路
US5576651A (en) * 1995-05-22 1996-11-19 International Business Machines Corporation Static/dynamic flip-flop
US5936449A (en) * 1997-09-08 1999-08-10 Winbond Electronics Corporation Dynamic CMOS register with a self-tracking clock
DE19743347C2 (de) * 1997-09-30 1999-08-12 Siemens Ag RS-Flip-Flop mit Enable-Eingängen
JP3533357B2 (ja) * 2000-02-29 2004-05-31 株式会社東芝 論理演算機能を備えた半導体集積回路
US7138850B1 (en) 2004-02-04 2006-11-21 Marvell Semiconductor Israel Ltd High-gain synchronizer circuitry and methods
US8786307B2 (en) * 2011-06-28 2014-07-22 Texas Instruments Incorporated Bias temperature instability-resistant circuits
US9178499B2 (en) * 2014-02-27 2015-11-03 Texas Instruments Incorporated Low-power offset-stored latch
TWI820090B (zh) * 2018-09-14 2023-11-01 日商鎧俠股份有限公司 半導體記憶裝置
US10867641B2 (en) 2018-09-14 2020-12-15 Toshiba Memory Corporation Data latch circuit and semiconductor memory device
CN113644907B (zh) * 2021-08-31 2023-07-07 复旦大学 由共栅互补场效应晶体管构建的d锁存器

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3739193A (en) * 1971-01-11 1973-06-12 Rca Corp Logic circuit
JPS5338373A (en) * 1976-09-20 1978-04-08 Seiko Epson Corp Ic for watch
US4506167A (en) * 1982-05-26 1985-03-19 Motorola, Inc. High speed logic flip-flop latching arrangements including input and feedback pairs of transmission gates
US4629909A (en) * 1984-10-19 1986-12-16 American Microsystems, Inc. Flip-flop for storing data on both leading and trailing edges of clock signal
US4617480A (en) * 1984-10-22 1986-10-14 Motorola, Inc. High speed data synchronizer which minimizes circuitry

Also Published As

Publication number Publication date
ES2035303T3 (es) 1993-04-16
US4800300A (en) 1989-01-24
JP2733578B2 (ja) 1998-03-30
EP0315301A2 (de) 1989-05-10
EP0315301B1 (de) 1992-10-21
DE3875450T2 (de) 1993-04-22
EP0315301A3 (en) 1990-03-14
DE3875450D1 (de) 1992-11-26
GR3006154T3 (de) 1993-06-21
JPH01130618A (ja) 1989-05-23

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee