ATE552557T1 - Zweikanalspeicherarchitektur mit verringerten schnittstellen-pin-anforderungen unter verwendung eines doppeldatenratenschemas für die adressen- /steuersignale - Google Patents

Zweikanalspeicherarchitektur mit verringerten schnittstellen-pin-anforderungen unter verwendung eines doppeldatenratenschemas für die adressen- /steuersignale

Info

Publication number
ATE552557T1
ATE552557T1 AT09717759T AT09717759T ATE552557T1 AT E552557 T1 ATE552557 T1 AT E552557T1 AT 09717759 T AT09717759 T AT 09717759T AT 09717759 T AT09717759 T AT 09717759T AT E552557 T1 ATE552557 T1 AT E552557T1
Authority
AT
Austria
Prior art keywords
memory
clock signal
dual
interface pin
memory architecture
Prior art date
Application number
AT09717759T
Other languages
English (en)
Inventor
Jian Mao
Raghu Sankuratri
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Application granted granted Critical
Publication of ATE552557T1 publication Critical patent/ATE552557T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
AT09717759T 2008-02-29 2009-02-04 Zweikanalspeicherarchitektur mit verringerten schnittstellen-pin-anforderungen unter verwendung eines doppeldatenratenschemas für die adressen- /steuersignale ATE552557T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/039,908 US7804735B2 (en) 2008-02-29 2008-02-29 Dual channel memory architecture having a reduced interface pin requirements using a double data rate scheme for the address/control signals
PCT/US2009/033018 WO2009111125A1 (en) 2008-02-29 2009-02-04 Dual channel memory architecture having reduced interface pin requirements using a double data rate scheme for the address/control signals

Publications (1)

Publication Number Publication Date
ATE552557T1 true ATE552557T1 (de) 2012-04-15

Family

ID=40674058

Family Applications (1)

Application Number Title Priority Date Filing Date
AT09717759T ATE552557T1 (de) 2008-02-29 2009-02-04 Zweikanalspeicherarchitektur mit verringerten schnittstellen-pin-anforderungen unter verwendung eines doppeldatenratenschemas für die adressen- /steuersignale

Country Status (7)

Country Link
US (2) US7804735B2 (de)
EP (1) EP2263153B1 (de)
JP (1) JP5474837B2 (de)
KR (1) KR101108342B1 (de)
CN (2) CN103279438B (de)
AT (1) ATE552557T1 (de)
WO (1) WO2009111125A1 (de)

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US20130111122A1 (en) * 2011-10-31 2013-05-02 Futurewei Technologies, Inc. Method and apparatus for network table lookups
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US10355001B2 (en) * 2012-02-15 2019-07-16 Micron Technology, Inc. Memories and methods to provide configuration information to controllers
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CN105760310B (zh) * 2016-02-05 2018-12-14 华为技术有限公司 地址分配方法及ddr控制器
US10380060B2 (en) * 2016-06-17 2019-08-13 Etron Technology, Inc. Low-pincount high-bandwidth memory and memory bus
US9773543B1 (en) * 2016-08-31 2017-09-26 Xilinx, Inc. Effective clamshell mirroring for memory interfaces
US9940984B1 (en) * 2016-09-28 2018-04-10 Intel Corporation Shared command address (C/A) bus for multiple memory channels
US10846018B2 (en) 2017-04-05 2020-11-24 Mediatek Inc. Memory device, memory controller and associated memory system operated according to selected clock signals
KR20180113371A (ko) * 2017-04-06 2018-10-16 에스케이하이닉스 주식회사 데이터 저장 장치
US10541020B2 (en) * 2018-02-27 2020-01-21 Seagate Technology Llc Controller architecture for reducing on-die capacitance
CN112449693B (zh) * 2018-03-07 2024-05-24 美光科技公司 在存储系统的两遍编程之前执行读取操作
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Also Published As

Publication number Publication date
JP2011513845A (ja) 2011-04-28
EP2263153A1 (de) 2010-12-22
CN103279438B (zh) 2016-01-20
CN101960436A (zh) 2011-01-26
CN103279438A (zh) 2013-09-04
JP5474837B2 (ja) 2014-04-16
CN101960436B (zh) 2013-07-17
US20090219779A1 (en) 2009-09-03
US20100318730A1 (en) 2010-12-16
WO2009111125A1 (en) 2009-09-11
US8325525B2 (en) 2012-12-04
US7804735B2 (en) 2010-09-28
EP2263153B1 (de) 2012-04-04
KR20100117687A (ko) 2010-11-03
KR101108342B1 (ko) 2012-01-25

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