ATE511676T1 - Scheduling auf der basis eines turnaround- ereignisses - Google Patents

Scheduling auf der basis eines turnaround- ereignisses

Info

Publication number
ATE511676T1
ATE511676T1 AT08851995T AT08851995T ATE511676T1 AT E511676 T1 ATE511676 T1 AT E511676T1 AT 08851995 T AT08851995 T AT 08851995T AT 08851995 T AT08851995 T AT 08851995T AT E511676 T1 ATE511676 T1 AT E511676T1
Authority
AT
Austria
Prior art keywords
memory
signal
turnaround
scheduled
driven
Prior art date
Application number
AT08851995T
Other languages
English (en)
Inventor
Richard Perego
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus Inc filed Critical Rambus Inc
Application granted granted Critical
Publication of ATE511676T1 publication Critical patent/ATE511676T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)
AT08851995T 2007-11-19 2008-11-19 Scheduling auf der basis eines turnaround- ereignisses ATE511676T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US98887807P 2007-11-19 2007-11-19
PCT/US2008/084003 WO2009067496A1 (en) 2007-11-19 2008-11-19 Scheduling based on turnaround event

Publications (1)

Publication Number Publication Date
ATE511676T1 true ATE511676T1 (de) 2011-06-15

Family

ID=40385138

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08851995T ATE511676T1 (de) 2007-11-19 2008-11-19 Scheduling auf der basis eines turnaround- ereignisses

Country Status (7)

Country Link
US (1) US20100293343A1 (de)
EP (1) EP2223224B1 (de)
JP (1) JP2011503753A (de)
KR (1) KR20100098622A (de)
CN (1) CN101868788B (de)
AT (1) ATE511676T1 (de)
WO (1) WO2009067496A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9619316B2 (en) 2012-03-26 2017-04-11 Intel Corporation Timing optimization for memory devices employing error detection coded transactions
US9754648B2 (en) 2012-10-26 2017-09-05 Micron Technology, Inc. Apparatuses and methods for memory operations having variable latencies
US9740485B2 (en) * 2012-10-26 2017-08-22 Micron Technology, Inc. Apparatuses and methods for memory operations having variable latencies
US9734097B2 (en) 2013-03-15 2017-08-15 Micron Technology, Inc. Apparatuses and methods for variable latency memory operations
US9727493B2 (en) 2013-08-14 2017-08-08 Micron Technology, Inc. Apparatuses and methods for providing data to a configurable storage area
CN104866238B (zh) 2015-05-25 2018-12-14 华为技术有限公司 访问请求调度方法及装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7187572B2 (en) * 2002-06-28 2007-03-06 Rambus Inc. Early read after write operation memory device, system and method
US5819027A (en) * 1996-02-28 1998-10-06 Intel Corporation Bus patcher
US6272600B1 (en) * 1996-11-15 2001-08-07 Hyundai Electronics America Memory request reordering in a data processing system
US5903916A (en) * 1996-12-16 1999-05-11 Intel Corporation Computer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operation
US6889304B2 (en) * 2001-02-28 2005-05-03 Rambus Inc. Memory device supporting a dynamically configurable core organization
US7610447B2 (en) * 2001-02-28 2009-10-27 Rambus Inc. Upgradable memory system with reconfigurable interconnect
US6785793B2 (en) * 2001-09-27 2004-08-31 Intel Corporation Method and apparatus for memory access scheduling to reduce memory access latency
US7149841B2 (en) * 2003-03-31 2006-12-12 Micron Technology, Inc. Memory devices with buffered command address bus
US8595459B2 (en) * 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
US7464225B2 (en) * 2005-09-26 2008-12-09 Rambus Inc. Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
WO2007095080A2 (en) * 2006-02-09 2007-08-23 Metaram, Inc. Memory circuit system and method
US7613883B2 (en) * 2006-03-10 2009-11-03 Rambus Inc. Memory device with mode-selectable prefetch and clock-to-core timing
JP2008033657A (ja) * 2006-07-28 2008-02-14 Toshiba Corp メモリ制御装置および情報処理装置並びにメモリ制御方法

Also Published As

Publication number Publication date
JP2011503753A (ja) 2011-01-27
CN101868788B (zh) 2012-12-26
EP2223224B1 (de) 2011-06-01
WO2009067496A1 (en) 2009-05-28
WO2009067496A4 (en) 2009-07-16
US20100293343A1 (en) 2010-11-18
KR20100098622A (ko) 2010-09-08
CN101868788A (zh) 2010-10-20
EP2223224A1 (de) 2010-09-01

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