ATE521067T1 - Sram mit elastischer spannungsversorgung für lese-und schreiboperationen - Google Patents
Sram mit elastischer spannungsversorgung für lese-und schreiboperationenInfo
- Publication number
- ATE521067T1 ATE521067T1 AT08728583T AT08728583T ATE521067T1 AT E521067 T1 ATE521067 T1 AT E521067T1 AT 08728583 T AT08728583 T AT 08728583T AT 08728583 T AT08728583 T AT 08728583T AT E521067 T1 ATE521067 T1 AT E521067T1
- Authority
- AT
- Austria
- Prior art keywords
- sram cell
- sram
- write operations
- voltage
- read
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
- Electrophonic Musical Instruments (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Inks, Pencil-Leads, Or Crayons (AREA)
- Electronic Switches (AREA)
- Keying Circuit Devices (AREA)
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US88800607P | 2007-02-02 | 2007-02-02 | |
US11/932,643 US20080266995A1 (en) | 2007-02-02 | 2007-10-31 | Method of selectively powering memory device |
US11/932,555 US7952910B2 (en) | 2007-02-02 | 2007-10-31 | Memory device with split power switch |
US11/932,967 US7672187B2 (en) | 2007-02-02 | 2007-10-31 | Elastic power for read and write margins |
US11/938,196 US7869263B2 (en) | 2007-02-02 | 2007-11-09 | Elastic power for read margin |
PCT/US2008/052496 WO2008097783A2 (en) | 2007-02-02 | 2008-01-30 | Elastic power for read and write margins |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE521067T1 true ATE521067T1 (de) | 2011-09-15 |
Family
ID=39676026
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT08728583T ATE521067T1 (de) | 2007-02-02 | 2008-01-30 | Sram mit elastischer spannungsversorgung für lese-und schreiboperationen |
Country Status (5)
Country | Link |
---|---|
US (4) | US7952910B2 (de) |
EP (2) | EP2118900B1 (de) |
AT (1) | ATE521067T1 (de) |
TW (2) | TWI389130B (de) |
WO (2) | WO2008097783A2 (de) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007193928A (ja) * | 2005-12-19 | 2007-08-02 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
US7570537B2 (en) * | 2007-07-12 | 2009-08-04 | Sun Microsystems, Inc. | Memory cells with power switch circuit for improved low voltage operation |
TWI399748B (zh) * | 2009-01-15 | 2013-06-21 | Univ Hsiuping Sci & Tech | 寫入操作時降低電源電壓之雙埠靜態隨機存取記憶體 |
KR101034616B1 (ko) * | 2009-11-30 | 2011-05-12 | 주식회사 하이닉스반도체 | 센스앰프 및 반도체 메모리장치 |
US8320203B2 (en) * | 2010-03-26 | 2012-11-27 | Intel Corporation | Method and system to lower the minimum operating voltage of register files |
JP2012038401A (ja) | 2010-08-11 | 2012-02-23 | Elpida Memory Inc | 半導体装置及び半導体装置の電源制御方法 |
US8427896B1 (en) | 2011-11-15 | 2013-04-23 | International Business Machines Corporation | Dynamic wordline assist scheme to improve performance tradeoff in SRAM |
US8729908B2 (en) | 2012-02-29 | 2014-05-20 | International Business Machines Corporation | Static noise margin monitoring circuit and method |
TWI494945B (zh) * | 2012-03-29 | 2015-08-01 | Nat Univ Chung Cheng | Single-ended read random access memory device |
US9317087B2 (en) * | 2012-04-26 | 2016-04-19 | Ravindraraj Ramaraju | Memory column drowsy control |
US9019751B2 (en) * | 2013-03-01 | 2015-04-28 | Qualcomm Incorporated | Process tolerant circuits |
US9627038B2 (en) * | 2013-03-15 | 2017-04-18 | Intel Corporation | Multiport memory cell having improved density area |
US9105355B2 (en) * | 2013-07-04 | 2015-08-11 | United Microelectronics Corporation | Memory cell array operated with multiple operation voltage |
TWI562163B (en) * | 2013-07-04 | 2016-12-11 | United Microelectronics Corp | Memory cell array |
TWI528361B (zh) * | 2013-12-10 | 2016-04-01 | 智原科技股份有限公司 | 靜態記憶胞 |
US9595307B2 (en) | 2014-05-22 | 2017-03-14 | Samsung Electronics Co., Ltd. | Volatile memory device and system-on-chip including the same |
US9570155B2 (en) | 2015-06-09 | 2017-02-14 | Globalfoundries Inc. | Circuit to improve SRAM stability |
US10049724B2 (en) | 2016-06-07 | 2018-08-14 | Intel Corporation | Aging tolerant register file |
US9922701B2 (en) * | 2016-08-08 | 2018-03-20 | Taiwan Semiconductor Manufacturing Company Limited | Pre-charging bit lines through charge-sharing |
US10236036B2 (en) * | 2017-05-09 | 2019-03-19 | Micron Technology, Inc. | Sense amplifier signal boost |
US11133039B2 (en) * | 2018-10-12 | 2021-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Power switch control in a memory device |
US11967365B2 (en) * | 2019-06-11 | 2024-04-23 | Arm Limited | Bitcell architecture with time-multiplexed ports |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4686391A (en) * | 1986-05-08 | 1987-08-11 | Genrad, Inc. | Fast-acting comparison circuit |
JPH07111824B2 (ja) * | 1986-12-15 | 1995-11-29 | 株式会社東芝 | 半導体メモリ |
KR0136074B1 (ko) * | 1992-09-11 | 1998-06-01 | 세키자와 스토무 | 개량된 소프트 에러 저항을 갖는 mos형 sram, 고전위 전원 전압 강하 검출 회로, 상보 신호 천이 검출 회로 및 개량된 내부신호 시간 마진을 갖는 반도체 장치 |
US5870331A (en) * | 1997-09-26 | 1999-02-09 | Advanced Micro Devices, Inc. | Application-specific SRAM memory cell for low voltage, high speed operation |
JP3183245B2 (ja) * | 1998-03-06 | 2001-07-09 | 日本電気株式会社 | 半導体記憶装置 |
US6117722A (en) * | 1999-02-18 | 2000-09-12 | Taiwan Semiconductor Manufacturing Company | SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof |
KR100346832B1 (ko) * | 2000-01-12 | 2002-08-03 | 삼성전자 주식회사 | 스태틱 랜덤 억세스 메모리 소자 및 그 제조 방법 |
US6801994B2 (en) * | 2000-12-20 | 2004-10-05 | Microsoft Corporation | Software management systems and methods for automotive computing devices |
JP2003045187A (ja) * | 2001-08-02 | 2003-02-14 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP4030383B2 (ja) * | 2002-08-26 | 2008-01-09 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
US6771095B1 (en) * | 2002-11-22 | 2004-08-03 | Analog Devices, Inc. | Level translating digital switch |
JP3906166B2 (ja) * | 2003-02-25 | 2007-04-18 | 株式会社東芝 | 半導体記憶装置 |
JP2004362695A (ja) * | 2003-06-05 | 2004-12-24 | Renesas Technology Corp | 半導体記憶装置 |
US7165165B2 (en) * | 2004-03-16 | 2007-01-16 | Intel Corporation | Anticipatory power control of memory |
US7129765B2 (en) * | 2004-04-30 | 2006-10-31 | Xilinx, Inc. | Differential clock tree in an integrated circuit |
US7092280B2 (en) * | 2004-11-22 | 2006-08-15 | International Business Machines Corp. | SRAM with dynamically asymmetric cell |
JP4912016B2 (ja) * | 2005-05-23 | 2012-04-04 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
US7403426B2 (en) * | 2005-05-25 | 2008-07-22 | Intel Corporation | Memory with dynamically adjustable supply |
US7060549B1 (en) | 2005-07-01 | 2006-06-13 | Advanced Micro Devices, Inc. | SRAM devices utilizing tensile-stressed strain films and methods for fabricating the same |
JP5100035B2 (ja) * | 2005-08-02 | 2012-12-19 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
JP4929668B2 (ja) * | 2005-10-12 | 2012-05-09 | 富士通セミコンダクター株式会社 | 半導体メモリ |
US7376001B2 (en) * | 2005-10-13 | 2008-05-20 | International Business Machines Corporation | Row circuit ring oscillator method for evaluating memory cell performance |
JP2007193928A (ja) * | 2005-12-19 | 2007-08-02 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
-
2007
- 2007-10-31 US US11/932,555 patent/US7952910B2/en active Active
- 2007-10-31 US US11/932,967 patent/US7672187B2/en active Active
- 2007-10-31 US US11/932,643 patent/US20080266995A1/en not_active Abandoned
- 2007-11-09 US US11/938,196 patent/US7869263B2/en active Active
-
2008
- 2008-01-30 AT AT08728583T patent/ATE521067T1/de not_active IP Right Cessation
- 2008-01-30 EP EP08728583A patent/EP2118900B1/de active Active
- 2008-01-30 EP EP08728581.3A patent/EP2118717B1/de active Active
- 2008-01-30 WO PCT/US2008/052496 patent/WO2008097783A2/en active Application Filing
- 2008-01-30 WO PCT/US2008/052493 patent/WO2008097782A1/en active Application Filing
- 2008-02-01 TW TW097103958A patent/TWI389130B/zh active
- 2008-02-01 TW TW097103973A patent/TWI394173B/zh active
Also Published As
Publication number | Publication date |
---|---|
US20080186791A1 (en) | 2008-08-07 |
EP2118717B1 (de) | 2013-08-21 |
TW200849271A (en) | 2008-12-16 |
EP2118900B1 (de) | 2011-08-17 |
WO2008097783A2 (en) | 2008-08-14 |
US7672187B2 (en) | 2010-03-02 |
US7869263B2 (en) | 2011-01-11 |
US20080266995A1 (en) | 2008-10-30 |
EP2118717A1 (de) | 2009-11-18 |
WO2008097783A3 (en) | 2008-10-23 |
US20080273412A1 (en) | 2008-11-06 |
EP2118900A2 (de) | 2009-11-18 |
TWI394173B (zh) | 2013-04-21 |
EP2118900A4 (de) | 2010-04-21 |
US20080186795A1 (en) | 2008-08-07 |
US7952910B2 (en) | 2011-05-31 |
TWI389130B (zh) | 2013-03-11 |
WO2008097782A1 (en) | 2008-08-14 |
TW200847178A (en) | 2008-12-01 |
EP2118717A4 (de) | 2010-04-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |