ATE483352T1 - Leiterplatte - Google Patents

Leiterplatte

Info

Publication number
ATE483352T1
ATE483352T1 AT06252299T AT06252299T ATE483352T1 AT E483352 T1 ATE483352 T1 AT E483352T1 AT 06252299 T AT06252299 T AT 06252299T AT 06252299 T AT06252299 T AT 06252299T AT E483352 T1 ATE483352 T1 AT E483352T1
Authority
AT
Austria
Prior art keywords
ground lines
ground
another
equal intervals
arranged parallel
Prior art date
Application number
AT06252299T
Other languages
English (en)
Inventor
Mitsuru Honjo
Yuki Saitou
Yoshifumi Morita
Yoshifumi Yamamoto
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Application granted granted Critical
Publication of ATE483352T1 publication Critical patent/ATE483352T1/de

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0253—Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0224—Patterned shielding planes, ground planes or power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09236—Parallel layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09681—Mesh conductors, e.g. as a ground plane
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24926—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)
  • Chemical And Physical Treatments For Wood And The Like (AREA)
  • Polysaccharides And Polysaccharide Derivatives (AREA)
  • Manufacturing Of Printed Wiring (AREA)
AT06252299T 2005-04-28 2006-04-28 Leiterplatte ATE483352T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005131308A JP3872084B2 (ja) 2005-04-28 2005-04-28 配線回路基板

Publications (1)

Publication Number Publication Date
ATE483352T1 true ATE483352T1 (de) 2010-10-15

Family

ID=36999884

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06252299T ATE483352T1 (de) 2005-04-28 2006-04-28 Leiterplatte

Country Status (6)

Country Link
US (1) US7473854B2 (de)
EP (1) EP1720384B1 (de)
JP (1) JP3872084B2 (de)
CN (1) CN1856214B (de)
AT (1) ATE483352T1 (de)
DE (1) DE602006017141D1 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008124317A (ja) * 2006-11-14 2008-05-29 Toshiba Matsushita Display Technology Co Ltd フレキシブルプリント基板
US8256111B2 (en) * 2006-12-22 2012-09-04 Hon Hai Precision Industry Co., Ltd. Circuit board layout method
CN101207968B (zh) * 2006-12-22 2011-11-09 鸿富锦精密工业（深圳）有限公司 电路板
EP2112871B1 (de) * 2008-04-22 2016-07-13 Hon Hai Precision Industry Co., Ltd. Leiterplatte mit verbesserter Erdungsschicht
CN101594732A (zh) * 2008-05-27 2009-12-02 鸿富锦精密工业（深圳）有限公司 电路板
JP4399019B1 (ja) * 2008-07-31 2010-01-13 株式会社東芝 電子機器、フレキシブルプリント配線板、およびフレキシブルプリント配線板の製造方法
JPWO2010082593A1 (ja) * 2009-01-16 2012-07-05 株式会社フジクラ コネクタ及びケーブルアセンブリ
KR101378027B1 (ko) 2009-07-13 2014-03-25 가부시키가이샤 무라타 세이사쿠쇼 신호선로 및 회로기판
JP2012094646A (ja) * 2010-10-26 2012-05-17 Daisho Denshi Co Ltd 特性インピーダンスコントロール対応プリント配線基板
USD720310S1 (en) * 2011-06-17 2014-12-30 Soraa, Inc. Triangular semiconductor die
KR20130033868A (ko) * 2011-09-27 2013-04-04 삼성전기주식회사 메쉬 패턴을 갖는 패키지 기판 및 그 제조방법
US8791371B2 (en) 2011-11-28 2014-07-29 International Business Machines Corporation Mesh planes with alternating spaces for multi-layered ceramic packages
US8952263B2 (en) * 2012-08-10 2015-02-10 Eastman Kodak Company Micro-wire electrode pattern
US20140216783A1 (en) * 2013-02-05 2014-08-07 David P. Trauernicht Micro-wire pattern with offset intersections
US20140216790A1 (en) * 2013-02-05 2014-08-07 David P. Trauernicht Conductive micro-wire structure with offset intersections
TWI457055B (zh) * 2013-02-20 2014-10-11 Novatek Microelectronics Corp 軟性電路板及其接地線結構
US9536848B2 (en) * 2014-10-16 2017-01-03 Globalfoundries Inc. Bond pad structure for low temperature flip chip bonding
JP6745712B2 (ja) 2016-11-30 2020-08-26 日東電工株式会社 配線回路基板およびその製造方法
JP6987700B2 (ja) * 2018-05-29 2022-01-05 京セラ株式会社 印刷配線板
CN114786328B (zh) * 2022-05-23 2024-04-30 西安易朴通讯技术有限公司 多层印制电路板

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855537A (en) * 1987-09-25 1989-08-08 Kabushiki Kaisha Toshiba Wiring substrate having mesh-shaped earth line
JPH05152768A (ja) 1991-11-27 1993-06-18 Nec Corp 多層構造基板
JPH05343820A (ja) 1992-06-04 1993-12-24 Toshiba Corp マルチチップモジュール用回路基板
JPH06326476A (ja) 1993-05-13 1994-11-25 Sony Corp 多層配線基板
JPH07202359A (ja) 1993-12-30 1995-08-04 Sony Corp 回路基板
JPH07302979A (ja) 1994-05-10 1995-11-14 Toshiba Corp 多層配線基板
JP3267148B2 (ja) 1996-04-03 2002-03-18 富士通株式会社 多層プリント配線板及び携帯型無線通信装置
JPH11298149A (ja) 1998-04-09 1999-10-29 Sumitomo Metal Ind Ltd 多層配線基板
TW476229B (en) 1998-08-24 2002-02-11 Adv Flexible Circuits Co Ltd Circuit board having shielding plate with empty-hole opening pattern to control impedance and transmission time
JP3307597B2 (ja) 1998-09-30 2002-07-24 株式会社 アドテック 印刷配線装置
US6433286B1 (en) * 2000-09-29 2002-08-13 Intel Corporation Method of making higher impedance traces on a low impedance circuit board
JP2003133659A (ja) 2001-10-19 2003-05-09 Kazunori Aoki 屈曲性能を具備した高周波用フレキシブルプリント配線板

Also Published As

Publication number Publication date
EP1720384A2 (de) 2006-11-08
EP1720384A3 (de) 2007-11-21
EP1720384B1 (de) 2010-09-29
JP2006310545A (ja) 2006-11-09
JP3872084B2 (ja) 2007-01-24
US7473854B2 (en) 2009-01-06
CN1856214A (zh) 2006-11-01
DE602006017141D1 (de) 2010-11-11
US20060246268A1 (en) 2006-11-02
CN1856214B (zh) 2010-09-01

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties