ATE476708T1 - Adressendecodierungsschema ohne kostenfaktor - Google Patents

Adressendecodierungsschema ohne kostenfaktor

Info

Publication number
ATE476708T1
ATE476708T1 AT01986244T AT01986244T ATE476708T1 AT E476708 T1 ATE476708 T1 AT E476708T1 AT 01986244 T AT01986244 T AT 01986244T AT 01986244 T AT01986244 T AT 01986244T AT E476708 T1 ATE476708 T1 AT E476708T1
Authority
AT
Austria
Prior art keywords
memory
decoding scheme
address decoding
cost factor
output
Prior art date
Application number
AT01986244T
Other languages
English (en)
Inventor
Erik Plesner
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Application granted granted Critical
Publication of ATE476708T1 publication Critical patent/ATE476708T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G06F12/0623—Address space extension for memory modules
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G06F2212/2022—Flash memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Static Random-Access Memory (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Executing Machine-Instructions (AREA)
  • Storage Device Security (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Communication Control (AREA)
  • Stored Programmes (AREA)
  • Semiconductor Memories (AREA)
AT01986244T 2001-12-20 2001-12-20 Adressendecodierungsschema ohne kostenfaktor ATE476708T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SE2001/002862 WO2002028162A2 (en) 2001-12-20 2001-12-20 Penalty free address decoding scheme

Publications (1)

Publication Number Publication Date
ATE476708T1 true ATE476708T1 (de) 2010-08-15

Family

ID=20285155

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01986244T ATE476708T1 (de) 2001-12-20 2001-12-20 Adressendecodierungsschema ohne kostenfaktor

Country Status (7)

Country Link
US (1) US20050021901A1 (de)
EP (1) EP1456757B1 (de)
CN (1) CN100380342C (de)
AT (1) ATE476708T1 (de)
AU (1) AU2002217672A1 (de)
DE (1) DE60142752D1 (de)
WO (1) WO2002028162A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6961281B2 (en) 2003-09-12 2005-11-01 Sun Microsystems, Inc. Single rank memory module for use in a two-rank memory module system
US7564735B2 (en) * 2006-07-05 2009-07-21 Qimonda Ag Memory device, and method for operating a memory device
US9281024B2 (en) 2014-04-17 2016-03-08 International Business Machines Corporation Write/read priority blocking scheme using parallel static address decode path

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3560943A (en) * 1968-01-29 1971-02-02 Bell Telephone Labor Inc Memory organization for two-way access
JPH06250931A (ja) * 1993-02-26 1994-09-09 Mitsubishi Electric Corp 情報処理装置
US5617559A (en) * 1994-08-31 1997-04-01 Motorola Inc. Modular chip select control circuit and method for performing pipelined memory accesses
US5913924A (en) * 1995-12-19 1999-06-22 Adaptec, Inc. Use of a stored signal to switch between memory banks
KR100204027B1 (ko) * 1996-02-16 1999-06-15 정선종 이중면 비휘발성 메모리를 이용한 데이타베이스 회복 장치 및 그 방법
US5765214A (en) * 1996-04-22 1998-06-09 Cypress Semiconductor Corporation Memory access method and apparatus and multi-plane memory device with prefetch
US5813041A (en) * 1996-06-06 1998-09-22 Motorola, Inc. Method for accessing memory by activating a programmable chip select signal
US6260103B1 (en) * 1998-01-05 2001-07-10 Intel Corporation Read-while-write memory including fewer verify sense amplifiers than read sense amplifiers
JP3920501B2 (ja) * 1999-04-02 2007-05-30 株式会社東芝 不揮発性半導体記憶装置及びそのデータ消去制御方法
US7046538B2 (en) * 2004-09-01 2006-05-16 Micron Technology, Inc. Memory stacking system and method

Also Published As

Publication number Publication date
AU2002217672A1 (en) 2002-04-15
CN100380342C (zh) 2008-04-09
DE60142752D1 (de) 2010-09-16
EP1456757A2 (de) 2004-09-15
EP1456757B1 (de) 2010-08-04
US20050021901A1 (en) 2005-01-27
CN1672134A (zh) 2005-09-21
WO2002028162A3 (en) 2002-10-24
WO2002028162A2 (en) 2002-04-11

Similar Documents

Publication Publication Date Title
ATE348455T1 (de) Fifo als übergang von taktregionen
KR960020510A (ko) 줄길이복호화기
ATE476708T1 (de) Adressendecodierungsschema ohne kostenfaktor
DE60234357D1 (de) Nung von dynamischen filtern
KR920003314A (ko) 반도체 메모리장치
KR970008190A (ko) 반도체장치의 모드 설정회로
TW428101B (en) Synchronous semiconductor memory apparatus
KR970022757A (ko) 메모리 소자내의 메인앰프의 배치구조
KR960043146A (ko) 본딩패드옵션을 구비한 집적회로장치와 본딩패드옵션의 실행방법
RU2001132281A (ru) Параллельная система поиска произвольных вхождений
KR950020133A (ko) 메모리 및 입/출력장치의 어드레스 디코딩장치
KR880000961A (ko) 영상 기억장치
RU95117901A (ru) Адаптивное устройство управления
KR970051443A (ko) 리페어 효율을 향상시킨 반도체 메모리 장치
KR940016226A (ko) 어드레스 핀을 이용한 상태 제어장치
KR960019988A (ko) 디바이스 식별어드레스 확장회로
RU2071221C1 (ru) Процессор для быстрого преобразования хартли
JPS6342092A (ja) 信号変化検出回路
KR960039627A (ko) 동기식 메모리소자의 입력버퍼
KR970051446A (ko) 리던던시 로오 디코더 회로
KR980004979A (ko) 반도체 메모리 장치
KR930022200A (ko) 퍼스널 컴퓨터 디버깅용 아답터보드
KR960025610A (ko) 음원발생장치
KR970051287A (ko) 메모리의 차지 펌핑회로
KR980006887A (ko) 컬럼 어드레스 버퍼 회로

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties