ATE464571T1 - Verfahren und testvorrichtung zur prüfung integrierter schaltungen - Google Patents

Verfahren und testvorrichtung zur prüfung integrierter schaltungen

Info

Publication number
ATE464571T1
ATE464571T1 AT06821206T AT06821206T ATE464571T1 AT E464571 T1 ATE464571 T1 AT E464571T1 AT 06821206 T AT06821206 T AT 06821206T AT 06821206 T AT06821206 T AT 06821206T AT E464571 T1 ATE464571 T1 AT E464571T1
Authority
AT
Austria
Prior art keywords
test
integrated circuit
providing
responses
test patterns
Prior art date
Application number
AT06821206T
Other languages
German (de)
English (en)
Inventor
Hendrikus Vranken
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE464571T1 publication Critical patent/ATE464571T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318364—Generation of test inputs, e.g. test vectors, patterns or sequences as a result of hardware simulation, e.g. in an HDL environment
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G01R31/318357—Simulation

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
AT06821206T 2005-11-04 2006-10-23 Verfahren und testvorrichtung zur prüfung integrierter schaltungen ATE464571T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05110387 2005-11-04
PCT/IB2006/053889 WO2007069098A1 (en) 2005-11-04 2006-10-23 Integrated circuit test method and test apparatus

Publications (1)

Publication Number Publication Date
ATE464571T1 true ATE464571T1 (de) 2010-04-15

Family

ID=37944819

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06821206T ATE464571T1 (de) 2005-11-04 2006-10-23 Verfahren und testvorrichtung zur prüfung integrierter schaltungen

Country Status (7)

Country Link
US (1) US8281197B2 (zh)
EP (1) EP1946132B1 (zh)
JP (1) JP2009515161A (zh)
CN (1) CN101300499B (zh)
AT (1) ATE464571T1 (zh)
DE (1) DE602006013681D1 (zh)
WO (1) WO2007069098A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101201386B (zh) * 2007-12-25 2011-06-15 电子科技大学 一种模拟集成电路参数型故障的定位方法
CN102156760B (zh) * 2010-08-23 2013-05-01 北京航空航天大学 基于Saber的电路故障仿真分析方法
US10101388B2 (en) 2015-12-15 2018-10-16 International Business Machines Corporation Method for enhanced semiconductor product diagnostic fail signature detection
CN113454471A (zh) * 2019-03-13 2021-09-28 美商新思科技有限公司 用于多个链缺陷的单次通过诊断

Family Cites Families (30)

* Cited by examiner, † Cited by third party
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US4194113A (en) * 1978-04-13 1980-03-18 Ncr Corporation Method and apparatus for isolating faults in a logic circuit
JPS62159246A (ja) 1986-01-08 1987-07-15 Hitachi Ltd 故障シミユレ−シヨン方式
JPH04264276A (ja) 1991-02-19 1992-09-21 Nippon Telegr & Teleph Corp <Ntt> 組み込み自己試験回路及び制御方式
JP3151787B2 (ja) 1992-09-24 2001-04-03 日本電信電話株式会社 集積回路の組み込み自己試験回路及びその評価方法及び設計方法
US5475694A (en) * 1993-01-19 1995-12-12 The University Of British Columbia Fuzzy multiple signature compaction scheme for built-in self-testing of large scale digital integrated circuits
JPH11174126A (ja) 1997-12-15 1999-07-02 Matsushita Electric Ind Co Ltd 論理回路の組込み自己検査パターン発生装置およびパタ ーン選定方法
JPH11202026A (ja) 1998-01-13 1999-07-30 Hitachi Ltd 不良解析手法
US6249893B1 (en) 1998-10-30 2001-06-19 Advantest Corp. Method and structure for testing embedded cores based system-on-a-chip
US6347395B1 (en) * 1998-12-18 2002-02-12 Koninklijke Philips Electronics N.V. (Kpenv) Method and arrangement for rapid silicon prototyping
CA2363531C (en) * 1999-02-22 2007-07-31 Jeewoo Lee Vanilloid analogues containing resiniferatoxin pharmacophores as potent vanilloid receptor agonists and analgesics, compositions and uses thereof
US6684358B1 (en) * 1999-11-23 2004-01-27 Janusz Rajski Decompressor/PRPG for applying pseudo-random and deterministic test patterns
EP1242885B1 (en) * 1999-11-23 2009-10-07 Mentor Graphics Corporation Continuous application and decompression of test patterns to a circuit-under-test
JP3732708B2 (ja) 2000-03-27 2006-01-11 株式会社東芝 テストパターン選別装置、テストパターン選別方法およびテストパターン選別プログラムを格納したコンピュータ読取り可能な記録媒体
US6971054B2 (en) * 2000-11-27 2005-11-29 International Business Machines Corporation Method and system for determining repeatable yield detractors of integrated circuits
US7007213B2 (en) * 2001-02-15 2006-02-28 Syntest Technologies, Inc. Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
JP3851782B2 (ja) 2001-03-07 2006-11-29 株式会社東芝 半導体集積回路及びそのテスト方法
US6681357B2 (en) * 2001-05-31 2004-01-20 Sun Microsystems, Inc. MISR simulation tool for memory BIST application
US7246277B2 (en) * 2001-06-20 2007-07-17 Jeffrey Lukanc Test bus architecture for embedded RAM and method of operating same
US7552373B2 (en) * 2002-01-16 2009-06-23 Syntest Technologies, Inc. Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit
US7437640B2 (en) * 2003-02-13 2008-10-14 Janusz Rajski Fault diagnosis of compressed test responses having one or more unknown states
US7509550B2 (en) * 2003-02-13 2009-03-24 Janusz Rajski Fault diagnosis of compressed test responses
CN1548974A (zh) * 2003-05-16 2004-11-24 中国科学院计算技术研究所 超大规模集成电路测试通道压缩方法及电路
CN1277181C (zh) * 2003-06-25 2006-09-27 中国科学院计算技术研究所 一种单输出无反馈时序测试响应压缩电路
DE602004009329T2 (de) * 2003-09-26 2008-07-10 Nxp B.V. Verfahren und system zum selektiven maskieren von testantworten
US7055077B2 (en) * 2003-12-23 2006-05-30 Kabushiki Kaisha Toshiba Systems and methods for circuit testing
US8280687B2 (en) * 2004-03-31 2012-10-02 Mentor Graphics Corporation Direct fault diagnostics using per-pattern compactor signatures
US7461312B2 (en) * 2004-07-22 2008-12-02 Microsoft Corporation Digital signature generation for hardware functional test
TW200622275A (en) * 2004-09-06 2006-07-01 Mentor Graphics Corp Integrated circuit yield and quality analysis methods and systems
US7487420B2 (en) * 2005-02-15 2009-02-03 Cadence Design Systems Inc. System and method for performing logic failure diagnosis using multiple input signature register output streams
US7509551B2 (en) * 2005-08-01 2009-03-24 Bernd Koenemann Direct logic diagnostics with signature-based fault dictionaries

Also Published As

Publication number Publication date
DE602006013681D1 (de) 2010-05-27
EP1946132A1 (en) 2008-07-23
JP2009515161A (ja) 2009-04-09
US8281197B2 (en) 2012-10-02
US20090077439A1 (en) 2009-03-19
CN101300499B (zh) 2011-05-18
EP1946132B1 (en) 2010-04-14
WO2007069098A1 (en) 2007-06-21
CN101300499A (zh) 2008-11-05

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