DE69814176D1 - Verfahren und gerät zum automatischen test eines simulierten integrierten schaltkreises - Google Patents

Verfahren und gerät zum automatischen test eines simulierten integrierten schaltkreises

Info

Publication number
DE69814176D1
DE69814176D1 DE69814176T DE69814176T DE69814176D1 DE 69814176 D1 DE69814176 D1 DE 69814176D1 DE 69814176 T DE69814176 T DE 69814176T DE 69814176 T DE69814176 T DE 69814176T DE 69814176 D1 DE69814176 D1 DE 69814176D1
Authority
DE
Germany
Prior art keywords
integrated circuit
automatically testing
flip
simulated integrated
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69814176T
Other languages
English (en)
Other versions
DE69814176T2 (de
Inventor
David Baker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Conexant Systems UK Ltd
Original Assignee
Virata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Virata Ltd filed Critical Virata Ltd
Application granted granted Critical
Publication of DE69814176D1 publication Critical patent/DE69814176D1/de
Publication of DE69814176T2 publication Critical patent/DE69814176T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318522—Test of Sequential circuits
    • G01R31/31853—Test of registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69814176T 1997-11-25 1998-11-11 Verfahren und gerät zum automatischen test eines simulierten integrierten schaltkreises Expired - Fee Related DE69814176T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB9724895 1997-11-25
GBGB9724895.9A GB9724895D0 (en) 1997-11-25 1997-11-25 Method and apparatus for automatically testing the design of a simulated integrated circuit
PCT/GB1998/003384 WO1999027472A1 (en) 1997-11-25 1998-11-11 Method and apparatus for automatically testing the design of a simulated integrated circuit

Publications (2)

Publication Number Publication Date
DE69814176D1 true DE69814176D1 (de) 2003-06-05
DE69814176T2 DE69814176T2 (de) 2004-03-25

Family

ID=10822614

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69814176T Expired - Fee Related DE69814176T2 (de) 1997-11-25 1998-11-11 Verfahren und gerät zum automatischen test eines simulierten integrierten schaltkreises

Country Status (7)

Country Link
EP (1) EP1070297B1 (de)
AT (1) ATE239262T1 (de)
AU (1) AU1045899A (de)
DE (1) DE69814176T2 (de)
GB (1) GB9724895D0 (de)
IL (1) IL135259A (de)
WO (1) WO1999027472A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014052936A1 (en) * 2012-09-28 2014-04-03 Arteris SAS Automatic safety logic insertion

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994023388A1 (en) * 1993-03-31 1994-10-13 Alcatel N.V. Method for solving asynchronisms in digital logic simulators

Also Published As

Publication number Publication date
EP1070297B1 (de) 2003-05-02
GB9724895D0 (en) 1998-01-28
IL135259A (en) 2004-06-01
AU1045899A (en) 1999-06-15
EP1070297A1 (de) 2001-01-24
IL135259A0 (en) 2001-05-20
ATE239262T1 (de) 2003-05-15
DE69814176T2 (de) 2004-03-25
WO1999027472A1 (en) 1999-06-03

Similar Documents

Publication Publication Date Title
KR960011441A (ko) 프로브 테스트 핸들러와 그를 사용한 ic 테스팅 방법 및 ic
ATE273520T1 (de) System und verfahren zur prüfung von integrierten schaltungen
EP1360513A4 (de) Mehrfacherfassungs-dft-system zum detektieren oder auffinden von überschreitenden taktbereichsfehlern während der selbstprüfung oder scan-prüfung
ATE410700T1 (de) Verfahren und vorrichtung zur bereitstellung eines optimierten zugangs zu schaltungen zum debuggen, programmieren und prüfen
ATE390637T1 (de) Verfahren und vorrichtung zum prüfen integrierter schaltungen
FI873793A (fi) Foerfarande och anordning foer isolering av fel i en digital logisk krets.
ATE370423T1 (de) Verfahren und vorrichtung zur optimierten parallelen prüfung und zum zugriff auf elektronische schaltung
DE2963143D1 (en) Method of and apparatus for testing electronic circuit assemblies and the like
TW352466B (en) Apparatus and method for testing integrated circuit
TW200608032A (en) Method and apparatus for configuration of automated debug of in-circuit tests
WO2004040324A3 (en) A method of and apparatus for testing for integrated circuit contact defects
MY124258A (en) Method of testing electronic components and testing apparatus for electronic components
DE69230478T2 (de) Prüfmustererzeugungseinrichtung für sequentielle Logikschaltung einer integrierten Schaltung und Verfahren dazu
WO2007031938A3 (en) Development of assertions for integrated circuit design simulation
DE69814176D1 (de) Verfahren und gerät zum automatischen test eines simulierten integrierten schaltkreises
ATE464571T1 (de) Verfahren und testvorrichtung zur prüfung integrierter schaltungen
DE69026212D1 (de) Wechselstromvorrichtung zum Prüfen eines IC-Testgerätes
Bushnell Increasing Test Coverage in a VLSI Design Course
DE602004000226D1 (de) Parallele Prüfung von Intergrierten Schaltungen
Liebelt The testability of microprocessor systems: an assessment of signature analysis as a method of field-service
DE50106894D1 (de) Test-schaltungsanordnung und verfahren zum testen einer vielzahl von elektrischen komponenten
WO2004107402A3 (en) Smart capture for atpg (automatic test pattern generation) and fault simulation of scan-based integrated circuits
Debany A military test method for measuring fault coverage
Balaz et al. eTool for teaching and application of digital system testability techniques
Hermann et al. TTBist: a DfT Tool for Enhancing Functional Test for SoC

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee