ATE410700T1 - Verfahren und vorrichtung zur bereitstellung eines optimierten zugangs zu schaltungen zum debuggen, programmieren und prüfen - Google Patents

Verfahren und vorrichtung zur bereitstellung eines optimierten zugangs zu schaltungen zum debuggen, programmieren und prüfen

Info

Publication number
ATE410700T1
ATE410700T1 AT01918854T AT01918854T ATE410700T1 AT E410700 T1 ATE410700 T1 AT E410700T1 AT 01918854 T AT01918854 T AT 01918854T AT 01918854 T AT01918854 T AT 01918854T AT E410700 T1 ATE410700 T1 AT E410700T1
Authority
AT
Austria
Prior art keywords
access interface
electronic circuit
programming
debugging
testing
Prior art date
Application number
AT01918854T
Other languages
English (en)
Inventor
Michael Ricchetti
Christopher Clark
Bulent Dervisoglu
Original Assignee
Intellitech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intellitech Corp filed Critical Intellitech Corp
Application granted granted Critical
Publication of ATE410700T1 publication Critical patent/ATE410700T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT01918854T 2000-03-23 2001-03-20 Verfahren und vorrichtung zur bereitstellung eines optimierten zugangs zu schaltungen zum debuggen, programmieren und prüfen ATE410700T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US19160200P 2000-03-23 2000-03-23
US09/716,583 US6594802B1 (en) 2000-03-23 2000-11-20 Method and apparatus for providing optimized access to circuits for debug, programming, and test

Publications (1)

Publication Number Publication Date
ATE410700T1 true ATE410700T1 (de) 2008-10-15

Family

ID=26887206

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01918854T ATE410700T1 (de) 2000-03-23 2001-03-20 Verfahren und vorrichtung zur bereitstellung eines optimierten zugangs zu schaltungen zum debuggen, programmieren und prüfen

Country Status (8)

Country Link
US (1) US6594802B1 (de)
EP (1) EP1275183B1 (de)
AT (1) ATE410700T1 (de)
AU (1) AU2001245878A1 (de)
CA (1) CA2404059C (de)
DE (1) DE60136059D1 (de)
HK (1) HK1052586A1 (de)
WO (1) WO2001071876A1 (de)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7308629B2 (en) * 2004-12-07 2007-12-11 Texas Instruments Incorporated Addressable tap domain selection circuit with TDI/TDO external terminal
US6694467B2 (en) * 1999-06-24 2004-02-17 Texas Instruments Incorporated Low power testing of very large circuits
US7200783B2 (en) * 2003-11-04 2007-04-03 Texas Instruments Incorporated Removable and replaceable TAP domain selection circuitry
US7356786B2 (en) * 1999-11-30 2008-04-08 Synplicity, Inc. Method and user interface for debugging an electronic system
US7065481B2 (en) * 1999-11-30 2006-06-20 Synplicity, Inc. Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzer
US6823497B2 (en) 1999-11-30 2004-11-23 Synplicity, Inc. Method and user interface for debugging an electronic system
US6931572B1 (en) 1999-11-30 2005-08-16 Synplicity, Inc. Design instrumentation circuitry
US7072818B1 (en) * 1999-11-30 2006-07-04 Synplicity, Inc. Method and system for debugging an electronic system
US6769080B2 (en) * 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
EP1146343B1 (de) * 2000-03-09 2005-02-23 Texas Instruments Incorporated Anpassung von "Scan-BIST"-Architekturen für einen Betrieb mit niedrigem Verbrauch
US7222315B2 (en) * 2000-11-28 2007-05-22 Synplicity, Inc. Hardware-based HDL code coverage and design analysis
US6652265B2 (en) * 2000-12-06 2003-11-25 North American Manufacturing Company Burner apparatus and method
ITMI20010997A1 (it) * 2001-05-16 2002-11-16 Cit Alcatel Metodi per testare il software di controllo di una apparecchiatura per telecomunicazioni dotata di un controllo di tipo distribuito
US7231551B1 (en) * 2001-06-29 2007-06-12 Mips Technologies, Inc. Distributed tap controller
JP3974110B2 (ja) * 2001-07-05 2007-09-12 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ テストインタフェースを有する装置
US6662134B2 (en) * 2001-11-01 2003-12-09 Agilent Technologies, Inc. Method and apparatus for enabling extests to be performed in AC-coupled systems
CA2473956A1 (en) * 2002-01-23 2003-07-31 Intellitech Corporation Management system, method and apparatus for licensed delivery and accounting of electronic circuits
KR100471544B1 (ko) * 2002-05-30 2005-03-10 주식회사 유니테스트 실장과 에이티이가 통합된 반도체 소자 테스트 장치
US7827510B1 (en) 2002-06-07 2010-11-02 Synopsys, Inc. Enhanced hardware debugging with embedded FPGAS in a hardware description language
JP2004021833A (ja) * 2002-06-19 2004-01-22 Renesas Technology Corp 自己テスト機能内蔵半導体集積回路およびそれを備えたシステム
US7058918B2 (en) 2003-04-28 2006-06-06 Dafca, Inc. Reconfigurable fabric for SoCs using functional I/O leads
US7506210B1 (en) 2003-06-26 2009-03-17 Xilinx, Inc. Method of debugging PLD configuration using boundary scan
US20050108228A1 (en) * 2003-11-05 2005-05-19 Larson Lee A. Apparatus and method for performing a polling operation of a single bit in a JTAG data stream
EP1687943A1 (de) * 2003-11-19 2006-08-09 Honeywell International, Inc. Clique-aggregation in tdma-netzwerken
US7372859B2 (en) * 2003-11-19 2008-05-13 Honeywell International Inc. Self-checking pair on a braided ring network
US7149943B2 (en) * 2004-01-12 2006-12-12 Lucent Technologies Inc. System for flexible embedded Boundary Scan testing
US7895301B1 (en) * 2004-05-21 2011-02-22 Uei Cayman Inc. Transmitting a codeset over a single-wire bus from a computer to a remote control device
TWI274166B (en) * 2004-06-18 2007-02-21 Unitest Inc Semiconductor test apparatus for simultaneously testing plurality of semiconductor devices
US7293199B1 (en) * 2004-06-22 2007-11-06 Sun Microsystems, Inc. Method and apparatus for testing memories with different read/write protocols using the same programmable memory bist controller
US7480843B1 (en) * 2004-09-29 2009-01-20 Xilinx, Inc. Configuration access from a boundary-scannable device
US7248070B1 (en) 2005-02-16 2007-07-24 Altera Corporation Method and system for using boundary scan in a programmable logic device
US8000954B2 (en) 2005-03-16 2011-08-16 Gaterocket, Inc. FPGA emulation system
US7685487B1 (en) * 2005-03-22 2010-03-23 Advanced Micro Devices, Inc. Simultaneous core testing in multi-core integrated circuits
US8205186B1 (en) 2005-04-11 2012-06-19 Synopsys, Inc. Incremental modification of instrumentation logic
US7428674B1 (en) * 2006-01-17 2008-09-23 Xilinx, Inc. Monitoring the state vector of a test access port
US7533315B2 (en) * 2006-03-06 2009-05-12 Mediatek Inc. Integrated circuit with scan-based debugging and debugging method thereof
US20070245040A1 (en) * 2006-04-14 2007-10-18 Acsadi Peter F Data storing
US7823097B2 (en) * 2006-09-15 2010-10-26 International Business Machines Corporation Unrolling hardware design generate statements in a source window debugger
US7668084B2 (en) * 2006-09-29 2010-02-23 Honeywell International Inc. Systems and methods for fault-tolerant high integrity data propagation using a half-duplex braided ring network
US7889683B2 (en) * 2006-11-03 2011-02-15 Honeywell International Inc. Non-destructive media access resolution for asynchronous traffic in a half-duplex braided-ring
US7912094B2 (en) * 2006-12-13 2011-03-22 Honeywell International Inc. Self-checking pair-based master/follower clock synchronization
US7656881B2 (en) * 2006-12-13 2010-02-02 Honeywell International Inc. Methods for expedited start-up and clique aggregation using self-checking node pairs on a ring network
US7877653B2 (en) 2007-05-09 2011-01-25 Texas Instruments Incorporated Address and TMS gating circuitry for TAP control circuit
US7778159B2 (en) * 2007-09-27 2010-08-17 Honeywell International Inc. High-integrity self-test in a network having a braided-ring topology
US8817597B2 (en) * 2007-11-05 2014-08-26 Honeywell International Inc. Efficient triple modular redundancy on a braided ring
US8108742B2 (en) 2009-06-11 2012-01-31 Texas Instruments Incorporated Tap control of TCA scan clock and scan enable
US8065578B2 (en) * 2009-09-14 2011-11-22 Texas Instruments Incorporated Inverted TCK access port selector selecting one of plural TAPs
US8127187B2 (en) * 2009-09-30 2012-02-28 Integrated Device Technology, Inc. Method and apparatus of ATE IC scan test using FPGA-based system
EP2749894A1 (de) 2012-12-31 2014-07-02 Testonica Lab Oü System und Verfahren für optimierte Leiterplattenprüfung und -konfiguration
US9164858B2 (en) 2013-03-29 2015-10-20 Testonica Lab Ou System and method for optimized board test and configuration
US10067854B2 (en) * 2016-10-25 2018-09-04 Xilinx, Inc. System and method for debugging software executed as a hardware simulation

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5755456A (en) * 1980-09-19 1982-04-02 Hitachi Ltd Career recording system
US5329471A (en) * 1987-06-02 1994-07-12 Texas Instruments Incorporated Emulation devices, systems and methods utilizing state machines
US5684721A (en) 1987-09-04 1997-11-04 Texas Instruments Incorporated Electronic systems and emulation and testing devices, cables, systems and methods
US5048021A (en) * 1989-08-28 1991-09-10 At&T Bell Laboratories Method and apparatus for generating control signals
US5231314A (en) 1992-03-02 1993-07-27 National Semiconductor Corporation Programmable timing circuit for integrated circuit device with test access port
US5495486A (en) 1992-08-11 1996-02-27 Crosscheck Technology, Inc. Method and apparatus for testing integrated circuits
US5357572A (en) 1992-09-22 1994-10-18 Hughes Aircraft Company Apparatus and method for sensitive circuit protection with set-scan testing
US5333139A (en) * 1992-12-30 1994-07-26 Intel Corporation Method of determining the number of individual integrated circuit computer chips or the like in a boundary scan test chain and the length of the chain
US6006343A (en) 1993-07-30 1999-12-21 Texas Instruments Incorporated Method and apparatus for streamlined testing of electrical circuits
US5526365A (en) * 1993-07-30 1996-06-11 Texas Instruments Incorporated Method and apparatus for streamlined testing of electrical circuits
US5677915A (en) * 1993-08-18 1997-10-14 Texas Instruments Incorporated Customized method and apparatus for streamlined testing a particular electrical circuit
US5596734A (en) 1993-12-17 1997-01-21 Intel Corporation Method and apparatus for programming embedded memories of a variety of integrated circuits using the IEEE test access port
US5682392A (en) 1994-09-28 1997-10-28 Teradyne, Inc. Method and apparatus for the automatic generation of boundary scan description language files
US5708773A (en) * 1995-07-20 1998-01-13 Unisys Corporation JTAG interface system for communicating with compliant and non-compliant JTAG devices
US5887146A (en) * 1995-08-14 1999-03-23 Data General Corporation Symmetric multiprocessing computer with non-uniform memory access architecture
US5627840A (en) 1995-09-15 1997-05-06 Unisys Corp. Memory based interface
US5650734A (en) 1995-12-11 1997-07-22 Altera Corporation Programming programmable transistor devices using state machines
US5752006A (en) * 1996-01-31 1998-05-12 Xilinx, Inc. Configuration emulation of a programmable logic device
US5648973A (en) * 1996-02-06 1997-07-15 Ast Research, Inc. I/O toggle test method using JTAG
US5694399A (en) * 1996-04-10 1997-12-02 Xilinix, Inc. Processing unit for generating signals for communication with a test access port
US5844917A (en) * 1997-04-08 1998-12-01 International Business Machines Corporation Method for testing adapter card ASIC using reconfigurable logic
US6026230A (en) * 1997-05-02 2000-02-15 Axis Systems, Inc. Memory simulation system and method
US5995424A (en) * 1997-07-16 1999-11-30 Tanisys Technology, Inc. Synchronous memory test system
US6032279A (en) * 1997-11-07 2000-02-29 Atmel Corporation Boundary scan system with address dependent instructions
US6016555A (en) 1997-11-19 2000-01-18 Texas Instruments Incorporated Non-intrusive software breakpoints in a processor instruction execution pipeline
US6158034A (en) * 1998-12-03 2000-12-05 Atmel Corporation Boundary scan method for terminating or modifying integrated circuit operating modes

Also Published As

Publication number Publication date
EP1275183A4 (de) 2005-01-19
CA2404059C (en) 2004-06-01
AU2001245878A1 (en) 2001-10-03
CA2404059A1 (en) 2001-09-27
EP1275183B1 (de) 2008-10-08
EP1275183A1 (de) 2003-01-15
HK1052586A1 (en) 2003-09-19
DE60136059D1 (de) 2008-11-20
WO2001071876A1 (en) 2001-09-27
US6594802B1 (en) 2003-07-15

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