ATE426897T1 - System und verfahren zur selbstpr fung und reparatur von speichermodulen - Google Patents

System und verfahren zur selbstpr fung und reparatur von speichermodulen

Info

Publication number
ATE426897T1
ATE426897T1 AT03788336T AT03788336T ATE426897T1 AT E426897 T1 ATE426897 T1 AT E426897T1 AT 03788336 T AT03788336 T AT 03788336T AT 03788336 T AT03788336 T AT 03788336T AT E426897 T1 ATE426897 T1 AT E426897T1
Authority
AT
Austria
Prior art keywords
memory
defective
locations
hub
repair
Prior art date
Application number
AT03788336T
Other languages
English (en)
Inventor
Joseph Jeddeloh
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE426897T1 publication Critical patent/ATE426897T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/76Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44Indication or identification of errors, e.g. for repair
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44Indication or identification of errors, e.g. for repair
    • G11C29/4401Indication or identification of errors, e.g. for repair for self repair
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5606Error catch memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Pens And Brushes (AREA)
  • Dot-Matrix Printers And Others (AREA)
AT03788336T 2002-08-16 2003-08-05 System und verfahren zur selbstpr fung und reparatur von speichermodulen ATE426897T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/222,393 US6754117B2 (en) 2002-08-16 2002-08-16 System and method for self-testing and repair of memory modules

Publications (1)

Publication Number Publication Date
ATE426897T1 true ATE426897T1 (de) 2009-04-15

Family

ID=31714947

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03788336T ATE426897T1 (de) 2002-08-16 2003-08-05 System und verfahren zur selbstpr fung und reparatur von speichermodulen

Country Status (10)

Country Link
US (1) US6754117B2 (de)
EP (1) EP1535131B1 (de)
JP (1) JP4431977B2 (de)
KR (1) KR100848254B1 (de)
CN (1) CN100578656C (de)
AT (1) ATE426897T1 (de)
AU (1) AU2003258104A1 (de)
DE (1) DE60326854D1 (de)
TW (1) TWI242780B (de)
WO (1) WO2004017162A2 (de)

Families Citing this family (110)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5526320A (en) 1994-12-23 1996-06-11 Micron Technology Inc. Burst EDO memory device
US7010642B2 (en) * 2000-01-05 2006-03-07 Rambus Inc. System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices
US7028213B2 (en) * 2001-09-28 2006-04-11 Hewlett-Packard Development Company, L.P. Error indication in a raid memory system
US6836438B2 (en) * 2002-01-11 2004-12-28 Macronix International Co., Ltd. Method and apparatus for dynamically hiding a defect in an embedded memory
US7133972B2 (en) 2002-06-07 2006-11-07 Micron Technology, Inc. Memory hub with internal cache and/or memory access prediction
GB2405724B (en) * 2002-06-24 2006-02-08 Samsung Electronics Co Ltd Memory module having a path for transmitting high-speed data and a path for transmitting low-speed data and memory system having the memory module
US7117316B2 (en) 2002-08-05 2006-10-03 Micron Technology, Inc. Memory hub and access method having internal row caching
US7149874B2 (en) * 2002-08-16 2006-12-12 Micron Technology, Inc. Memory hub bypass circuit and method
US6820181B2 (en) * 2002-08-29 2004-11-16 Micron Technology, Inc. Method and system for controlling memory accesses to memory modules having a memory hub architecture
US7836252B2 (en) * 2002-08-29 2010-11-16 Micron Technology, Inc. System and method for optimizing interconnections of memory devices in a multichip module
US7102907B2 (en) * 2002-09-09 2006-09-05 Micron Technology, Inc. Wavelength division multiplexed memory module, memory system and method
US7007211B1 (en) * 2002-10-04 2006-02-28 Cisco Technology, Inc. Testing self-repairing memory of a device
US7111213B1 (en) * 2002-12-10 2006-09-19 Altera Corporation Failure isolation and repair techniques for integrated circuits
US6934199B2 (en) * 2002-12-11 2005-08-23 Micron Technology, Inc. Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
US6961259B2 (en) * 2003-01-23 2005-11-01 Micron Technology, Inc. Apparatus and methods for optically-coupled memory systems
US7184916B2 (en) * 2003-05-20 2007-02-27 Cray Inc. Apparatus and method for testing memory cards
US7320100B2 (en) 2003-05-20 2008-01-15 Cray Inc. Apparatus and method for memory with bit swapping on the fly and testing
US20040243769A1 (en) * 2003-05-30 2004-12-02 Frame David W. Tree based memory structure
US7245145B2 (en) 2003-06-11 2007-07-17 Micron Technology, Inc. Memory module and method having improved signal routing topology
US7120727B2 (en) 2003-06-19 2006-10-10 Micron Technology, Inc. Reconfigurable memory module and method
US7107415B2 (en) * 2003-06-20 2006-09-12 Micron Technology, Inc. Posted write buffers and methods of posting write requests in memory modules
US7260685B2 (en) * 2003-06-20 2007-08-21 Micron Technology, Inc. Memory hub and access method having internal prefetch buffers
KR100500454B1 (ko) * 2003-07-28 2005-07-12 삼성전자주식회사 메모리 모듈 테스트 시스템 및 메모리 모듈 평가 시스템
DE10335708B4 (de) * 2003-08-05 2009-02-26 Qimonda Ag Hub-Baustein zum Anschließen von einem oder mehreren Speicherbausteinen
DE10335978B4 (de) * 2003-08-06 2006-02-16 Infineon Technologies Ag Hub-Baustein zum Anschließen von einem oder mehreren Speicherbausteinen
US7210059B2 (en) * 2003-08-19 2007-04-24 Micron Technology, Inc. System and method for on-board diagnostics of memory modules
US7133991B2 (en) * 2003-08-20 2006-11-07 Micron Technology, Inc. Method and system for capturing and bypassing memory transactions in a hub-based memory system
US7310752B2 (en) 2003-09-12 2007-12-18 Micron Technology, Inc. System and method for on-board timing margin testing of memory modules
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US6996749B1 (en) * 2003-11-13 2006-02-07 Intel Coporation Method and apparatus for providing debug functionality in a buffered memory channel
US20050138302A1 (en) * 2003-12-23 2005-06-23 Intel Corporation (A Delaware Corporation) Method and apparatus for logic analyzer observability of buffered memory module links
US7330992B2 (en) * 2003-12-29 2008-02-12 Micron Technology, Inc. System and method for read synchronization of memory modules
US7216196B2 (en) * 2003-12-29 2007-05-08 Micron Technology, Inc. Memory hub and method for memory system performance monitoring
US7188219B2 (en) * 2004-01-30 2007-03-06 Micron Technology, Inc. Buffer control system and method for a memory system having outstanding read and write request buffers
US7366864B2 (en) 2004-03-08 2008-04-29 Micron Technology, Inc. Memory hub architecture having programmable lane widths
US7082075B2 (en) * 2004-03-18 2006-07-25 Micron Technology, Inc. Memory device and method having banks of different sizes
US7120723B2 (en) 2004-03-25 2006-10-10 Micron Technology, Inc. System and method for memory hub-based expansion bus
US7590797B2 (en) 2004-04-08 2009-09-15 Micron Technology, Inc. System and method for optimizing interconnections of components in a multichip memory module
US7162567B2 (en) * 2004-05-14 2007-01-09 Micron Technology, Inc. Memory hub and method for memory sequencing
US7222213B2 (en) * 2004-05-17 2007-05-22 Micron Technology, Inc. System and method for communicating the synchronization status of memory modules during initialization of the memory modules
US7519788B2 (en) 2004-06-04 2009-04-14 Micron Technology, Inc. System and method for an asynchronous data buffer having buffer write and read pointers
US7310748B2 (en) 2004-06-04 2007-12-18 Micron Technology, Inc. Memory hub tester interface and method for use thereof
KR100624576B1 (ko) 2004-06-11 2006-09-19 삼성전자주식회사 허브를 갖는 메모리 모듈을 테스트하는 방법 및 이를수행하기 위한 메모리 모듈의 허브
CN100337285C (zh) * 2004-07-13 2007-09-12 海信集团有限公司 一种对NAND flash存储器进行物理损坏模拟的系统及其方法
DE102004039393B4 (de) * 2004-08-13 2008-04-17 Qimonda Ag Verfahren zum Testen einer Speichervorrichtung und Speichervorrichtung zur Durchführung des Verfahrens
US7392331B2 (en) 2004-08-31 2008-06-24 Micron Technology, Inc. System and method for transmitting data packets in a computer system having a memory hub architecture
DE102004042074A1 (de) * 2004-08-31 2006-03-09 Infineon Technologies Ag Verfahren zum Testen eines Speichers mittels externem Testchip und Vorrichtung zur Durchführung des Verfahrens
KR100565889B1 (ko) * 2004-11-03 2006-03-31 삼성전자주식회사 메모리 테스트 방법, 메모리 모듈의 허브 및 이를 가지는풀리 버퍼드 듀얼인라인 메모리 모듈
US7409623B2 (en) 2004-11-04 2008-08-05 Sigmatel, Inc. System and method of reading non-volatile computer memory
KR100557221B1 (ko) * 2004-11-04 2006-03-07 삼성전자주식회사 메모리 모듈에서의 신호 무결성 테스트 방법 및 이를 위한메모리 모듈의 버퍼
US7523364B2 (en) * 2005-02-09 2009-04-21 International Business Machines Corporation Double DRAM bit steering for multiple error corrections
US7262354B2 (en) * 2005-03-04 2007-08-28 Orred Gregory D Stringed practice device and method
KR100666612B1 (ko) * 2005-05-27 2007-01-09 삼성전자주식회사 리던던시 코드 체크 기능을 가지는 반도체 메모리 장치 및그것을 구비한 메모리 시스템
US7328381B2 (en) * 2005-08-01 2008-02-05 Micron Technology, Inc. Testing system and method for memory modules having a memory hub architecture
US7319340B2 (en) * 2005-08-01 2008-01-15 Micron Technology, Inc. Integrated circuit load board and method having on-board test circuit
US7765424B2 (en) * 2005-08-19 2010-07-27 Micron Technology, Inc. System and method for injecting phase jitter into integrated circuit test signals
US11328764B2 (en) 2005-09-26 2022-05-10 Rambus Inc. Memory system topologies including a memory die stack
US7562271B2 (en) 2005-09-26 2009-07-14 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US7464225B2 (en) 2005-09-26 2008-12-09 Rambus Inc. Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
US20070118778A1 (en) * 2005-11-10 2007-05-24 Via Telecom Co., Ltd. Method and/or apparatus to detect and handle defects in a memory
US7355387B2 (en) * 2005-12-08 2008-04-08 Micron Technology, Inc. System and method for testing integrated circuit timing margins
US7284169B2 (en) * 2005-12-08 2007-10-16 Micron Technology, Inc. System and method for testing write strobe timing margins in memory devices
US7539912B2 (en) 2005-12-15 2009-05-26 King Tiger Technology, Inc. Method and apparatus for testing a fully buffered memory module
US7478285B2 (en) * 2005-12-30 2009-01-13 Silicon Graphics, Inc. Generation and use of system level defect tables for main memory
US7471538B2 (en) * 2006-03-30 2008-12-30 Micron Technology, Inc. Memory module, system and method of making same
US7277337B1 (en) 2006-09-25 2007-10-02 Kingston Technology Corp. Memory module with a defective memory chip having defective blocks disabled by non-multiplexed address lines to the defective chip
US7856576B2 (en) * 2007-04-25 2010-12-21 Hewlett-Packard Development Company, L.P. Method and system for managing memory transactions for memory repair
US7620861B2 (en) * 2007-05-31 2009-11-17 Kingtiger Technology (Canada) Inc. Method and apparatus for testing integrated circuits by employing test vector patterns that satisfy passband requirements imposed by communication channels
US7945815B2 (en) 2007-08-14 2011-05-17 Dell Products L.P. System and method for managing memory errors in an information handling system
US7694195B2 (en) 2007-08-14 2010-04-06 Dell Products L.P. System and method for using a memory mapping function to map memory defects
US7949913B2 (en) * 2007-08-14 2011-05-24 Dell Products L.P. Method for creating a memory defect map and optimizing performance using the memory defect map
US9373362B2 (en) * 2007-08-14 2016-06-21 Dell Products L.P. System and method for implementing a memory defect map
US7757144B2 (en) * 2007-11-01 2010-07-13 Kingtiger Technology (Canada) Inc. System and method for testing integrated circuit modules comprising a plurality of integrated circuit devices
TW200921691A (en) * 2007-11-14 2009-05-16 Etron Technology Inc Method for controlling a dram
US8090935B2 (en) * 2008-01-24 2012-01-03 Mentor Graphics Corporation Direct register access for host simulation
US9229887B2 (en) * 2008-02-19 2016-01-05 Micron Technology, Inc. Memory device with network on chip methods, apparatus, and systems
US8001434B1 (en) 2008-04-14 2011-08-16 Netlist, Inc. Memory board with self-testing capability
US7848899B2 (en) * 2008-06-09 2010-12-07 Kingtiger Technology (Canada) Inc. Systems and methods for testing integrated circuit devices
US7978721B2 (en) 2008-07-02 2011-07-12 Micron Technology Inc. Multi-serial interface stacked-die memory architecture
US8086913B2 (en) 2008-09-11 2011-12-27 Micron Technology, Inc. Methods, apparatus, and systems to repair memory
US20100169729A1 (en) * 2008-12-30 2010-07-01 Datta Shamanna M Enabling an integrated memory controller to transparently work with defective memory devices
TWI409820B (zh) * 2009-02-18 2013-09-21 King Yuan Electronics Co Ltd Semiconductor Test System with Self - Test for Memory Repair Analysis
WO2011062825A2 (en) 2009-11-20 2011-05-26 Rambus Inc. Bit-replacement technique for dram error correction
US8356215B2 (en) * 2010-01-19 2013-01-15 Kingtiger Technology (Canada) Inc. Testing apparatus and method for analyzing a memory module operating within an application system
US9123552B2 (en) 2010-03-30 2015-09-01 Micron Technology, Inc. Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same
TWI398656B (zh) * 2010-03-31 2013-06-11 Rdc Semiconductor Co Ltd 用於驗證一中央處理器之裝置及其方法
JP5559616B2 (ja) * 2010-06-17 2014-07-23 ラピスセミコンダクタ株式会社 半導体メモリ装置
US8918686B2 (en) 2010-08-18 2014-12-23 Kingtiger Technology (Canada) Inc. Determining data valid windows in a system and method for testing an integrated circuit device
CN101950263A (zh) * 2010-09-27 2011-01-19 深圳市江波龙电子有限公司 一种存储设备的修复方法、系统及存储设备
CN102610280B (zh) * 2011-01-20 2015-05-27 北京兆易创新科技股份有限公司 修复存储芯片的方法和装置、存储芯片
CN102841832B (zh) * 2011-06-24 2017-05-24 佛山慧捷电子科技有限公司 出错内存条定位方法
US9003256B2 (en) 2011-09-06 2015-04-07 Kingtiger Technology (Canada) Inc. System and method for testing integrated circuits by determining the solid timing window
US8724408B2 (en) 2011-11-29 2014-05-13 Kingtiger Technology (Canada) Inc. Systems and methods for testing and assembling memory modules
US9298573B2 (en) 2012-03-30 2016-03-29 Intel Corporation Built-in self-test for stacked memory architecture
US9411678B1 (en) 2012-08-01 2016-08-09 Rambus Inc. DRAM retention monitoring method for dynamic error correction
US9117552B2 (en) 2012-08-28 2015-08-25 Kingtiger Technology(Canada), Inc. Systems and methods for testing memory
US9734921B2 (en) 2012-11-06 2017-08-15 Rambus Inc. Memory repair using external tags
TWI497511B (zh) * 2012-11-08 2015-08-21 Ind Tech Res Inst 具嵌入式非揮發性記憶體之晶片及其測試方法
US10042750B2 (en) 2013-03-15 2018-08-07 Micron Technology, Inc. Apparatuses and methods for adaptive control of memory using an adaptive memory controller with a memory management hypervisor
CN104063234B (zh) * 2013-03-19 2017-06-27 华为技术有限公司 一种兼容方法及装置
CN104750535B (zh) * 2013-12-26 2018-08-07 珠海全志科技股份有限公司 NAND Flash仿真控制器及控制调试方法
US10387259B2 (en) * 2015-06-26 2019-08-20 Intel Corporation Instant restart in non volatile system memory computing systems with embedded programmable data checking
US10387209B2 (en) * 2015-09-28 2019-08-20 International Business Machines Corporation Dynamic transparent provisioning of resources for application specific resources
US10725933B2 (en) * 2016-12-30 2020-07-28 Intel Corporation Method and apparatus for redirecting memory access commands sent to unusable memory partitions
CN108511029B (zh) * 2017-02-23 2022-04-05 上海复旦微电子集团股份有限公司 一种fpga中双端口sram阵列的内建自测和修复系统及其方法
US10713136B2 (en) * 2017-09-22 2020-07-14 Qualcomm Incorporated Memory repair enablement
US11087857B2 (en) * 2017-11-15 2021-08-10 Texas Instruments Incorporated Enabling high at-speed test coverage of functional memory interface logic by selective usage of test paths
TWI745997B (zh) * 2020-06-09 2021-11-11 慧榮科技股份有限公司 生產固態硬碟的方法及裝置以及電腦程式產品
CN113778915B (zh) 2020-06-09 2023-10-10 慧荣科技股份有限公司 生产固态硬盘的方法及计算机可读取存储介质及装置
CN112397135A (zh) * 2020-11-06 2021-02-23 润昇系统测试(深圳)有限公司 测试及修复装置以及测试及修复方法

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5450578A (en) * 1993-12-23 1995-09-12 Unisys Corporation Method and apparatus for automatically routing around faults within an interconnect system
US5875352A (en) 1995-11-03 1999-02-23 Sun Microsystems, Inc. Method and apparatus for multiple channel direct memory access control
US5818844A (en) 1996-06-06 1998-10-06 Advanced Micro Devices, Inc. Address generation and data path arbitration to and from SRAM to accommodate multiple transmitted packets
US6167486A (en) 1996-11-18 2000-12-26 Nec Electronics, Inc. Parallel access virtual channel memory system with cacheable channels
US7024518B2 (en) 1998-02-13 2006-04-04 Intel Corporation Dual-port buffer-to-memory interface
US6301637B1 (en) 1998-06-08 2001-10-09 Storage Technology Corporation High performance data paths
JP3178423B2 (ja) 1998-07-03 2001-06-18 日本電気株式会社 バーチャルチャネルsdram
US6272609B1 (en) 1998-07-31 2001-08-07 Micron Electronics, Inc. Pipelined memory controller
US6587912B2 (en) 1998-09-30 2003-07-01 Intel Corporation Method and apparatus for implementing multiple memory buses on a memory module
US6434639B1 (en) 1998-11-13 2002-08-13 Intel Corporation System for combining requests associated with one or more memory locations that are collectively associated with a single cache line to furnish a single memory operation
US6463059B1 (en) 1998-12-04 2002-10-08 Koninklijke Philips Electronics N.V. Direct memory access execution engine with indirect addressing of circular queues in addition to direct memory addressing
US6349363B2 (en) 1998-12-08 2002-02-19 Intel Corporation Multi-section cache with different attributes for each section
US6067262A (en) * 1998-12-11 2000-05-23 Lsi Logic Corporation Redundancy analysis for embedded memories with built-in self test and built-in self repair
US6496909B1 (en) 1999-04-06 2002-12-17 Silicon Graphics, Inc. Method for managing concurrent access to virtual memory data structures
US6359858B1 (en) * 1999-06-03 2002-03-19 Fujitsu Network Communications, Inc. Switching redundancy control
US6477592B1 (en) 1999-08-06 2002-11-05 Integrated Memory Logic, Inc. System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream
US6539490B1 (en) 1999-08-30 2003-03-25 Micron Technology, Inc. Clock distribution without clock delay or skew
US6552564B1 (en) 1999-08-30 2003-04-22 Micron Technology, Inc. Technique to reduce reflections and ringing on CMOS interconnections
US6594713B1 (en) 1999-09-10 2003-07-15 Texas Instruments Incorporated Hub interface unit and application unit interfaces for expanded direct memory access processor
US6421744B1 (en) 1999-10-25 2002-07-16 Motorola, Inc. Direct memory access controller and method therefor
JP3546788B2 (ja) 1999-12-20 2004-07-28 日本電気株式会社 メモリ制御回路
JP2002014875A (ja) * 2000-06-30 2002-01-18 Mitsubishi Electric Corp 半導体集積回路、半導体集積回路のメモリリペア方法およびその方法をコンピュータに実行させるプログラムを記録したコンピュータ読み取り可能な記録媒体
US6523093B1 (en) 2000-09-29 2003-02-18 Intel Corporation Prefetch buffer allocation and filtering system
US6523092B1 (en) 2000-09-29 2003-02-18 Intel Corporation Cache line replacement policy enhancement to avoid memory page thrashing
US6631440B2 (en) 2000-11-30 2003-10-07 Hewlett-Packard Development Company Method and apparatus for scheduling memory calibrations based on transactions
US6622227B2 (en) 2000-12-27 2003-09-16 Intel Corporation Method and apparatus for utilizing write buffers in memory control/interface
DE10110469A1 (de) * 2001-03-05 2002-09-26 Infineon Technologies Ag Integrierter Speicher und Verfahren zum Testen und Reparieren desselben
US6904499B2 (en) 2001-03-30 2005-06-07 Intel Corporation Controlling cache memory in external chipset using processor
US6920533B2 (en) 2001-06-27 2005-07-19 Intel Corporation System boot time reduction method
US7941056B2 (en) 2001-08-30 2011-05-10 Micron Technology, Inc. Optical interconnect in high-speed memory systems
US7133972B2 (en) 2002-06-07 2006-11-07 Micron Technology, Inc. Memory hub with internal cache and/or memory access prediction
JP2008000002A (ja) * 2004-09-30 2008-01-10 Sysmex Corp リブロース2リン酸カルボキシラーゼスモールチェーン1A(RBCS−1A)遺伝子及び/又は該遺伝子のmRNAを検出するための核酸増幅用プライマ、及び内部標準として該遺伝子及び/又は該遺伝子のmRNAを用いた検査方法。
JP5025113B2 (ja) * 2005-09-29 2012-09-12 三洋電機株式会社 回路装置
JP2007097002A (ja) * 2005-09-30 2007-04-12 Orion Denki Kk デジタル放送受信装置
JP2008002006A (ja) * 2006-06-21 2008-01-10 Toray Ind Inc 合成繊維の溶融紡糸装置

Also Published As

Publication number Publication date
AU2003258104A8 (en) 2004-03-03
EP1535131A4 (de) 2006-02-22
AU2003258104A1 (en) 2004-03-03
WO2004017162A2 (en) 2004-02-26
WO2004017162A3 (en) 2004-05-27
JP2005535978A (ja) 2005-11-24
CN100578656C (zh) 2010-01-06
EP1535131B1 (de) 2009-03-25
JP4431977B2 (ja) 2010-03-17
DE60326854D1 (de) 2009-05-07
TWI242780B (en) 2005-11-01
TW200414219A (en) 2004-08-01
KR100848254B1 (ko) 2008-07-25
US6754117B2 (en) 2004-06-22
US20040034825A1 (en) 2004-02-19
CN1703755A (zh) 2005-11-30
EP1535131A2 (de) 2005-06-01
KR20050061459A (ko) 2005-06-22

Similar Documents

Publication Publication Date Title
ATE426897T1 (de) System und verfahren zur selbstpr fung und reparatur von speichermodulen
ATE340386T1 (de) Verfahren und system zur automatischen prüfung von software
DE69710501D1 (de) System zur optimierung von speicherreparaturzeit mit prüfdaten
BR9802223A (pt) Base de dados para facilitar a instalação de software e testar um sistema de computador montado por encomenda
TW200632924A (en) Hub for testing memory and methods thereof
DE69604592D1 (de) Speicherprüfgerät zur schnellreparatur von halbleiterspeicherchips
ATE364227T1 (de) Verfahren und system zur optimierung der testkosten und deaktivierungsdefekte für scan- und bist-speicher
DE602005008560D1 (de) Dynamisches befehls- und/oder adressenspiegelungssystem und verfahren für speichermodule
TW200615753A (en) Hub, memory module, memory system and methods for reading and writing to the same
DE60021066D1 (de) Prüfung eines Softwarepakets
TW200625334A (en) Memory system, memory device, and output data strobe signal generating method
DE58909354D1 (de) Verfahren und Vorrichtung zum internen Paralleltest von Halbleiterspeichern.
TW200719140A (en) Automatic testing system and method
DE69504072T2 (de) Speicherprüfsystem
CN101923494A (zh) 一种存储器控制器验证系统、方法及记分板
ATE424582T1 (de) Verfahren und vorrichtung zum starten von leseoptimierungen in speicher-verbindungen
TW200612508A (en) Semiconductor test system
DE60233925D1 (de) Schaltung und Verfahren zur Verbesserung des Nutzungsgrades in einem Rasterpufferspeicher unter Verwendung von fehlerhaften Speicherstellen
TW200506404A (en) Method and apparatus for testing integrated circuits
ATE341788T1 (de) Speichersystem mit mehreren speichercontrollern and verfahren zu deren synchronisierung
ATE487188T1 (de) System und verfahren zur automatischen prüfung von planungsergebnissen
FR2785393B1 (fr) Appareil de test pour cartes a memoire electronique
ATE340382T1 (de) Verfahren und prüfeinrichtung zum entdecken von adressierungsfehlern in steuergeräten
DE69705734T2 (de) Verfahren und system zur sicherstellung, dass mit einem elektronischen gerät verbundene module von einem bestimmten typ sind, und ein modul und ein speichermedium dafür
DE60209201D1 (de) Verfahren zum Speichern von Registereigenschaften in einer Datenstruktur und dazugehörige Datenstruktur

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties