ATE415665T1 - Übertragen von daten zwischen unterschiedlich getakteten bussen - Google Patents
Übertragen von daten zwischen unterschiedlich getakteten bussenInfo
- Publication number
- ATE415665T1 ATE415665T1 AT03700180T AT03700180T ATE415665T1 AT E415665 T1 ATE415665 T1 AT E415665T1 AT 03700180 T AT03700180 T AT 03700180T AT 03700180 T AT03700180 T AT 03700180T AT E415665 T1 ATE415665 T1 AT E415665T1
- Authority
- AT
- Austria
- Prior art keywords
- data
- speed bus
- high speed
- predetermined
- transmitting data
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
- G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Information Transfer Systems (AREA)
- Dc Digital Transmission (AREA)
- Bus Control (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Detection And Correction Of Errors (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GBGB0204144.0A GB0204144D0 (en) | 2002-02-22 | 2002-02-22 | Transferring data between differently clocked busses |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE415665T1 true ATE415665T1 (de) | 2008-12-15 |
Family
ID=9931531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT03700180T ATE415665T1 (de) | 2002-02-22 | 2003-01-28 | Übertragen von daten zwischen unterschiedlich getakteten bussen |
Country Status (11)
| Country | Link |
|---|---|
| US (1) | US7165184B2 (de) |
| EP (1) | EP1478994B1 (de) |
| JP (2) | JP2005518042A (de) |
| KR (1) | KR100963706B1 (de) |
| CN (1) | CN100343778C (de) |
| AT (1) | ATE415665T1 (de) |
| AU (1) | AU2003201487A1 (de) |
| DE (1) | DE60324897D1 (de) |
| GB (1) | GB0204144D0 (de) |
| TW (1) | TWI291624B (de) |
| WO (1) | WO2003071405A1 (de) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005059765A1 (fr) * | 2003-12-18 | 2005-06-30 | Zte Corporation | Convertisseur a interface bus apte a convertir un protocole de bus amba ahb en protocole de bus de type i960 |
| KR101086401B1 (ko) * | 2004-06-02 | 2011-11-25 | 삼성전자주식회사 | 서로 다른 속도로 동작하는 버스들을 인터페이싱하는 방법및 장치 |
| US7600081B2 (en) * | 2006-01-18 | 2009-10-06 | Marvell World Trade Ltd. | Processor architecture having multi-ported memory |
| JP4882862B2 (ja) | 2007-05-11 | 2012-02-22 | ソニー株式会社 | 無線通信端末、半導体デバイス、データ通信方法および無線通信システム |
| US8250280B1 (en) | 2008-07-15 | 2012-08-21 | Marvell Israel (M.I.S.L.) Ltd. | Bus transaction maintenance protocol |
| IT1399916B1 (it) * | 2010-04-30 | 2013-05-09 | Balluchi | Dispositivo di memoria ad accesso di registro indicizzato |
| JP2012216985A (ja) * | 2011-03-31 | 2012-11-08 | Renesas Electronics Corp | データ転送システムおよびデータ転送方法 |
| US9489304B1 (en) * | 2011-11-14 | 2016-11-08 | Marvell International Ltd. | Bi-domain bridge enhanced systems and communication methods |
| CN103092175B (zh) * | 2013-01-21 | 2015-04-15 | 杭州华三通信技术有限公司 | I2c主设备与从设备之间串行时钟线scl控制的方法及装置 |
| GB2528481B (en) * | 2014-07-23 | 2016-08-17 | Ibm | Updating of shadow registers in N:1 clock domain |
| GB201810785D0 (en) | 2018-06-29 | 2018-08-15 | Nordic Semiconductor Asa | Asynchronous communication |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4716525A (en) * | 1985-04-15 | 1987-12-29 | Concurrent Computer Corporation | Peripheral controller for coupling data buses having different protocol and transfer rates |
| US5256912A (en) * | 1991-12-19 | 1993-10-26 | Sun Microsystems, Inc. | Synchronizer apparatus for system having at least two clock domains |
| JPH0713927A (ja) * | 1993-06-24 | 1995-01-17 | Fujitsu Ltd | 非同期同期変換回路 |
| RU2176814C2 (ru) * | 1995-06-07 | 2001-12-10 | Самсунг Электроникс Ко., Лтд. | Схема уменьшения задержки при передаче буферизованных данных между двумя взаимно асинхронными шинами |
| JP2993463B2 (ja) * | 1997-05-08 | 1999-12-20 | 日本電気株式会社 | 同期回路制御装置 |
| JPH11160100A (ja) | 1997-11-25 | 1999-06-18 | Sony Precision Technology Inc | スケール装置 |
| JP2000010850A (ja) * | 1998-06-19 | 2000-01-14 | Nec Eng Ltd | メモリアクセスシステム |
| US6064626A (en) * | 1998-07-31 | 2000-05-16 | Arm Limited | Peripheral buses for integrated circuit |
| JP2000076180A (ja) * | 1998-08-28 | 2000-03-14 | Nec Corp | バス接続装置及び情報処理システム |
| JP2000242544A (ja) * | 1999-02-25 | 2000-09-08 | Fuji Xerox Co Ltd | メモリ制御装置及びダイレクトメモリアクセス制御装置 |
| US6345328B1 (en) * | 1999-06-09 | 2002-02-05 | Advanced Micro Devices, Inc. | Gear box for multiple clock domains |
| US6549593B1 (en) * | 1999-07-19 | 2003-04-15 | Thomson Licensing S.A. | Interface apparatus for interfacing data to a plurality of different clock domains |
| US6408409B1 (en) * | 1999-11-15 | 2002-06-18 | Sun Microsystems, Inc. | Method and apparatus for ring buffer flow error detection |
| US6816979B1 (en) * | 2001-02-01 | 2004-11-09 | Cypress Semiconductor Corp. | Configurable fast clock detection logic with programmable resolution |
| US6928574B1 (en) * | 2001-08-23 | 2005-08-09 | Hewlett-Packard Development Company, L.P. | System and method for transferring data from a lower frequency clock domain to a higher frequency clock domain |
| US6931562B1 (en) * | 2001-08-23 | 2005-08-16 | Hewlett-Packard Development Company, L.P. | System and method for transferring data from a higher frequency clock domain to a lower frequency clock domain |
| US7010713B2 (en) * | 2002-12-19 | 2006-03-07 | Mosaid Technologies, Inc. | Synchronization circuit and method with transparent latches |
| US6949955B2 (en) * | 2003-11-24 | 2005-09-27 | Intel Corporation | Synchronizing signals between clock domains |
| US7061286B2 (en) * | 2004-06-24 | 2006-06-13 | Teradyne, Inc. | Synchronization between low frequency and high frequency digital signals |
-
2002
- 2002-02-22 GB GBGB0204144.0A patent/GB0204144D0/en not_active Ceased
-
2003
- 2003-01-28 KR KR1020047012965A patent/KR100963706B1/ko not_active Expired - Fee Related
- 2003-01-28 AT AT03700180T patent/ATE415665T1/de not_active IP Right Cessation
- 2003-01-28 EP EP03700180A patent/EP1478994B1/de not_active Expired - Lifetime
- 2003-01-28 US US10/504,759 patent/US7165184B2/en not_active Expired - Lifetime
- 2003-01-28 AU AU2003201487A patent/AU2003201487A1/en not_active Abandoned
- 2003-01-28 DE DE60324897T patent/DE60324897D1/de not_active Expired - Lifetime
- 2003-01-28 WO PCT/IB2003/000246 patent/WO2003071405A1/en not_active Ceased
- 2003-01-28 CN CNB038044374A patent/CN100343778C/zh not_active Expired - Fee Related
- 2003-01-28 JP JP2003570232A patent/JP2005518042A/ja active Pending
- 2003-02-19 TW TW092103410A patent/TWI291624B/zh not_active IP Right Cessation
-
2009
- 2009-03-09 JP JP2009055004A patent/JP2009163758A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| EP1478994A1 (de) | 2004-11-24 |
| JP2005518042A (ja) | 2005-06-16 |
| GB0204144D0 (en) | 2002-04-10 |
| KR100963706B1 (ko) | 2010-06-14 |
| DE60324897D1 (de) | 2009-01-08 |
| CN100343778C (zh) | 2007-10-17 |
| AU2003201487A1 (en) | 2003-09-09 |
| JP2009163758A (ja) | 2009-07-23 |
| US7165184B2 (en) | 2007-01-16 |
| EP1478994B1 (de) | 2008-11-26 |
| WO2003071405A1 (en) | 2003-08-28 |
| CN1639670A (zh) | 2005-07-13 |
| TWI291624B (en) | 2007-12-21 |
| US20050108482A1 (en) | 2005-05-19 |
| KR20040085209A (ko) | 2004-10-07 |
| TW200303472A (en) | 2003-09-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7134035B2 (en) | Method for generating a synchronization signal based on the clock ratio between two clock domains for data transfer between the domains | |
| US9753486B2 (en) | Clock gating with an asynchronous wrapper cell | |
| US4873703A (en) | Synchronizing system | |
| EP0977109A1 (de) | Verfahren und Vorrichtung zur Synchronisierung von Datenübertragungen in einer Logikschaltung mit mehreren Taktbereichen | |
| ATE415665T1 (de) | Übertragen von daten zwischen unterschiedlich getakteten bussen | |
| US8386828B1 (en) | Circuit for estimating latency through a FIFO buffer | |
| JPH03237832A (ja) | データ・クロックのタイミング合わせ回路 | |
| EP1298667A3 (de) | Halbleiterspeicheranordnung | |
| JPH07253947A (ja) | データ通信装置 | |
| US20060140317A1 (en) | Clock synchronization circuit | |
| CN101063894B (zh) | 动态同步化处理器时钟与总线时钟前缘的方法与系统 | |
| EP0940758A3 (de) | Serielle Busbeschleunigungsschaltung | |
| CN104850524A (zh) | 一种跨时钟域的ahb总线桥接方法和装置 | |
| US7500132B1 (en) | Method of asynchronously transmitting data between clock domains | |
| US20090271651A1 (en) | Method and System for Reducing Latency in Data Transfer Between Asynchronous Clock Domains | |
| WO2001095551A3 (en) | Method and device for synchronization of phase mismatch in communication systems employing a common clock period | |
| TW255079B (en) | Communications unit with data and clock recovery circuit | |
| WO2001089193A3 (en) | Video signal processing system for driving multiple monitors | |
| CN113491082A (zh) | 一种数据处理装置 | |
| CN105988959B (zh) | 一种异步数据传输方法及系统 | |
| US20080247496A1 (en) | Early HSS Rx Data Sampling | |
| AU6272299A (en) | Regulating a data transfer time | |
| ATE317567T1 (de) | Digitales bussystem | |
| US6031396A (en) | Circuit for synchronizing asynchronous inputs using dual edge logic design | |
| CN102916681B (zh) | 一种脉宽可调的nrz/rz码转换装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |