ATE387652T1 - Taktverteilung in integrierten schaltungen - Google Patents

Taktverteilung in integrierten schaltungen

Info

Publication number
ATE387652T1
ATE387652T1 AT04801333T AT04801333T ATE387652T1 AT E387652 T1 ATE387652 T1 AT E387652T1 AT 04801333 T AT04801333 T AT 04801333T AT 04801333 T AT04801333 T AT 04801333T AT E387652 T1 ATE387652 T1 AT E387652T1
Authority
AT
Austria
Prior art keywords
block
integrated circuits
clock distribution
local clock
circuit
Prior art date
Application number
AT04801333T
Other languages
English (en)
Inventor
Sylvain Duvillard
Isabelle Delbaere
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE387652T1 publication Critical patent/ATE387652T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AT04801333T 2003-12-19 2004-12-06 Taktverteilung in integrierten schaltungen ATE387652T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03300273 2003-12-19

Publications (1)

Publication Number Publication Date
ATE387652T1 true ATE387652T1 (de) 2008-03-15

Family

ID=34717267

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04801333T ATE387652T1 (de) 2003-12-19 2004-12-06 Taktverteilung in integrierten schaltungen

Country Status (7)

Country Link
US (1) US7474137B2 (de)
EP (1) EP1697821B1 (de)
JP (1) JP2007519097A (de)
CN (1) CN100421048C (de)
AT (1) ATE387652T1 (de)
DE (1) DE602004012156T2 (de)
WO (1) WO2005064434A1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080157977A1 (en) * 2006-07-10 2008-07-03 Toshiba Tec Kabushiki Kaisha Wireless tag reader/writer, communication method thereof, and wireless tag relating to the communication method
KR101437848B1 (ko) * 2008-09-29 2014-09-04 삼성전자주식회사 이동통신 시스템의 시스템 클럭 동기 장치 및 방법
CN105138735B (zh) * 2015-07-30 2018-05-25 中山大学 一种多宏单元多时钟芯片的时钟树综合方法
US10325046B2 (en) * 2016-09-20 2019-06-18 Synopsys, Inc. Formal method for clock tree analysis and optimization

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2719226B2 (ja) * 1990-10-01 1998-02-25 株式会社日立製作所 情報処理システム
JPH04192715A (ja) * 1990-11-26 1992-07-10 Olympus Optical Co Ltd ディジタル回路
US5481573A (en) * 1992-06-26 1996-01-02 International Business Machines Corporation Synchronous clock distribution system
KR100293596B1 (ko) * 1993-01-27 2001-09-17 가나이 쓰도무 Lsi내클럭분배회로
US5528638A (en) * 1995-05-24 1996-06-18 Sun Microsystems, Inc. Multiple phase shifted clocks generation using a minimal set of signals from a PLL
JP2735097B2 (ja) * 1995-07-20 1998-04-02 日本電気株式会社 半導体集積回路
SE505022C2 (sv) * 1995-08-08 1997-06-16 Saab Dynamics Ab Metod och anordning för distribution och synkronisering av klocksignaler i ett digitalt system
US5565816A (en) * 1995-08-18 1996-10-15 International Business Machines Corporation Clock distribution network
US6157237A (en) * 1996-05-01 2000-12-05 Sun Microsystems, Inc. Reduced skew control block clock distribution network
JP2959482B2 (ja) * 1996-08-19 1999-10-06 日本電気株式会社 大規模集積回路
US6125157A (en) * 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
JPH11161364A (ja) * 1997-11-25 1999-06-18 Mitsubishi Electric Corp 半導体回路装置
US6208702B1 (en) * 1998-01-23 2001-03-27 International Business Machines Corporation High frequency clock signal distribution utilizing CMOS negative impedance terminations
JPH11298459A (ja) * 1998-04-15 1999-10-29 Hitachi Ltd 高速伝送方式及び高速伝送装置
JP2001053233A (ja) * 1999-08-06 2001-02-23 Hitachi Ltd 半導体集積回路及び記憶媒体
JP3620440B2 (ja) * 2000-11-20 2005-02-16 日本電気株式会社 半導体集積回路とそのクロック分配方法
JP2002312058A (ja) * 2001-04-11 2002-10-25 Mitsubishi Electric Corp 半導体集積回路
US6538957B2 (en) * 2001-05-14 2003-03-25 Sony Computer Entertainment America Inc. Apparatus and method for distributing a clock signal on a large scale integrated circuit
US6686785B2 (en) * 2001-10-11 2004-02-03 Sun Microsystems, Inc. Deskewing global clock skew using localized DLLs
JP2003234643A (ja) * 2002-02-07 2003-08-22 Mitsubishi Electric Corp 半導体集積回路装置の設計方法および半導体集積回路装置

Also Published As

Publication number Publication date
WO2005064434A1 (en) 2005-07-14
EP1697821A1 (de) 2006-09-06
DE602004012156T2 (de) 2009-03-19
CN100421048C (zh) 2008-09-24
CN1898626A (zh) 2007-01-17
US7474137B2 (en) 2009-01-06
US20070194829A1 (en) 2007-08-23
DE602004012156D1 (de) 2008-04-10
EP1697821B1 (de) 2008-02-27
JP2007519097A (ja) 2007-07-12

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Legal Events

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