DE60217408D1 - Informationsaustausch zwischen lokal synchronen schaltungen - Google Patents

Informationsaustausch zwischen lokal synchronen schaltungen

Info

Publication number
DE60217408D1
DE60217408D1 DE60217408T DE60217408T DE60217408D1 DE 60217408 D1 DE60217408 D1 DE 60217408D1 DE 60217408 T DE60217408 T DE 60217408T DE 60217408 T DE60217408 T DE 60217408T DE 60217408 D1 DE60217408 D1 DE 60217408D1
Authority
DE
Germany
Prior art keywords
circuit
handshake
clock
delay
information exchange
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60217408T
Other languages
English (en)
Other versions
DE60217408T2 (de
Inventor
L Kessels
M Peeters
Paul Wielage
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Application granted granted Critical
Publication of DE60217408D1 publication Critical patent/DE60217408D1/de
Publication of DE60217408T2 publication Critical patent/DE60217408T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Mobile Radio Communication Systems (AREA)
DE60217408T 2002-01-02 2002-12-06 Informationsaustausch zwischen lokal synchronen schaltungen Expired - Lifetime DE60217408T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP02075578 2002-01-02
EP02075578 2002-01-02
PCT/IB2002/005204 WO2003060727A2 (en) 2002-01-02 2002-12-06 Information exchange between locally synchronous circuits

Publications (2)

Publication Number Publication Date
DE60217408D1 true DE60217408D1 (de) 2007-02-15
DE60217408T2 DE60217408T2 (de) 2007-10-04

Family

ID=8185592

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60217408T Expired - Lifetime DE60217408T2 (de) 2002-01-02 2002-12-06 Informationsaustausch zwischen lokal synchronen schaltungen

Country Status (9)

Country Link
US (1) US7185220B2 (de)
EP (1) EP1464001B1 (de)
JP (1) JP4404637B2 (de)
KR (1) KR100956304B1 (de)
CN (1) CN100507891C (de)
AT (1) ATE350712T1 (de)
AU (1) AU2002367038A1 (de)
DE (1) DE60217408T2 (de)
WO (1) WO2003060727A2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7089443B2 (en) * 2003-01-23 2006-08-08 University Of Rochester Multiple clock domain microprocessor
DE10303673A1 (de) * 2003-01-24 2004-08-12 IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik Asynchrone Hüllschaltung für eine global asynchrone, lokal synchrone (GALS) Schaltung
JP2008535305A (ja) * 2005-03-22 2008-08-28 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 非同期遅延を実現する電子回路
JP2007164286A (ja) * 2005-12-09 2007-06-28 Sony Corp 情報信号処理装置、機能ブロックおよび機能ブロックの制御方法
US7856516B2 (en) 2006-10-27 2010-12-21 Kyocera Mita Corporation Interfacing incompatible signaling using generic I/O and interrupt routines
WO2009147566A1 (en) * 2008-06-02 2009-12-10 Koninklijke Philips Electronics N.V. Asynchronous communication
US8189723B2 (en) * 2008-08-15 2012-05-29 International Business Machines Corporation Method, circuit, and design structure for capturing data across a pseudo-synchronous interface
US8300752B2 (en) * 2008-08-15 2012-10-30 International Business Machines Corporation Method, circuit, and design structure for capturing data across a pseudo-synchronous interface
CN101377691B (zh) * 2008-09-05 2012-01-11 无锡中星微电子有限公司 一种apb总线跨时钟域访问的电路及方法
US8625714B2 (en) * 2011-05-12 2014-01-07 St-Ericsson Sa Time delay estimation
US10505704B1 (en) * 2015-08-02 2019-12-10 Wave Computing, Inc. Data uploading to asynchronous circuitry using circular buffer control
GB2580165B (en) * 2018-12-21 2021-02-24 Graphcore Ltd Data exchange in a computer with predetermined delay
CN114024893A (zh) * 2021-11-18 2022-02-08 群联电子股份有限公司 时钟重整电路模块、信号传输系统及信号传输方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3560793B2 (ja) * 1997-11-27 2004-09-02 株式会社東芝 データ転送方法
US7065665B2 (en) * 2002-10-02 2006-06-20 International Business Machines Corporation Interlocked synchronous pipeline clock gating

Also Published As

Publication number Publication date
DE60217408T2 (de) 2007-10-04
JP2005515544A (ja) 2005-05-26
WO2003060727A2 (en) 2003-07-24
JP4404637B2 (ja) 2010-01-27
US20050141257A1 (en) 2005-06-30
US7185220B2 (en) 2007-02-27
EP1464001A2 (de) 2004-10-06
KR100956304B1 (ko) 2010-05-10
ATE350712T1 (de) 2007-01-15
AU2002367038A1 (en) 2003-07-30
EP1464001B1 (de) 2007-01-03
KR20040073538A (ko) 2004-08-19
CN100507891C (zh) 2009-07-01
CN1666186A (zh) 2005-09-07
AU2002367038A8 (en) 2003-07-30
WO2003060727A3 (en) 2004-03-11

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Legal Events

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8320 Willingness to grant licences declared (paragraph 23)
8364 No opposition during term of opposition