DE60134835D1 - Verfahren und Schaltungsanordung zur Datenübertragung zwischen pseudo-synchronisierten Kanälen - Google Patents

Verfahren und Schaltungsanordung zur Datenübertragung zwischen pseudo-synchronisierten Kanälen

Info

Publication number
DE60134835D1
DE60134835D1 DE60134835T DE60134835T DE60134835D1 DE 60134835 D1 DE60134835 D1 DE 60134835D1 DE 60134835 T DE60134835 T DE 60134835T DE 60134835 T DE60134835 T DE 60134835T DE 60134835 D1 DE60134835 D1 DE 60134835D1
Authority
DE
Germany
Prior art keywords
phase
signals
output clock
pseudo
pll circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60134835T
Other languages
English (en)
Inventor
Kevin W Locker
Joseph Murray
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell International Inc
Original Assignee
Honeywell International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell International Inc filed Critical Honeywell International Inc
Application granted granted Critical
Publication of DE60134835D1 publication Critical patent/DE60134835D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
DE60134835T 2000-01-10 2001-01-09 Verfahren und Schaltungsanordung zur Datenübertragung zwischen pseudo-synchronisierten Kanälen Expired - Fee Related DE60134835D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/479,974 US6297702B1 (en) 2000-01-10 2000-01-10 Phase lock loop system and method
PCT/US2001/000701 WO2001052417A2 (en) 2000-01-10 2001-01-09 Phase lock loop system and method

Publications (1)

Publication Number Publication Date
DE60134835D1 true DE60134835D1 (de) 2008-08-28

Family

ID=23906171

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60134835T Expired - Fee Related DE60134835D1 (de) 2000-01-10 2001-01-09 Verfahren und Schaltungsanordung zur Datenübertragung zwischen pseudo-synchronisierten Kanälen

Country Status (5)

Country Link
US (2) US6297702B1 (de)
EP (1) EP1262022B1 (de)
AT (1) ATE401701T1 (de)
DE (1) DE60134835D1 (de)
WO (1) WO2001052417A2 (de)

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US6704892B1 (en) * 2000-05-31 2004-03-09 Intel Corporation Automated clock alignment for testing processors in a bypass mode
US6538516B2 (en) * 2001-05-17 2003-03-25 Fairchild Semiconductor Corporation System and method for synchronizing multiple phase-lock loops or other synchronizable oscillators without using a master clock signal
DE10148878B4 (de) * 2001-10-04 2006-03-02 Siemens Ag System und Verfahren zum Übertragen digitaler Daten
US7164734B2 (en) * 2001-12-04 2007-01-16 Northrop Grumman Corporation Decision directed phase locked loops (DD-PLL) with excess processing power in digital communication systems
US7426220B2 (en) * 2002-01-09 2008-09-16 L-3 Communications Corporation Method and apparatus for aligning the clock signals of transceivers in a multiple access communication system utilizing programmable, multi-tap phase-locked loops
US7120203B2 (en) * 2002-02-12 2006-10-10 Broadcom Corporation Dual link DVI transmitter serviced by single Phase Locked Loop
US7256628B2 (en) * 2003-01-29 2007-08-14 Sun Microsystems, Inc. Speed-matching control method and circuit
US7623482B2 (en) * 2003-05-10 2009-11-24 Hewlett-Packard Development Company, L.P. System and method for effectuating the transfer of data blocks including a header block across a clock boundary
DE10331092B4 (de) * 2003-07-09 2007-10-31 Rohde & Schwarz Gmbh & Co. Kg Anordnung zur Phasensynchronisation von mehreren zu einem Meßsystem zusammengefaßten elektronischen Meßgeräten
US7499684B2 (en) * 2003-09-19 2009-03-03 Ipr Licensing, Inc. Master-slave local oscillator porting between radio integrated circuits
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7788451B2 (en) 2004-02-05 2010-08-31 Micron Technology, Inc. Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
US7257683B2 (en) 2004-03-24 2007-08-14 Micron Technology, Inc. Memory arbitration system and method having an arbitration packet protocol
US6980042B2 (en) * 2004-04-05 2005-12-27 Micron Technology, Inc. Delay line synchronizer apparatus and method
US7574185B2 (en) * 2004-12-17 2009-08-11 Verigy (Singapore) Pte. Ltd. Method and apparatus for generating a phase-locked output signal
US7346793B2 (en) * 2005-02-10 2008-03-18 Northrop Grumman Corporation Synchronization of multiple operational flight programs
US7581131B1 (en) * 2005-05-09 2009-08-25 National Semiconductor Corporation Method and system for balancing clock trees in a multi-voltage synchronous digital environment
US7512201B2 (en) * 2005-06-14 2009-03-31 International Business Machines Corporation Multi-channel synchronization architecture
US7627065B2 (en) * 2005-12-21 2009-12-01 Sun Microsystems, Inc. Generating a clock crossing signal based on clock ratios
DE102006011682B4 (de) * 2006-03-14 2015-04-09 Intel Mobile Communications GmbH Transceiver-Schaltungsanordnung
US7751274B2 (en) * 2006-09-05 2010-07-06 Intel Corporation Extended synchronized clock
US7768325B2 (en) * 2008-04-23 2010-08-03 International Business Machines Corporation Circuit and design structure for synchronizing multiple digital signals
JP5663881B2 (ja) * 2010-01-18 2015-02-04 富士通株式会社 クロック装置
CA2699596A1 (fr) 2010-03-24 2011-09-24 Hydro-Quebec Systeme et methode de synchronisation de phase de signaux produits par des unites de mesure respectives
US8633749B2 (en) * 2012-05-09 2014-01-21 Aeroflex Colorado Springs Inc. Phase-locked loop (PLL) fail-over circuit technique and method to mitigate effects of single-event transients
US8907707B2 (en) * 2013-03-01 2014-12-09 Laurence H. Cooke Aligning multiple chip input signals using digital phase lock loops
US8593191B1 (en) * 2013-03-01 2013-11-26 Laurence H. Cooke Aligning multiple chip input signals using digital phase lock loops
US10924122B2 (en) * 2016-06-22 2021-02-16 Telefonaktiebolaget Lm Ericsson (Publ) Method and system for phase alignment of multiple phased locked loops
US10256828B2 (en) 2016-11-29 2019-04-09 Taiwan Semiconductor Manufacturing Co., Ltd. Phase-locked loop monitor circuit
EP3839695A1 (de) 2019-12-19 2021-06-23 Microsoft Technology Licensing, LLC Verfahren und vorrichtung zur synchronisierung von zwei systemen
US11588488B1 (en) 2021-12-09 2023-02-21 Raytheon Company Dual-loop phase-locking circuit

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Publication number Priority date Publication date Assignee Title
DE2907608A1 (de) * 1979-02-27 1980-08-28 Siemens Ag Schaltungsanordnung zur takterzeugung in fernmeldeanlagen, insbesondere zeitmultiplex-digital-vermittlungsanlagen
US4692715A (en) * 1986-03-03 1987-09-08 Spence Lewis C Constant frequency signal generator circuit and method
EP0379279A3 (de) * 1989-01-17 1991-09-11 Marconi Instruments Limited Datenvermittlungssynchronisator
DE3924907A1 (de) * 1989-07-27 1991-01-31 Siemens Ag Redundante taktgeberanordnung
JPH0556085A (ja) * 1991-08-23 1993-03-05 Nec Ic Microcomput Syst Ltd インターフエイス回路
US5256912A (en) * 1991-12-19 1993-10-26 Sun Microsystems, Inc. Synchronizer apparatus for system having at least two clock domains
US5726607A (en) * 1992-06-15 1998-03-10 Adc Telecommunications, Inc. Phase locked loop using a counter and a microcontroller to produce VCXO control signals
US5987083A (en) * 1995-01-31 1999-11-16 Advantest Corporation Signal transmission apparatus with a plurality of LSIS
US5787265A (en) * 1995-09-28 1998-07-28 Emc Corporation Bus arbitration system having a pair of logic networks to control data transfer between a memory and a pair of buses
US5799048A (en) * 1996-04-17 1998-08-25 Sun Microsystems, Inc. Phase detector for clock synchronization and recovery
US5748569A (en) * 1996-12-19 1998-05-05 Dsc Telecom L.P. Apparatus and method for clock alignment and switching
KR100255664B1 (ko) * 1997-12-29 2000-05-01 윤종용 반도체 집적회로의 클락 포워딩 회로 및 클락포워딩 방법

Also Published As

Publication number Publication date
US20010043098A1 (en) 2001-11-22
WO2001052417A3 (en) 2002-03-07
WO2001052417A2 (en) 2001-07-19
EP1262022B1 (de) 2008-07-16
EP1262022A2 (de) 2002-12-04
ATE401701T1 (de) 2008-08-15
US6577174B2 (en) 2003-06-10
US6297702B1 (en) 2001-10-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee