DE60228909D1 - Netzwerkschnittstelle mit programmierbarer Verzögerung und Frequenzverdoppler - Google Patents

Netzwerkschnittstelle mit programmierbarer Verzögerung und Frequenzverdoppler

Info

Publication number
DE60228909D1
DE60228909D1 DE60228909T DE60228909T DE60228909D1 DE 60228909 D1 DE60228909 D1 DE 60228909D1 DE 60228909 T DE60228909 T DE 60228909T DE 60228909 T DE60228909 T DE 60228909T DE 60228909 D1 DE60228909 D1 DE 60228909D1
Authority
DE
Germany
Prior art keywords
ports
frequency doubler
signal
network interface
programmable delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60228909T
Other languages
English (en)
Inventor
Jonathan Mr Lin
Jong Jiang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of DE60228909D1 publication Critical patent/DE60228909D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0697—Synchronisation in a packet node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0091—Transmitter details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Information Transfer Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Logic Circuits (AREA)
  • Small-Scale Networks (AREA)
DE60228909T 2001-03-16 2002-03-18 Netzwerkschnittstelle mit programmierbarer Verzögerung und Frequenzverdoppler Expired - Lifetime DE60228909D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US27603401P 2001-03-16 2001-03-16

Publications (1)

Publication Number Publication Date
DE60228909D1 true DE60228909D1 (de) 2008-10-30

Family

ID=23054866

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60228909T Expired - Lifetime DE60228909D1 (de) 2001-03-16 2002-03-18 Netzwerkschnittstelle mit programmierbarer Verzögerung und Frequenzverdoppler

Country Status (4)

Country Link
US (2) US6934866B2 (de)
EP (2) EP1267525A2 (de)
AT (1) ATE408945T1 (de)
DE (1) DE60228909D1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7382736B2 (en) 1999-01-12 2008-06-03 Mcdata Corporation Method for scoring queued frames for selective transmission through a switch
US6920552B2 (en) 2001-03-16 2005-07-19 Broadcom Corporation Network interface with double data rate and delay locked loop
US7447198B1 (en) * 2001-04-23 2008-11-04 Brocade Communications Systems, Inc. Link trunking and measuring link latency in fibre channel fabric
KR100464034B1 (ko) * 2002-07-19 2005-01-03 엘지전자 주식회사 클록 동기화 방법
US7600035B2 (en) 2003-01-31 2009-10-06 Brocade Communications Systems, Inc. Dynamic link distance configuration for extended fabric
US7486702B1 (en) * 2003-08-11 2009-02-03 Cisco Technology, Inc DDR interface for reducing SSO/SSI noise
US7593336B2 (en) 2003-10-31 2009-09-22 Brocade Communications Systems, Inc. Logical ports in trunking
US7619974B2 (en) 2003-10-31 2009-11-17 Brocade Communication Systems, Inc. Frame traffic balancing across trunk groups
US7356047B1 (en) * 2004-04-24 2008-04-08 Cisco Technology, Inc. 10/100/1000/2500 Mbps serial media independent interface (SGMII)
JP2006242449A (ja) * 2005-03-02 2006-09-14 Sanden Corp ショーケース
US8223633B2 (en) * 2008-10-03 2012-07-17 Brocade Communications Systems, Inc. Port trunking at a fabric boundary
US8412831B2 (en) * 2009-08-03 2013-04-02 Brocade Communications Systems, Inc. Per priority TCP quality of service

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3917714A1 (de) * 1989-05-31 1990-12-06 Siemens Ag Multiplizierschaltung
US5487095A (en) * 1994-06-17 1996-01-23 International Business Machines Corporation Edge detector
US5923621A (en) * 1995-06-07 1999-07-13 Cirrus Logic, Inc. Clock doubler circuit with duty cycle control
US6385710B1 (en) * 1996-02-23 2002-05-07 Sun Microsystems, Inc. Multiple-mode external cache subsystem
US5919265A (en) * 1996-05-28 1999-07-06 Sun Microsystems, Inc. Source synchronization data transfers without resynchronization penalty
US5930689A (en) * 1997-10-24 1999-07-27 Motorola, Inc. Apparatus and method for producing a plurality of output signals with fixed phase relationships therebetween
JP3769940B2 (ja) * 1998-08-06 2006-04-26 株式会社日立製作所 半導体装置
JP3667196B2 (ja) * 2000-05-26 2005-07-06 Ｎｅｃエレクトロニクス株式会社 タイミング差分割回路
JP3807593B2 (ja) * 2000-07-24 2006-08-09 株式会社ルネサステクノロジ クロック生成回路および制御方法並びに半導体記憶装置

Also Published As

Publication number Publication date
ATE408945T1 (de) 2008-10-15
US6934866B2 (en) 2005-08-23
US7024576B2 (en) 2006-04-04
EP1249971A3 (de) 2005-09-21
EP1249971B1 (de) 2008-09-17
EP1267525A2 (de) 2002-12-18
US20050268138A1 (en) 2005-12-01
US20020131456A1 (en) 2002-09-19
EP1249971A2 (de) 2002-10-16

Similar Documents

Publication Publication Date Title
DE60228909D1 (de) Netzwerkschnittstelle mit programmierbarer Verzögerung und Frequenzverdoppler
AU2002233528A1 (en) Synchronous to asynchronous to synchronous interface
DE60134835D1 (de) Verfahren und Schaltungsanordung zur Datenübertragung zwischen pseudo-synchronisierten Kanälen
TW200505140A (en) Low-to-high level shift circuit
TW200605512A (en) Circuit for applying jitter and test
BRPI0409327A (pt) dispositivo para gerar um sinal de áudio de saìda com base em um sinal de aúdio de entrada, método para prover um sinal de áudio de saìda com base em um sinal de áudio de entrada e aparelho para fornecer um sinal de áudio de saìda
BR0009251B1 (pt) aparelho de interface dinÂmica canalizada em onda e mÉtodo para o mesmo.
DE60141613D1 (de) Konfigurierbarer Modulator
WO2004059471A3 (en) Clock skew compensation apparatus and method
AU2001268304A1 (en) Method and apparatus for adjusting the phase of input/output circuitry
TW200625811A (en) Clock buffering devices including master-slave terminal transmission gates and methods of operating same
AU2003233131A1 (en) Electronic circuit with asynchronously operating components
WO2005050842A3 (en) Apparatus and method for generating a delayed clock signal
GB2462239A (en) Techniques for integrated circuit clock management
ATE279751T1 (de) Elektronische schaltung mit asynchroner taktung von peripherieeinheiten
TW200518021A (en) Apparatus and method for processing signals
WO2003038687A3 (en) Optimization of the design of a synchronous digital circuit
TW200514991A (en) Method and apparatus for testing a bridge circuit
ATE534207T1 (de) Verzögerungsregelkreis und -verfahren
TW200615737A (en) Apparatus and method for generating a clock signal
WO2003030362A3 (de) Multiplexerzelle und multiplexer-schaltungsanordnung und codiervorrichtung zum einsatz in einer derartigen multiplexer-schaltungsanordnung
WO2001086397A3 (en) Apparatus for a radiation hardened clock splitter
AU2003233331A1 (en) Random signal generator
JPS63181515A (ja) 遅延時間自動調整方式
WO2002084462A3 (en) Voltage multiplier for low voltage microprocessor

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: BOSCH JEHLE PATENTANWALTSGESELLSCHAFT MBH, 80639 M