ATE387652T1 - CLOCK DISTRIBUTION IN INTEGRATED CIRCUITS - Google Patents

CLOCK DISTRIBUTION IN INTEGRATED CIRCUITS

Info

Publication number
ATE387652T1
ATE387652T1 AT04801333T AT04801333T ATE387652T1 AT E387652 T1 ATE387652 T1 AT E387652T1 AT 04801333 T AT04801333 T AT 04801333T AT 04801333 T AT04801333 T AT 04801333T AT E387652 T1 ATE387652 T1 AT E387652T1
Authority
AT
Austria
Prior art keywords
block
integrated circuits
clock distribution
local clock
circuit
Prior art date
Application number
AT04801333T
Other languages
German (de)
Inventor
Sylvain Duvillard
Isabelle Delbaere
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE387652T1 publication Critical patent/ATE387652T1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10Distribution of clock signals, e.g. skew
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06Clock generators producing several clock signals

Abstract

A circuit is provided with a plurality of interconnected logic blocks, a main clock generator for distributing a reference clock signal to the logic blocks. Each logic block in the circuit comprises a local clock generator that generates a set of synchronized local clock signals from the reference clock signal for further provision to respective elements of the logic block. In such a circuit, a phase shift is introduced between a set of local clock signals of a first block and a set of local clock signals of a second block.
AT04801333T 2003-12-19 2004-12-06 CLOCK DISTRIBUTION IN INTEGRATED CIRCUITS ATE387652T1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03300273 2003-12-19

Publications (1)

Publication Number Publication Date
ATE387652T1 true ATE387652T1 (en) 2008-03-15

Family

ID=34717267

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04801333T ATE387652T1 (en) 2003-12-19 2004-12-06 CLOCK DISTRIBUTION IN INTEGRATED CIRCUITS

Country Status (7)

Country Link
US (1) US7474137B2 (en)
EP (1) EP1697821B1 (en)
JP (1) JP2007519097A (en)
CN (1) CN100421048C (en)
AT (1) ATE387652T1 (en)
DE (1) DE602004012156T2 (en)
WO (1) WO2005064434A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080157977A1 (en) * 2006-07-10 2008-07-03 Toshiba Tec Kabushiki Kaisha Wireless tag reader/writer, communication method thereof, and wireless tag relating to the communication method
KR101437848B1 (en) * 2008-09-29 2014-09-04 삼성전자주식회사 Apparatus and method for synchronization system clock of mobile communication system
CN105138735B (en) * 2015-07-30 2018-05-25 中山大学 A kind of clock tree synthesis method of more macroelement multi-clock chips
US10325046B2 (en) * 2016-09-20 2019-06-18 Synopsys, Inc. Formal method for clock tree analysis and optimization

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2719226B2 (en) * 1990-10-01 1998-02-25 株式会社日立製作所 Information processing system
JPH04192715A (en) * 1990-11-26 1992-07-10 Olympus Optical Co Ltd Digital circuit
US5481573A (en) * 1992-06-26 1996-01-02 International Business Machines Corporation Synchronous clock distribution system
US5430397A (en) * 1993-01-27 1995-07-04 Hitachi, Ltd. Intra-LSI clock distribution circuit
US5528638A (en) * 1995-05-24 1996-06-18 Sun Microsystems, Inc. Multiple phase shifted clocks generation using a minimal set of signals from a PLL
JP2735097B2 (en) * 1995-07-20 1998-04-02 日本電気株式会社 Semiconductor integrated circuit
SE505022C2 (en) * 1995-08-08 1997-06-16 Saab Dynamics Ab Method and apparatus for distribution and synchronization of clock signals in a digital system
US5565816A (en) * 1995-08-18 1996-10-15 International Business Machines Corporation Clock distribution network
US6157237A (en) * 1996-05-01 2000-12-05 Sun Microsystems, Inc. Reduced skew control block clock distribution network
JP2959482B2 (en) * 1996-08-19 1999-10-06 日本電気株式会社 Large-scale integrated circuits
US6125157A (en) * 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
JPH11161364A (en) * 1997-11-25 1999-06-18 Mitsubishi Electric Corp Semiconductor circuit device
US6208702B1 (en) * 1998-01-23 2001-03-27 International Business Machines Corporation High frequency clock signal distribution utilizing CMOS negative impedance terminations
JPH11298459A (en) * 1998-04-15 1999-10-29 Hitachi Ltd High speed transmission system and high speed transmitter
JP2001053233A (en) * 1999-08-06 2001-02-23 Hitachi Ltd Semiconductor integrated circuit and storage medium
JP3620440B2 (en) * 2000-11-20 2005-02-16 日本電気株式会社 Semiconductor integrated circuit and clock distribution method thereof
JP2002312058A (en) * 2001-04-11 2002-10-25 Mitsubishi Electric Corp Semiconductor integrated circuit
US6538957B2 (en) * 2001-05-14 2003-03-25 Sony Computer Entertainment America Inc. Apparatus and method for distributing a clock signal on a large scale integrated circuit
US6686785B2 (en) * 2001-10-11 2004-02-03 Sun Microsystems, Inc. Deskewing global clock skew using localized DLLs
JP2003234643A (en) * 2002-02-07 2003-08-22 Mitsubishi Electric Corp Design method for semiconductor integrated circuit device and semiconductor integrated circuit device

Also Published As

Publication number Publication date
EP1697821A1 (en) 2006-09-06
CN100421048C (en) 2008-09-24
US20070194829A1 (en) 2007-08-23
DE602004012156D1 (en) 2008-04-10
WO2005064434A1 (en) 2005-07-14
US7474137B2 (en) 2009-01-06
JP2007519097A (en) 2007-07-12
CN1898626A (en) 2007-01-17
DE602004012156T2 (en) 2009-03-19
EP1697821B1 (en) 2008-02-27

Similar Documents

Publication Publication Date Title
TW428129B (en) Data path clock skew management in a dynamic power management environment
ATE401701T1 (en) METHOD AND CIRCUIT ARRANGEMENT FOR DATA TRANSMISSION BETWEEN PSEUDO-SYNCHRONIZED CHANNELS
US6242953B1 (en) Multiplexed synchronization circuits for switching frequency synthesized signals
TW200733567A (en) Clock generation circuit and method of generating clock signals
TW200610277A (en) Circuits and methods for recovering a clock signal
KR930013997A (en) Synchronizer device and method
DE60020742D1 (en) FREQUENCY DISTRIBUTION / MULTIPLICATION WITH MINIMIZATION OF THE JITTER
TW200419910A (en) Method and device for generating a clock signal having predetermined clock signal properties
TW200501586A (en) Delay locked loop (DLL) circuit and method for locking clock delay by using the same
ATE229667T1 (en) SYNCHRONOUS MULTI-PHASE CLOCK DISTRIBUTION SYSTEM
ATE387652T1 (en) CLOCK DISTRIBUTION IN INTEGRATED CIRCUITS
DE60238353D1 (en) SEAMLESS CLOCK
WO2004090682A3 (en) Minimization of clock skew and clock phase delay in integrated circuits
TWI264181B (en) Clock architecture for a frequency-based tester
DE60217408D1 (en) INFORMATION EXCHANGE BETWEEN LOCAL SYNCHRONIZED CIRCUITS
KR960009092A (en) Semiconductor Integrated Circuits with Testable Blocks
AU2001222415A1 (en) Device and method in a semiconductor circuit
TW200720932A (en) Memory controller and method thereof
WO2002025941A3 (en) System and method for single pin reset in a mixed signal integrated circuit
US20080191753A1 (en) Methods and Systems for Locally Generating Non-Integral Divided Clocks with Centralized State Machines
DE60136863D1 (en) INTEGRATED SEMICONDUCTOR SWITCHING
Mu et al. Digital multiphase clock/pattern generator
US20050147195A1 (en) Synchronizing circuit for stably generating an output signal
Zhuang et al. A design approach for gals based systems-on-chip
TW200635228A (en) Delay-locked loop device capable of anti-false-locking and related methods

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties