ATE384329T1 - Mram ohne isolationseinrichtungen - Google Patents

Mram ohne isolationseinrichtungen

Info

Publication number
ATE384329T1
ATE384329T1 AT03731902T AT03731902T ATE384329T1 AT E384329 T1 ATE384329 T1 AT E384329T1 AT 03731902 T AT03731902 T AT 03731902T AT 03731902 T AT03731902 T AT 03731902T AT E384329 T1 ATE384329 T1 AT E384329T1
Authority
AT
Austria
Prior art keywords
data
current
column
voltage
current conveyor
Prior art date
Application number
AT03731902T
Other languages
English (en)
Inventor
Peter Naji
Mark Durlam
Saied Tehrani
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Application granted granted Critical
Publication of ATE384329T1 publication Critical patent/ATE384329T1/de

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14Dummy cell management; Sense reference voltage generators
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1673Reading or sensing circuits or methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Semiconductor Memories (AREA)
  • Hall/Mr Elements (AREA)
  • Cable Accessories (AREA)
  • Insulated Conductors (AREA)
AT03731902T 2002-01-18 2003-01-09 Mram ohne isolationseinrichtungen ATE384329T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/051,646 US6512689B1 (en) 2002-01-18 2002-01-18 MRAM without isolation devices

Publications (1)

Publication Number Publication Date
ATE384329T1 true ATE384329T1 (de) 2008-02-15

Family

ID=21972539

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03731902T ATE384329T1 (de) 2002-01-18 2003-01-09 Mram ohne isolationseinrichtungen

Country Status (9)

Country Link
US (1) US6512689B1 (de)
EP (1) EP1476875B1 (de)
JP (2) JP2005520271A (de)
KR (1) KR20040077739A (de)
CN (1) CN100390899C (de)
AT (1) ATE384329T1 (de)
DE (1) DE60318683T2 (de)
TW (1) TWI283404B (de)
WO (1) WO2003063173A1 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10060432A1 (de) * 2000-12-05 2002-07-25 Infineon Technologies Ag Magnetoresistiver Speicher und Verfahren zu seinem Auslesen
US6839269B2 (en) * 2001-12-28 2005-01-04 Kabushiki Kaisha Toshiba Magnetic random access memory
JP4046513B2 (ja) * 2002-01-30 2008-02-13 株式会社ルネサステクノロジ 半導体集積回路
US6888743B2 (en) * 2002-12-27 2005-05-03 Freescale Semiconductor, Inc. MRAM architecture
TWI223259B (en) * 2003-01-07 2004-11-01 Ind Tech Res Inst A reference mid-point current generator for a magnetic random access memory
US6868025B2 (en) * 2003-03-10 2005-03-15 Sharp Laboratories Of America, Inc. Temperature compensated RRAM circuit
US6816403B1 (en) * 2003-05-14 2004-11-09 International Business Machines Corporation Capacitively coupled sensing apparatus and method for cross point magnetic random access memory devices
US7352618B2 (en) * 2004-12-15 2008-04-01 Samsung Electronics Co., Ltd. Multi-level cell memory device and associated read method
JP4660249B2 (ja) * 2005-03-31 2011-03-30 株式会社東芝 磁気ランダムアクセスメモリ
JP4987616B2 (ja) * 2006-08-31 2012-07-25 株式会社東芝 磁気ランダムアクセスメモリ及び抵抗ランダムアクセスメモリ
JP5044432B2 (ja) * 2008-02-07 2012-10-10 株式会社東芝 抵抗変化メモリ
KR101068573B1 (ko) * 2009-04-30 2011-09-30 주식회사 하이닉스반도체 반도체 메모리 장치
US9100013B2 (en) 2011-09-27 2015-08-04 Nec Corporation Nonvolatile resistor network assembly and nonvolatile logic gate with increased fault tolerance using the same
KR102015637B1 (ko) 2012-08-31 2019-08-28 삼성전자주식회사 가변 저항 메모리 장치 및 그 소거 검증 방법
US10176853B2 (en) * 2016-05-25 2019-01-08 Mediatek Inc. Pre-processing circuit with data-line DC immune clamping and associated method and sensing circuit
US10510393B2 (en) 2017-09-15 2019-12-17 Samsung Electronics Co., Ltd Resistive memory device including reference cell and operating method thereof
WO2019203132A1 (ja) * 2018-04-18 2019-10-24 国立大学法人東北大学 磁気抵抗効果素子、磁気メモリ装置並びに磁気メモリ装置の書き込み及び読み出し方法
US11460521B2 (en) * 2019-03-18 2022-10-04 Analog Devices International Unlimited Company Multiturn sensor arrangement
US11742012B2 (en) * 2021-05-28 2023-08-29 Nxp Usa, Inc. Memory read circuitry with a flipped voltage follower

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19853447A1 (de) * 1998-11-19 2000-05-25 Siemens Ag Magnetischer Speicher
KR100450466B1 (ko) * 1999-01-13 2004-09-30 인피니언 테크놀로지스 아게 Mram용 판독-/기록 아키텍처
DE19914489C1 (de) * 1999-03-30 2000-06-08 Siemens Ag Vorrichtung zur Bewertung der Zellenwiderstände in einem magnetoresistiven Speicher
US6205073B1 (en) * 2000-03-31 2001-03-20 Motorola, Inc. Current conveyor and method for readout of MTJ memories
JP3800925B2 (ja) * 2000-05-15 2006-07-26 日本電気株式会社 磁気ランダムアクセスメモリ回路
US6317376B1 (en) * 2000-06-20 2001-11-13 Hewlett-Packard Company Reference signal generation for magnetic random access memory devices
JP4726290B2 (ja) * 2000-10-17 2011-07-20 ルネサスエレクトロニクス株式会社 半導体集積回路
US6418046B1 (en) * 2001-01-30 2002-07-09 Motorola, Inc. MRAM architecture and system
US6445612B1 (en) * 2001-08-27 2002-09-03 Motorola, Inc. MRAM with midpoint generator reference and method for readout

Also Published As

Publication number Publication date
CN1620697A (zh) 2005-05-25
EP1476875A1 (de) 2004-11-17
JP2008135167A (ja) 2008-06-12
TWI283404B (en) 2007-07-01
CN100390899C (zh) 2008-05-28
KR20040077739A (ko) 2004-09-06
TW200302478A (en) 2003-08-01
DE60318683T2 (de) 2008-06-05
WO2003063173A1 (en) 2003-07-31
EP1476875B1 (de) 2008-01-16
JP2005520271A (ja) 2005-07-07
DE60318683D1 (de) 2008-03-06
US6512689B1 (en) 2003-01-28

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