ATE325429T1 - Verfahren zur herstellung einer für dissoziation ausgelegten belasteten struktur - Google Patents

Verfahren zur herstellung einer für dissoziation ausgelegten belasteten struktur

Info

Publication number
ATE325429T1
ATE325429T1 AT03815088T AT03815088T ATE325429T1 AT E325429 T1 ATE325429 T1 AT E325429T1 AT 03815088 T AT03815088 T AT 03815088T AT 03815088 T AT03815088 T AT 03815088T AT E325429 T1 ATE325429 T1 AT E325429T1
Authority
AT
Austria
Prior art keywords
substrates
assembling
substrate
faces
preform
Prior art date
Application number
AT03815088T
Other languages
English (en)
Inventor
Franck Fournel
Hubert Moriceau
Christelle Lagahe
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE325429T1 publication Critical patent/ATE325429T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Micromachines (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Hydraulic Control Valves For Brake Systems (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Investigating Strength Of Materials By Application Of Mechanical Stress (AREA)
  • Separation Using Semi-Permeable Membranes (AREA)
AT03815088T 2002-12-09 2003-12-08 Verfahren zur herstellung einer für dissoziation ausgelegten belasteten struktur ATE325429T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0215550A FR2848336B1 (fr) 2002-12-09 2002-12-09 Procede de realisation d'une structure contrainte destinee a etre dissociee

Publications (1)

Publication Number Publication Date
ATE325429T1 true ATE325429T1 (de) 2006-06-15

Family

ID=32320122

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03815088T ATE325429T1 (de) 2002-12-09 2003-12-08 Verfahren zur herstellung einer für dissoziation ausgelegten belasteten struktur

Country Status (7)

Country Link
US (2) US20060205179A1 (de)
EP (1) EP1570516B1 (de)
JP (1) JP4943656B2 (de)
AT (1) ATE325429T1 (de)
DE (1) DE60305067T2 (de)
FR (1) FR2848336B1 (de)
WO (1) WO2004064146A1 (de)

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FR2848336B1 (fr) 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
FR2856844B1 (fr) 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
FR2861497B1 (fr) 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
US8241996B2 (en) * 2005-02-28 2012-08-14 Silicon Genesis Corporation Substrate stiffness method and resulting devices for layer transfer process
FR2891281B1 (fr) 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
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FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
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FR2962594B1 (fr) * 2010-07-07 2012-08-31 Soitec Silicon On Insulator Procede de collage par adhesion moleculaire avec compensation de desalignement radial
FR2972078A1 (fr) * 2011-02-24 2012-08-31 Soitec Silicon On Insulator Appareil et procédé de collage par adhésion moléculaire
FR2972848A1 (fr) * 2011-03-18 2012-09-21 Soitec Silicon On Insulator Appareil et procédé de collage par adhésion moléculaire avec minimisation de déformations locales
FR2985370A1 (fr) * 2011-12-29 2013-07-05 Commissariat Energie Atomique Procede de fabrication d'une structure multicouche sur un support
US8916450B2 (en) * 2012-08-02 2014-12-23 International Business Machines Corporation Method for improving quality of spalled material layers
CN106548972B (zh) * 2015-09-18 2019-02-26 胡兵 一种将半导体衬底主体与其上功能层进行分离的方法
FR3077923B1 (fr) 2018-02-12 2021-07-16 Soitec Silicon On Insulator Procede de fabrication d'une structure de type semi-conducteur sur isolant par transfert de couche
KR102648711B1 (ko) 2018-09-20 2024-03-20 삼성전자주식회사 기판 본딩 장치 및 그를 이용한 기판 본딩 방법
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EP1570516A1 (de) 2005-09-07
US8389379B2 (en) 2013-03-05
US20100167499A1 (en) 2010-07-01
FR2848336A1 (fr) 2004-06-11
DE60305067D1 (de) 2006-06-08
DE60305067T2 (de) 2006-12-07
EP1570516B1 (de) 2006-05-03
WO2004064146A1 (fr) 2004-07-29
FR2848336B1 (fr) 2005-10-28
JP4943656B2 (ja) 2012-05-30
US20060205179A1 (en) 2006-09-14

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