ATE287118T1 - Verfahren für eine zweifache ausgangsdatenrate - Google Patents

Verfahren für eine zweifache ausgangsdatenrate

Info

Publication number
ATE287118T1
ATE287118T1 AT00961533T AT00961533T ATE287118T1 AT E287118 T1 ATE287118 T1 AT E287118T1 AT 00961533 T AT00961533 T AT 00961533T AT 00961533 T AT00961533 T AT 00961533T AT E287118 T1 ATE287118 T1 AT E287118T1
Authority
AT
Austria
Prior art keywords
data
pipelines
output data
data rate
double output
Prior art date
Application number
AT00961533T
Other languages
English (en)
Inventor
Mark R Thomann
Wen Li
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE287118T1 publication Critical patent/ATE287118T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization

Landscapes

  • Dram (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Optical Communication System (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
AT00961533T 1999-09-02 2000-08-31 Verfahren für eine zweifache ausgangsdatenrate ATE287118T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/388,686 US6694416B1 (en) 1999-09-02 1999-09-02 Double data rate scheme for data output
PCT/US2000/024283 WO2001016958A1 (en) 1999-09-02 2000-08-31 Double data rate scheme for data output

Publications (1)

Publication Number Publication Date
ATE287118T1 true ATE287118T1 (de) 2005-01-15

Family

ID=23535096

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00961533T ATE287118T1 (de) 1999-09-02 2000-08-31 Verfahren für eine zweifache ausgangsdatenrate

Country Status (8)

Country Link
US (3) US6694416B1 (de)
EP (1) EP1208567B1 (de)
JP (1) JP4495381B2 (de)
KR (1) KR100466989B1 (de)
AT (1) ATE287118T1 (de)
AU (1) AU7347400A (de)
DE (1) DE60017419T2 (de)
WO (1) WO2001016958A1 (de)

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US7677052B2 (en) * 2005-03-28 2010-03-16 Intel Corporation Systems for improved passive liquid cooling
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US8127049B1 (en) * 2008-03-12 2012-02-28 Matrox Graphics Inc. Input/output pin allocation for data streams of variable widths
US20100266081A1 (en) * 2009-04-21 2010-10-21 International Business Machines Corporation System and Method for Double Rate Clocking Pulse Generation With Mistrack Cancellation
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US9176920B2 (en) 2012-10-24 2015-11-03 Sandisk Technologies Inc. Multi-level encoded data transfer
KR102106064B1 (ko) * 2013-07-11 2020-05-28 에스케이하이닉스 주식회사 반도체 장치 및 이의 제어 방법
US9209961B1 (en) * 2014-09-29 2015-12-08 Apple Inc. Method and apparatus for delay compensation in data transmission
US9779813B2 (en) 2015-09-11 2017-10-03 Macronix International Co., Ltd. Phase change memory array architecture achieving high write/read speed
US10360956B2 (en) 2017-12-07 2019-07-23 Micron Technology, Inc. Wave pipeline
CA3165378A1 (en) * 2021-10-09 2023-04-09 Nan Li Pipeline clock driving circuit, computing chip, hashboard and computing device

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Also Published As

Publication number Publication date
KR20020029118A (ko) 2002-04-17
US20040117543A1 (en) 2004-06-17
US7093095B2 (en) 2006-08-15
EP1208567B1 (de) 2005-01-12
DE60017419D1 (de) 2005-02-17
US7251715B2 (en) 2007-07-31
US20060198234A1 (en) 2006-09-07
US6694416B1 (en) 2004-02-17
JP2003508840A (ja) 2003-03-04
JP4495381B2 (ja) 2010-07-07
AU7347400A (en) 2001-03-26
EP1208567A1 (de) 2002-05-29
DE60017419T2 (de) 2005-12-22
WO2001016958A1 (en) 2001-03-08
KR100466989B1 (ko) 2005-01-24

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