DE60017419D1 - Verfahren für eine zweifache ausgangsdatenrate - Google Patents

Verfahren für eine zweifache ausgangsdatenrate

Info

Publication number
DE60017419D1
DE60017419D1 DE60017419T DE60017419T DE60017419D1 DE 60017419 D1 DE60017419 D1 DE 60017419D1 DE 60017419 T DE60017419 T DE 60017419T DE 60017419 T DE60017419 T DE 60017419T DE 60017419 D1 DE60017419 D1 DE 60017419D1
Authority
DE
Germany
Prior art keywords
data
pipelines
output data
data rate
procedure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60017419T
Other languages
English (en)
Other versions
DE60017419T2 (de
Inventor
R Thomann
Wen Li
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE60017419D1 publication Critical patent/DE60017419D1/de
Application granted granted Critical
Publication of DE60017419T2 publication Critical patent/DE60017419T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
DE60017419T 1999-09-02 2000-08-31 Verfahren für eine zweifache ausgangsdatenrate Expired - Lifetime DE60017419T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/388,686 US6694416B1 (en) 1999-09-02 1999-09-02 Double data rate scheme for data output
US388686 1999-09-02
PCT/US2000/024283 WO2001016958A1 (en) 1999-09-02 2000-08-31 Double data rate scheme for data output

Publications (2)

Publication Number Publication Date
DE60017419D1 true DE60017419D1 (de) 2005-02-17
DE60017419T2 DE60017419T2 (de) 2005-12-22

Family

ID=23535096

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60017419T Expired - Lifetime DE60017419T2 (de) 1999-09-02 2000-08-31 Verfahren für eine zweifache ausgangsdatenrate

Country Status (8)

Country Link
US (3) US6694416B1 (de)
EP (1) EP1208567B1 (de)
JP (1) JP4495381B2 (de)
KR (1) KR100466989B1 (de)
AT (1) ATE287118T1 (de)
AU (1) AU7347400A (de)
DE (1) DE60017419T2 (de)
WO (1) WO2001016958A1 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7082162B2 (en) * 1999-04-17 2006-07-25 Pts Corporation Segment-based encoding system including segment-specific metadata
US6694416B1 (en) * 1999-09-02 2004-02-17 Micron Technology, Inc. Double data rate scheme for data output
JP4756729B2 (ja) * 2000-07-31 2011-08-24 エルピーダメモリ株式会社 半導体記憶装置
US6678811B2 (en) * 2001-04-07 2004-01-13 Hewlett-Packard Development Company, L.P. Memory controller with 1X/MX write capability
US6633965B2 (en) * 2001-04-07 2003-10-14 Eric M. Rentschler Memory controller with 1×/M× read capability
KR100452328B1 (ko) * 2002-07-31 2004-10-12 삼성전자주식회사 동기식 반도체 메모리 장치의 데이터 출력회로
US7010713B2 (en) 2002-12-19 2006-03-07 Mosaid Technologies, Inc. Synchronization circuit and method with transparent latches
US7677052B2 (en) * 2005-03-28 2010-03-16 Intel Corporation Systems for improved passive liquid cooling
TWI338839B (en) * 2007-06-27 2011-03-11 Etron Technology Inc Memory control system and memory data fetching method
US8180970B2 (en) * 2008-02-22 2012-05-15 International Business Machines Corporation Least recently used (LRU) compartment capture in a cache memory system
US8127049B1 (en) * 2008-03-12 2012-02-28 Matrox Graphics Inc. Input/output pin allocation for data streams of variable widths
US20100266081A1 (en) * 2009-04-21 2010-10-21 International Business Machines Corporation System and Method for Double Rate Clocking Pulse Generation With Mistrack Cancellation
JP2010257540A (ja) * 2009-04-27 2010-11-11 Toshiba Corp 不揮発性半導体記憶装置
US9176920B2 (en) 2012-10-24 2015-11-03 Sandisk Technologies Inc. Multi-level encoded data transfer
KR102106064B1 (ko) * 2013-07-11 2020-05-28 에스케이하이닉스 주식회사 반도체 장치 및 이의 제어 방법
US9209961B1 (en) * 2014-09-29 2015-12-08 Apple Inc. Method and apparatus for delay compensation in data transmission
US9779813B2 (en) 2015-09-11 2017-10-03 Macronix International Co., Ltd. Phase change memory array architecture achieving high write/read speed
US10360956B2 (en) 2017-12-07 2019-07-23 Micron Technology, Inc. Wave pipeline
CA3165378A1 (en) * 2021-10-09 2023-04-09 Nan Li Pipeline clock driving circuit, computing chip, hashboard and computing device

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4463443A (en) 1979-07-24 1984-07-31 The United States Of America As Represented By The Secretary Of The Air Force Data buffer apparatus between subsystems which operate at differing or varying data rates
US5007012A (en) 1988-09-09 1991-04-09 Advanced Micro Devices, Inc. Fly-by data transfer system
US5506814A (en) 1993-05-28 1996-04-09 Micron Technology, Inc. Video random access memory device and method implementing independent two WE nibble control
US5402389A (en) 1994-03-08 1995-03-28 Motorola, Inc. Synchronous memory having parallel output data paths
US5834800A (en) * 1995-04-10 1998-11-10 Lucent Technologies Inc. Heterojunction bipolar transistor having mono crystalline SiGe intrinsic base and polycrystalline SiGe and Si extrinsic base regions
US5719890A (en) 1995-06-01 1998-02-17 Micron Technology, Inc. Method and circuit for transferring data with dynamic parity generation and checking scheme in multi-port DRAM
US5592488A (en) 1995-06-07 1997-01-07 Micron Technology, Inc. Method and apparatus for pipelined multiplexing employing analog delays for a multiport interface
US5854800A (en) 1995-06-07 1998-12-29 Micron Technlogy, Inc. Method and apparatus for a high speed cyclical redundancy check system
JPH098989A (ja) 1995-06-19 1997-01-10 Brother Ind Ltd パラレルデータ転送システム及び電子機器
US5657289A (en) 1995-08-30 1997-08-12 Micron Technology, Inc. Expandable data width SAM for a multiport RAM
US5724288A (en) 1995-08-30 1998-03-03 Micron Technology, Inc. Data communication for memory
JPH09161471A (ja) 1995-12-06 1997-06-20 Internatl Business Mach Corp <Ibm> Ｄｒａｍシステム、ｄｒａｍシステムの動作方法
US5663916A (en) 1996-05-21 1997-09-02 Elonex I.P. Holdings, Ltd. Apparatus and method for minimizing DRAM recharge time
US5834813A (en) 1996-05-23 1998-11-10 Micron Technology, Inc. Field-effect transistor for one-time programmable nonvolatile memory element
US5815447A (en) 1996-08-08 1998-09-29 Micron Technology, Inc. Memory device having complete row redundancy
US5915128A (en) 1997-01-29 1999-06-22 Unisys Corporation Serial speed-matching buffer utilizing plurality of registers where each register selectively receives data from transferring units or sequentially transfers data to another register
KR100268429B1 (ko) * 1997-03-18 2000-11-01 윤종용 동기형반도체메모리장치의데이터의입력회로및데이터입력방법
KR100238242B1 (ko) 1997-04-22 2000-01-15 윤종용 반도체 메모리장치의 동작 제어장치
US6067585A (en) 1997-06-23 2000-05-23 Compaq Computer Corporation Adaptive interface controller that can operate with segments of different protocol and transmission rates in a single integrated device
JP3414621B2 (ja) 1997-08-11 2003-06-09 富士通株式会社 半導体集積回路装置
JP3788867B2 (ja) * 1997-10-28 2006-06-21 株式会社東芝 半導体記憶装置
US5920511A (en) 1997-12-22 1999-07-06 Samsung Electronics Co., Ltd. High-speed data input circuit for a synchronous memory device
JP3386705B2 (ja) * 1997-12-25 2003-03-17 株式会社東芝 半導体記憶装置およびそのバーストアドレスカウンタ
KR100252057B1 (ko) 1997-12-30 2000-05-01 윤종용 단일 및 이중 데이터 율 겸용 반도체 메모리 장치
KR100278653B1 (ko) 1998-01-23 2001-02-01 윤종용 이중 데이터율 모드 반도체 메모리 장치
US5963469A (en) 1998-02-24 1999-10-05 Micron Technology, Inc. Vertical bipolar read access for low voltage memory cell
SE9801118D0 (sv) 1998-03-30 1998-03-30 Astra Ab Electrical device
DE69923769T2 (de) * 1998-04-01 2006-02-02 Mosaid Technologies Incorporated, Kanata Asynchrones halbleiterspeicher-fliessband
US6314042B1 (en) 1998-05-22 2001-11-06 Mitsubishi Denki Kabushiki Kaisha Fast accessible semiconductor memory device
US6112267A (en) 1998-05-28 2000-08-29 Digital Equipment Corporation Hierarchical ring buffers for buffering data between processor and I/O device permitting data writes by processor and data reads by I/O device simultaneously directed at different buffers at different levels
US5923258A (en) * 1998-06-09 1999-07-13 K Jump Health Co., Ltd. Electronic thermometer with high intensity fever alarm
JP2000067577A (ja) 1998-06-10 2000-03-03 Mitsubishi Electric Corp 同期型半導体記憶装置
US6202139B1 (en) * 1998-06-19 2001-03-13 Advanced Micro Devices, Inc. Pipelined data cache with multiple ports and processor with load/store unit selecting only load or store operations for concurrent processing
US6446180B2 (en) * 1999-07-19 2002-09-03 Micron Technology, Inc. Memory device with synchronized output path
US6516363B1 (en) * 1999-08-06 2003-02-04 Micron Technology, Inc. Output data path having selectable data rates
US6477592B1 (en) 1999-08-06 2002-11-05 Integrated Memory Logic, Inc. System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream
US6694416B1 (en) * 1999-09-02 2004-02-17 Micron Technology, Inc. Double data rate scheme for data output

Also Published As

Publication number Publication date
US20060198234A1 (en) 2006-09-07
US20040117543A1 (en) 2004-06-17
JP4495381B2 (ja) 2010-07-07
ATE287118T1 (de) 2005-01-15
JP2003508840A (ja) 2003-03-04
EP1208567A1 (de) 2002-05-29
US6694416B1 (en) 2004-02-17
WO2001016958A1 (en) 2001-03-08
EP1208567B1 (de) 2005-01-12
KR20020029118A (ko) 2002-04-17
DE60017419T2 (de) 2005-12-22
AU7347400A (en) 2001-03-26
US7093095B2 (en) 2006-08-15
KR100466989B1 (ko) 2005-01-24
US7251715B2 (en) 2007-07-31

Similar Documents

Publication Publication Date Title
DE60017419D1 (de) Verfahren für eine zweifache ausgangsdatenrate
KR960012011A (ko) 데이타 억세스로부터 파이프라인 단들 사이의 차이로 인한 시간 손실을 제거하는 반도체 파이프라인 메모리 장치
GB0227503D0 (en) Devices,systems and methods for obtaining timing information and ranging
WO2003039061A3 (en) Clock domain crossing fifo
MY125891A (en) Method of using av devices and av device system.
NO20021359L (no) Akustisk telemetrisystem med höy datahastighet
DE3481739D1 (de) Verkaufspunkt- und elektronische geldueberweisungssysteme.
FR2735892B1 (fr) Dispositif de lecture de symbole de donnees
DE68923378T2 (de) Verbindungsvorrichtung für rohre.
TW200623145A (en) Pseudo-synchronization of the transportation of data across asynchronous clock domains
DE69205078D1 (de) Verbindungstechnik für elektronische Vorrichtungen.
DE50013084D1 (de) Datenübertragungssystem für Luftfahrzeuge
GB1469565A (en) Data processing systems employing semiconductor compatible charge transfer devices
CA2217375A1 (en) Bi-directional data bus scheme with optimized read and write characteristics
DE69517649T2 (de) Halbleiterplattenvorrichtung mit konstanter Dateneinschreibzeitperiode
FR2734932B1 (fr) Dispositif de lecture de symboles de donnees
WO2001050231A3 (en) Encoded clocks to distribute multiple clock signals to multiple devices in a computer system
ATE479137T1 (de) Datensynchronisationsverfahren und -system
DE69223990D1 (de) Auch gegen mehrfachfehler sicherer, fehlertoleranter taktgeber
DE69312697D1 (de) Datenübertragungsempfangsystem für elektronische Uhr
TW200601351A (en) Semiconductor memory device having test mode for data access time
WO2006120225A3 (en) Dumping data in processing systems to a shared storage
DE68917679T2 (de) Datenübertragungsnetzwerk für Multiprozessorsysteme.
FR2836251B1 (fr) Dispositif et procede de securisation de donnees sensibles, notamment entre deux parties via un organisme tiers
DE60015939D1 (de) Verfahren und schaltung um an zwei enden getakten daten zu empfangen

Legal Events

Date Code Title Description
8364 No opposition during term of opposition