ATE251342T1 - Verfahren zum füllen eines hohraumes in einem substrat - Google Patents

Verfahren zum füllen eines hohraumes in einem substrat

Info

Publication number
ATE251342T1
ATE251342T1 AT92304633T AT92304633T ATE251342T1 AT E251342 T1 ATE251342 T1 AT E251342T1 AT 92304633 T AT92304633 T AT 92304633T AT 92304633 T AT92304633 T AT 92304633T AT E251342 T1 ATE251342 T1 AT E251342T1
Authority
AT
Austria
Prior art keywords
layer
filling
cavity
substrate
article
Prior art date
Application number
AT92304633T
Other languages
German (de)
English (en)
Inventor
Christopher David Dobson
Original Assignee
Trikon Technologies Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB919111440A external-priority patent/GB9111440D0/en
Priority claimed from GB929202745A external-priority patent/GB9202745D0/en
Application filed by Trikon Technologies Ltd filed Critical Trikon Technologies Ltd
Application granted granted Critical
Publication of ATE251342T1 publication Critical patent/ATE251342T1/de

Links

Classifications

    • H10P72/0454
    • H10D64/011
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4084Through-connections; Vertical interconnect access [VIA] connections by deforming at least one of the conductive layers
    • H10P14/40
    • H10P72/0468
    • H10P95/00
    • H10P95/04
    • H10W20/059
    • H10W20/092
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0335Layered conductors or foils
    • H05K2201/0355Metal foils
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0278Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Vapour Deposition (AREA)
  • Element Separation (AREA)
  • Chemical Vapour Deposition (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
AT92304633T 1991-05-28 1992-05-21 Verfahren zum füllen eines hohraumes in einem substrat ATE251342T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB919111440A GB9111440D0 (en) 1991-05-28 1991-05-28 Forming a layer
GB929202745A GB9202745D0 (en) 1992-02-10 1992-02-10 Forming a layer

Publications (1)

Publication Number Publication Date
ATE251342T1 true ATE251342T1 (de) 2003-10-15

Family

ID=26298966

Family Applications (1)

Application Number Title Priority Date Filing Date
AT92304633T ATE251342T1 (de) 1991-05-28 1992-05-21 Verfahren zum füllen eines hohraumes in einem substrat

Country Status (6)

Country Link
EP (1) EP0516344B1 (enExample)
JP (1) JP3105643B2 (enExample)
KR (1) KR100242602B1 (enExample)
AT (1) ATE251342T1 (enExample)
DE (1) DE69233222T2 (enExample)
TW (1) TW221521B (enExample)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9414145D0 (en) * 1994-07-13 1994-08-31 Electrotech Ltd Forming a layer
US5932289A (en) * 1991-05-28 1999-08-03 Trikon Technologies Limited Method for filling substrate recesses using pressure and heat treatment
GB9402486D0 (en) * 1994-02-09 1994-03-30 Electrotech Ltd Forming a layer
KR960026249A (ko) * 1994-12-12 1996-07-22 윌리엄 이. 힐러 고압, 저온 반도체 갭 충진 프로세스
EP0793268A3 (en) * 1995-05-23 1999-03-03 Texas Instruments Incorporated Process for filling a cavity in a semiconductor device
US5857368A (en) * 1995-10-06 1999-01-12 Applied Materials, Inc. Apparatus and method for fabricating metal paths in semiconductor substrates through high pressure extrusion
GB9619461D0 (en) 1996-09-18 1996-10-30 Electrotech Ltd Method of processing a workpiece
GB2319533B (en) 1996-11-22 2001-06-06 Trikon Equip Ltd Methods of forming a barrier layer
GB2319532B (en) * 1996-11-22 2001-01-31 Trikon Equip Ltd Method and apparatus for treating a semiconductor wafer
US6218277B1 (en) 1998-01-26 2001-04-17 Texas Instruments Incorporated Method for filling a via opening or contact opening in an integrated circuit
US7322981B2 (en) 2003-08-28 2008-01-29 Jackson Roger P Polyaxial bone screw with split retainer ring
JP4357486B2 (ja) 2003-06-18 2009-11-04 ロジャー・ピー・ジャクソン スプライン捕捉連結部を備えた多軸骨ねじ
US7160300B2 (en) 2004-02-27 2007-01-09 Jackson Roger P Orthopedic implant rod reduction tool set and method
US10049927B2 (en) 2016-06-10 2018-08-14 Applied Materials, Inc. Seam-healing method upon supra-atmospheric process in diffusion promoting ambient
US10224224B2 (en) 2017-03-10 2019-03-05 Micromaterials, LLC High pressure wafer processing systems and related methods
US10622214B2 (en) 2017-05-25 2020-04-14 Applied Materials, Inc. Tungsten defluorination by high pressure treatment
US10276411B2 (en) 2017-08-18 2019-04-30 Applied Materials, Inc. High pressure and high temperature anneal chamber
JP6947914B2 (ja) 2017-08-18 2021-10-13 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated 高圧高温下のアニールチャンバ
CN117936417A (zh) 2017-11-11 2024-04-26 微材料有限责任公司 用于高压处理腔室的气体输送系统
KR20200075892A (ko) 2017-11-17 2020-06-26 어플라이드 머티어리얼스, 인코포레이티드 고압 처리 시스템을 위한 컨덴서 시스템
EP3762962A4 (en) 2018-03-09 2021-12-08 Applied Materials, Inc. HIGH PRESSURE ANNEALING PROCESS FOR METAL-BASED MATERIALS
US10950429B2 (en) 2018-05-08 2021-03-16 Applied Materials, Inc. Methods of forming amorphous carbon hard mask layers and hard mask layers formed therefrom
US10748783B2 (en) 2018-07-25 2020-08-18 Applied Materials, Inc. Gas delivery module
WO2020117462A1 (en) 2018-12-07 2020-06-11 Applied Materials, Inc. Semiconductor processing system
US11901222B2 (en) 2020-02-17 2024-02-13 Applied Materials, Inc. Multi-step process for flowable gap-fill film
CN113543527B (zh) * 2021-07-09 2022-12-30 广东工业大学 载板填孔工艺的填充基材选型方法及载板填孔工艺

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69023382T2 (de) * 1989-04-17 1996-06-20 Ibm Laminierungsverfahren zum Überdecken der Seitenwände einer Höhlung in einem Substrat sowie zur Füllung dieser Höhlung.
US5011793A (en) * 1990-06-19 1991-04-30 Nihon Shinku Gijutsu Kabushiki Kaisha Vacuum deposition using pressurized reflow process

Also Published As

Publication number Publication date
DE69233222D1 (de) 2003-11-06
JP3105643B2 (ja) 2000-11-06
DE69233222T2 (de) 2004-08-26
EP0516344B1 (en) 2003-10-01
KR920022405A (ko) 1992-12-19
KR100242602B1 (ko) 2000-02-01
TW221521B (enExample) 1994-03-01
JPH07193063A (ja) 1995-07-28
EP0516344A1 (en) 1992-12-02

Similar Documents

Publication Publication Date Title
ATE251342T1 (de) Verfahren zum füllen eines hohraumes in einem substrat
DE59209850D1 (de) Verfahren zur Herstellung eines Halbleiter-Bauelements
ATE212725T1 (de) Verfahren zur herstellung eines halbleitersensors
DE69127395D1 (de) Verfahren zum Herstellen eines Dünnfilm-Transistors mit polykristallinem Halbleiter
DE3851125D1 (de) Verfahren zur Herstellung eines Halbleiterbauelementes mit Schaltungsmaterial gefüllter Rille.
EP0500069A3 (en) Method for etching silicon compound film and process for forming article by utilizing the method
JPS5339349A (en) Thermosetting resin molding material
JPS5512735A (en) Semiconductor device
JPS5443461A (en) Packing method of semiconductor wafer
JPS5522849A (en) Manufacturing method of material for magnetic- electrical conversion element
JPS5587436A (en) Method of producing semiconductor device
JPS5381069A (en) Production of susceptor in cvd device
JPS5518053A (en) Packing of method semiconductor wafer
JPS52106673A (en) Crystal growing method and device thereof
JPS51121270A (en) Semiconductor device
JPS5766328A (en) Semiconductor pressure sensor
JPS52151561A (en) Polishing method of semiconductor wafers
JPS5678495A (en) Preparation of base
JPS54577A (en) Resin seal semiconductor device
JPH03162596A (ja) 部分メッキ方法及び装置
JPS5259589A (en) Production of semiconductor device
JPS5361595A (en) Liquid phase epitaxial growing method for gaas-algaas
KR950001304B1 (en) Semiconductor device isolation method
JPS5367362A (en) Manufacture of semiconductor device
JPS5335474A (en) Fixing method of wafer, mask substrate, and so on

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties