ATE201111T1 - Verfahren und vorrichtung zur programmierung von speicheranordnungen - Google Patents

Verfahren und vorrichtung zur programmierung von speicheranordnungen

Info

Publication number
ATE201111T1
ATE201111T1 AT95301953T AT95301953T ATE201111T1 AT E201111 T1 ATE201111 T1 AT E201111T1 AT 95301953 T AT95301953 T AT 95301953T AT 95301953 T AT95301953 T AT 95301953T AT E201111 T1 ATE201111 T1 AT E201111T1
Authority
AT
Austria
Prior art keywords
circuit
programming
program mode
memory cells
integrated
Prior art date
Application number
AT95301953T
Other languages
English (en)
Inventor
George Chang
Pearl Cheng
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE201111T1 publication Critical patent/ATE201111T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Logic Circuits (AREA)
AT95301953T 1994-04-14 1995-03-23 Verfahren und vorrichtung zur programmierung von speicheranordnungen ATE201111T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/227,755 US5530803A (en) 1994-04-14 1994-04-14 Method and apparatus for programming memory devices

Publications (1)

Publication Number Publication Date
ATE201111T1 true ATE201111T1 (de) 2001-05-15

Family

ID=22854328

Family Applications (1)

Application Number Title Priority Date Filing Date
AT95301953T ATE201111T1 (de) 1994-04-14 1995-03-23 Verfahren und vorrichtung zur programmierung von speicheranordnungen

Country Status (7)

Country Link
US (1) US5530803A (de)
EP (1) EP0677850B1 (de)
JP (1) JP3741744B2 (de)
KR (1) KR100357443B1 (de)
AT (1) ATE201111T1 (de)
DE (1) DE69520853T2 (de)
TW (1) TW332292B (de)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5787039A (en) * 1997-03-06 1998-07-28 Macronix International Co., Ltd. Low current floating gate programming with bit-by-bit verification
JP3156636B2 (ja) * 1997-05-30 2001-04-16 日本電気株式会社 不揮発性半導体記憶装置
US6768165B1 (en) 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6928001B2 (en) * 2000-12-07 2005-08-09 Saifun Semiconductors Ltd. Programming and erasing methods for a non-volatile memory cell
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US6665769B2 (en) * 2001-04-05 2003-12-16 Saifun Semiconductors Ltd. Method and apparatus for dynamically masking an N-bit memory array having individually programmable cells
KR100393595B1 (ko) * 2001-08-27 2003-08-02 엘지전자 주식회사 메모리 프로그래밍 시스템 및 그 방법
US6700818B2 (en) * 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
US7190620B2 (en) * 2002-01-31 2007-03-13 Saifun Semiconductors Ltd. Method for operating a memory device
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US6967896B2 (en) * 2003-01-30 2005-11-22 Saifun Semiconductors Ltd Address scramble
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US7142464B2 (en) 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
US7123532B2 (en) 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US7652930B2 (en) 2004-04-01 2010-01-26 Saifun Semiconductors Ltd. Method, circuit and system for erasing one or more non-volatile memory cells
US7366025B2 (en) * 2004-06-10 2008-04-29 Saifun Semiconductors Ltd. Reduced power programming of non-volatile cells
US7317633B2 (en) 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
US7095655B2 (en) 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7535765B2 (en) 2004-12-09 2009-05-19 Saifun Semiconductors Ltd. Non-volatile memory device and method for reading cells
CN1838328A (zh) 2005-01-19 2006-09-27 赛芬半导体有限公司 擦除存储器阵列上存储单元的方法
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US8400841B2 (en) 2005-06-15 2013-03-19 Spansion Israel Ltd. Device to program adjacent storage cells of different NROM cells
JP2007027760A (ja) 2005-07-18 2007-02-01 Saifun Semiconductors Ltd 高密度不揮発性メモリアレイ及び製造方法
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US7443732B2 (en) * 2005-09-20 2008-10-28 Spansion Llc High performance flash memory device capable of high density data storage
US7221138B2 (en) 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
TWI308692B (en) 2005-10-26 2009-04-11 Sunplus Technology Co Ltd Programmable memory and accessing method of the same
US7352627B2 (en) 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
KR101333503B1 (ko) * 2006-02-03 2013-11-28 삼성전자주식회사 프로그램 셀의 수에 따라 프로그램 전압을 조절하는 반도체메모리 장치 및 그것의 프로그램 방법
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US7638835B2 (en) 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US7605579B2 (en) 2006-09-18 2009-10-20 Saifun Semiconductors Ltd. Measuring and controlling current consumption and output current of charge pumps
US7590001B2 (en) 2007-12-18 2009-09-15 Saifun Semiconductors Ltd. Flash memory with optimized write sector spares
US8570828B2 (en) * 2010-04-12 2013-10-29 Mosaid Technologies Incorporated Memory programming using variable data width

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6151695A (ja) * 1984-08-22 1986-03-14 Hitachi Ltd 半導体集積回路装置
EP0195429A3 (de) * 1985-03-20 1989-03-22 Kabushiki Kaisha Toshiba Halbleiterspeichergerät
JPS61292755A (ja) * 1985-06-20 1986-12-23 Fujitsu Ltd 半導体集積回路
US4763305A (en) * 1985-11-27 1988-08-09 Motorola, Inc. Intelligent write in an EEPROM with data and erase check
NL8600099A (nl) * 1986-01-20 1987-08-17 Philips Nv Niet-vluchtig, programmeerbaar halfgeleidergeheugen.
JPS63175300A (ja) * 1987-01-16 1988-07-19 Hitachi Ltd 半導体集積回路装置
JPH02195599A (ja) * 1989-01-24 1990-08-02 Ricoh Co Ltd 情報処理装置
JP2900523B2 (ja) * 1990-05-31 1999-06-02 日本電気株式会社 不揮発性半導体メモリ装置の書込回路
US5224103A (en) * 1990-07-16 1993-06-29 North American Philips Corporation Processing device and method of programming such a processing device
US5228000A (en) * 1990-08-02 1993-07-13 Mitsubishi Denki Kabushiki Kaisha Test circuit of semiconductor memory device
KR960002006B1 (ko) * 1991-03-12 1996-02-09 가부시끼가이샤 도시바 2개의 기준 레벨을 사용하는 기록 검증 제어기를 갖는 전기적으로 소거 가능하고 프로그램 가능한 불휘발성 메모리 장치
JPH06267283A (ja) * 1993-03-16 1994-09-22 Mitsubishi Electric Corp データ書き込み可能な読み出し専用メモリ及びそのデータ書き込み／読み出し方法

Also Published As

Publication number Publication date
EP0677850A3 (de) 1996-12-11
TW332292B (en) 1998-05-21
JPH0845290A (ja) 1996-02-16
EP0677850A2 (de) 1995-10-18
US5530803A (en) 1996-06-25
KR950033835A (ko) 1995-12-26
EP0677850B1 (de) 2001-05-09
JP3741744B2 (ja) 2006-02-01
DE69520853T2 (de) 2001-12-20
KR100357443B1 (ko) 2002-12-12
DE69520853D1 (de) 2001-06-13

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