ATE158113T1 - Bitleitungsanordnung für integrierte schaltungen - Google Patents

Bitleitungsanordnung für integrierte schaltungen

Info

Publication number
ATE158113T1
ATE158113T1 AT92120086T AT92120086T ATE158113T1 AT E158113 T1 ATE158113 T1 AT E158113T1 AT 92120086 T AT92120086 T AT 92120086T AT 92120086 T AT92120086 T AT 92120086T AT E158113 T1 ATE158113 T1 AT E158113T1
Authority
AT
Austria
Prior art keywords
integrated circuits
line arrangement
contacts
bit lines
contact surfaces
Prior art date
Application number
AT92120086T
Other languages
German (de)
English (en)
Inventor
Hanno Dipl-Phys Melzner
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of ATE158113T1 publication Critical patent/ATE158113T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Landscapes

  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AT92120086T 1991-12-02 1992-11-25 Bitleitungsanordnung für integrierte schaltungen ATE158113T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE4139719A DE4139719C1 (OSRAM) 1991-12-02 1991-12-02

Publications (1)

Publication Number Publication Date
ATE158113T1 true ATE158113T1 (de) 1997-09-15

Family

ID=6446093

Family Applications (1)

Application Number Title Priority Date Filing Date
AT92120086T ATE158113T1 (de) 1991-12-02 1992-11-25 Bitleitungsanordnung für integrierte schaltungen

Country Status (7)

Country Link
US (1) US5315542A (OSRAM)
EP (1) EP0545256B1 (OSRAM)
JP (1) JP3304146B2 (OSRAM)
KR (1) KR100279485B1 (OSRAM)
AT (1) ATE158113T1 (OSRAM)
DE (2) DE4139719C1 (OSRAM)
TW (1) TW226484B (OSRAM)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2884962B2 (ja) * 1992-10-30 1999-04-19 日本電気株式会社 半導体メモリ
US5864181A (en) * 1993-09-15 1999-01-26 Micron Technology, Inc. Bi-level digit line architecture for high density DRAMs
JP2638487B2 (ja) * 1994-06-30 1997-08-06 日本電気株式会社 半導体記憶装置
TW318281B (OSRAM) * 1994-08-30 1997-10-21 Mitsubishi Electric Corp
US6043562A (en) 1996-01-26 2000-03-28 Micron Technology, Inc. Digit line architecture for dynamic memory
US5864496A (en) * 1997-09-29 1999-01-26 Siemens Aktiengesellschaft High density semiconductor memory having diagonal bit lines and dual word lines
TW417290B (en) * 1998-06-26 2001-01-01 Texas Instruments Inc Relaxed layout for storage nodes for dynamic random access memories
US6249451B1 (en) 1999-02-08 2001-06-19 Kabushiki Kaisha Toshiba Data line connections with twisting scheme technical field
US6282113B1 (en) * 1999-09-29 2001-08-28 International Business Machines Corporation Four F-squared gapless dual layer bitline DRAM array architecture
JP4936582B2 (ja) * 2000-07-28 2012-05-23 ルネサスエレクトロニクス株式会社 半導体記憶装置
US9911693B2 (en) 2015-08-28 2018-03-06 Micron Technology, Inc. Semiconductor devices including conductive lines and methods of forming the semiconductor devices
US9553048B1 (en) * 2015-09-04 2017-01-24 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method of semiconductor device
US10818729B2 (en) * 2018-05-17 2020-10-27 Macronix International Co., Ltd. Bit cost scalable 3D phase change cross-point memory

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0760858B2 (ja) * 1984-10-26 1995-06-28 三菱電機株式会社 半導体メモリ装置
JPH01278065A (ja) * 1988-04-28 1989-11-08 Hitachi Ltd 半導体記憶装置
JPH07120714B2 (ja) * 1989-05-23 1995-12-20 株式会社東芝 半導体記憶装置
JP2974252B2 (ja) * 1989-08-19 1999-11-10 富士通株式会社 半導体記憶装置
US5107459A (en) * 1990-04-20 1992-04-21 International Business Machines Corporation Stacked bit-line architecture for high density cross-point memory cell array

Also Published As

Publication number Publication date
DE59208890D1 (de) 1997-10-16
US5315542A (en) 1994-05-24
TW226484B (OSRAM) 1994-07-11
EP0545256A1 (de) 1993-06-09
JP3304146B2 (ja) 2002-07-22
JPH05243527A (ja) 1993-09-21
HK1000947A1 (en) 1998-05-08
DE4139719C1 (OSRAM) 1993-04-08
EP0545256B1 (de) 1997-09-10
KR930014952A (ko) 1993-07-23
KR100279485B1 (ko) 2001-03-02

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Legal Events

Date Code Title Description
REN Ceased due to non-payment of the annual fee