ATE156607T1 - Befehlspuffersystem für einen digitalen rechner - Google Patents

Befehlspuffersystem für einen digitalen rechner

Info

Publication number
ATE156607T1
ATE156607T1 AT89309274T AT89309274T ATE156607T1 AT E156607 T1 ATE156607 T1 AT E156607T1 AT 89309274 T AT89309274 T AT 89309274T AT 89309274 T AT89309274 T AT 89309274T AT E156607 T1 ATE156607 T1 AT E156607T1
Authority
AT
Austria
Prior art keywords
instruction
bytes
cache
digital computer
consumed
Prior art date
Application number
AT89309274T
Other languages
English (en)
Inventor
David B Fite
Ricky C Hetherington
Michael M Mckeon
Dwight P Manley
John E Murray
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE156607T1 publication Critical patent/ATE156607T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802Instruction prefetching
    • G06F9/3816Instruction alignment, e.g. cache line crossing

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Communication Control (AREA)
  • Executing Machine-Instructions (AREA)
AT89309274T 1989-02-03 1989-09-13 Befehlspuffersystem für einen digitalen rechner ATE156607T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/306,831 US5113515A (en) 1989-02-03 1989-02-03 Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer

Publications (1)

Publication Number Publication Date
ATE156607T1 true ATE156607T1 (de) 1997-08-15

Family

ID=23187060

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89309274T ATE156607T1 (de) 1989-02-03 1989-09-13 Befehlspuffersystem für einen digitalen rechner

Country Status (7)

Country Link
US (1) US5113515A (de)
EP (1) EP0380854B1 (de)
JP (1) JPH02208728A (de)
AT (1) ATE156607T1 (de)
AU (1) AU628527B2 (de)
CA (1) CA1323937C (de)
DE (1) DE68928236T2 (de)

Families Citing this family (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2505887B2 (ja) * 1989-07-14 1996-06-12 富士通株式会社 命令処理システム
JP2682217B2 (ja) * 1989-08-28 1997-11-26 日本電気株式会社 マイクロプロセッサ
JPH0395629A (ja) * 1989-09-08 1991-04-22 Fujitsu Ltd データ処理装置
EP0436341B1 (de) * 1990-01-02 1997-05-07 Motorola, Inc. Verfahren zum sequentiellen Vorabruf von 1-Wort-, 2-Wort oder 3-Wort-Befehlen
CA2045791A1 (en) * 1990-06-29 1991-12-30 Richard Lee Sites Branch performance in high speed processor
US5530941A (en) * 1990-08-06 1996-06-25 Ncr Corporation System and method for prefetching data from a main computer memory into a cache memory
US5493662A (en) * 1990-08-20 1996-02-20 Nec Corporation Apparatus for enabling exchange of data of different lengths between memories of at least two computer systems
EP0477598A2 (de) * 1990-09-26 1992-04-01 Siemens Aktiengesellschaft Befehlswerk für einen n Prozessorelemente aufweisenden Prozessor
JPH04340145A (ja) * 1991-05-17 1992-11-26 Nec Corp キャッシュメモリ装置
GB2263565B (en) * 1992-01-23 1995-08-30 Intel Corp Microprocessor with apparatus for parallel execution of instructions
SG45269A1 (en) * 1992-02-06 1998-01-16 Intel Corp End bit markers for instruction decode
GB2263985B (en) * 1992-02-06 1995-06-14 Intel Corp Two stage window multiplexors for deriving variable length instructions from a stream of instructions
DE69326066T2 (de) * 1992-03-25 2000-03-30 Zilog, Inc. Schnelle befehlsdekodierung in einem pipeline-prozessor
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
US5572682A (en) * 1992-04-03 1996-11-05 Cyrix Corporation Control logic for a sequential data buffer using byte read-enable lines to define and shift the access window
US5471628A (en) * 1992-06-30 1995-11-28 International Business Machines Corporation Multi-function permutation switch for rotating and manipulating an order of bits of an input data byte in either cyclic or non-cyclic mode
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
WO1994008287A1 (en) 1992-09-29 1994-04-14 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US5367657A (en) * 1992-10-01 1994-11-22 Intel Corporation Method and apparatus for efficient read prefetching of instruction code data in computer memory subsystems
JPH06222990A (ja) * 1992-10-16 1994-08-12 Fujitsu Ltd データ処理装置
CA2123442A1 (en) * 1993-09-20 1995-03-21 David S. Ray Multiple execution unit dispatch with instruction dependency
EP0651320B1 (de) * 1993-10-29 2001-05-23 Advanced Micro Devices, Inc. Superskalarbefehlsdekoder
US5689672A (en) * 1993-10-29 1997-11-18 Advanced Micro Devices, Inc. Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions
US5630082A (en) * 1993-10-29 1997-05-13 Advanced Micro Devices, Inc. Apparatus and method for instruction queue scanning
DE69434669T2 (de) * 1993-10-29 2006-10-12 Advanced Micro Devices, Inc., Sunnyvale Spekulative Befehlswarteschlange für Befehle mit variabler Byteslänge
JP3442118B2 (ja) * 1993-11-19 2003-09-02 富士通株式会社 バッファ回路
US5604909A (en) * 1993-12-15 1997-02-18 Silicon Graphics Computer Systems, Inc. Apparatus for processing instructions in a computing system
US5600806A (en) * 1994-03-01 1997-02-04 Intel Corporation Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer
US5608885A (en) * 1994-03-01 1997-03-04 Intel Corporation Method for handling instructions from a branch prior to instruction decoding in a computer which executes variable-length instructions
US5559975A (en) 1994-06-01 1996-09-24 Advanced Micro Devices, Inc. Program counter update mechanism
US5644752A (en) * 1994-06-29 1997-07-01 Exponential Technology, Inc. Combined store queue for a master-slave cache system
US5758116A (en) * 1994-09-30 1998-05-26 Intel Corporation Instruction length decoder for generating output length indicia to identity boundaries between variable length instructions
US5860096A (en) * 1994-10-17 1999-01-12 Hewlett-Packard Company Multi-level instruction cache for a computer
US5640526A (en) * 1994-12-21 1997-06-17 International Business Machines Corporation Superscaler instruction pipeline having boundary indentification logic for variable length instructions
US6525971B2 (en) * 1995-06-30 2003-02-25 Micron Technology, Inc. Distributed write data drivers for burst access memories
US5526320A (en) 1994-12-23 1996-06-11 Micron Technology Inc. Burst EDO memory device
US6006324A (en) 1995-01-25 1999-12-21 Advanced Micro Devices, Inc. High performance superscalar alignment unit
US5832249A (en) * 1995-01-25 1998-11-03 Advanced Micro Devices, Inc. High performance superscalar alignment unit
US5737550A (en) * 1995-03-28 1998-04-07 Advanced Micro Devices, Inc. Cache memory to processor bus interface and method thereof
US5991869A (en) * 1995-04-12 1999-11-23 Advanced Micro Devices, Inc. Superscalar microprocessor including a high speed instruction alignment unit
US5758114A (en) * 1995-04-12 1998-05-26 Advanced Micro Devices, Inc. High speed instruction alignment unit for aligning variable byte-length instructions according to predecode information in a superscalar microprocessor
US5822558A (en) * 1995-04-12 1998-10-13 Advanced Micro Devices, Inc. Method and apparatus for predecoding variable byte-length instructions within a superscalar microprocessor
US5680564A (en) * 1995-05-26 1997-10-21 National Semiconductor Corporation Pipelined processor with two tier prefetch buffer structure and method with bypass
US5809529A (en) * 1995-08-23 1998-09-15 International Business Machines Corporation Prefetching of committed instructions from a memory to an instruction cache
US5781789A (en) * 1995-08-31 1998-07-14 Advanced Micro Devices, Inc. Superscaler microprocessor employing a parallel mask decoder
US5809273A (en) * 1996-01-26 1998-09-15 Advanced Micro Devices, Inc. Instruction predecode and multiple instruction decode
US6093213A (en) * 1995-10-06 2000-07-25 Advanced Micro Devices, Inc. Flexible implementation of a system management mode (SMM) in a processor
US5926642A (en) * 1995-10-06 1999-07-20 Advanced Micro Devices, Inc. RISC86 instruction set
US5920713A (en) * 1995-10-06 1999-07-06 Advanced Micro Devices, Inc. Instruction decoder including two-way emulation code branching
US5819056A (en) * 1995-10-06 1998-10-06 Advanced Micro Devices, Inc. Instruction buffer organization method and system
US5794063A (en) * 1996-01-26 1998-08-11 Advanced Micro Devices, Inc. Instruction decoder including emulation using indirect specifiers
US5796974A (en) * 1995-11-07 1998-08-18 Advanced Micro Devices, Inc. Microcode patching apparatus and method
US5740392A (en) * 1995-12-27 1998-04-14 Intel Corporation Method and apparatus for fast decoding of 00H and OFH mapped instructions
US5829010A (en) * 1996-05-31 1998-10-27 Sun Microsystems, Inc. Apparatus and method to efficiently abort and restart a primary memory access
US6981126B1 (en) * 1996-07-03 2005-12-27 Micron Technology, Inc. Continuous interleave burst access
US5907702A (en) * 1997-03-28 1999-05-25 International Business Machines Corporation Method and apparatus for decreasing thread switch latency in a multithread processor
US5872946A (en) * 1997-06-11 1999-02-16 Advanced Micro Devices, Inc. Instruction alignment unit employing dual instruction queues for high frequency instruction dispatch
US6170050B1 (en) 1998-04-22 2001-01-02 Sun Microsystems, Inc. Length decoder for variable length data
US7117342B2 (en) 1998-12-03 2006-10-03 Sun Microsystems, Inc. Implicitly derived register specifiers in a processor
US6321325B1 (en) 1998-12-03 2001-11-20 Sun Microsystems, Inc. Dual in-line buffers for an instruction fetch unit
US7114056B2 (en) 1998-12-03 2006-09-26 Sun Microsystems, Inc. Local and global register partitioning in a VLIW processor
US6694423B1 (en) * 1999-05-26 2004-02-17 Infineon Technologies North America Corp. Prefetch streaming buffer
EP1150213B1 (de) * 2000-04-28 2012-01-25 TELEFONAKTIEBOLAGET LM ERICSSON (publ) Datenverarbeitungssystem und Verfahren
US7082516B1 (en) 2000-09-28 2006-07-25 Intel Corporation Aligning instructions using a variable width alignment engine having an intelligent buffer refill mechanism
EP1370950B1 (de) 2001-02-13 2017-12-27 NetApp, Inc. System und verfahren für die bereitstellung und das management von speicherung auf richtlinienbasis
US7203730B1 (en) 2001-02-13 2007-04-10 Network Appliance, Inc. Method and apparatus for identifying storage devices
US6738792B1 (en) 2001-03-09 2004-05-18 Advanced Micro Devices, Inc. Parallel mask generator
US7472231B1 (en) 2001-09-07 2008-12-30 Netapp, Inc. Storage area network data cache
US7032136B1 (en) 2001-09-07 2006-04-18 Network Appliance, Inc. Auto regression test for network-based storage virtualization system
US7032097B2 (en) * 2003-04-24 2006-04-18 International Business Machines Corporation Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache
US8806177B2 (en) * 2006-07-07 2014-08-12 International Business Machines Corporation Prefetch engine based translation prefetching
US11768689B2 (en) 2013-08-08 2023-09-26 Movidius Limited Apparatus, systems, and methods for low power computational imaging
US10001993B2 (en) 2013-08-08 2018-06-19 Linear Algebra Technologies Limited Variable-length instruction buffer management
US9672110B1 (en) 2015-09-22 2017-06-06 Amazon Technologies, Inc. Transmission time refinement in a storage system
US10254980B1 (en) 2015-09-22 2019-04-09 Amazon Technologies, Inc. Scheduling requests from data sources for efficient data decoding
US11204768B2 (en) 2019-11-06 2021-12-21 Onnivation Llc Instruction length based parallel instruction demarcator

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3771138A (en) * 1971-08-31 1973-11-06 Ibm Apparatus and method for serializing instructions from two independent instruction streams
US4521850A (en) * 1977-12-30 1985-06-04 Honeywell Information Systems Inc. Instruction buffer associated with a cache memory unit
US4236206A (en) * 1978-10-25 1980-11-25 Digital Equipment Corporation Central processor unit for executing instructions of variable length
JPS5927935B2 (ja) * 1980-02-29 1984-07-09 株式会社日立製作所 情報処理装置
CA1174370A (en) * 1980-05-19 1984-09-11 Hidekazu Matsumoto Data processing unit with pipelined operands
US4500958A (en) * 1982-04-21 1985-02-19 Digital Equipment Corporation Memory controller with data rotation arrangement
JPS59123053A (ja) * 1982-12-28 1984-07-16 Fujitsu Ltd 命令制御方式
US4626988A (en) * 1983-03-07 1986-12-02 International Business Machines Corporation Instruction fetch look-aside buffer with loop mode control
US4602368A (en) * 1983-04-15 1986-07-22 Honeywell Information Systems Inc. Dual validity bit arrays
US4635194A (en) * 1983-05-02 1987-01-06 International Business Machines Corporation Instruction buffer bypass apparatus
JPS6051948A (ja) * 1983-08-31 1985-03-23 Hitachi Ltd 情報処理装置
JPH0670773B2 (ja) * 1984-11-01 1994-09-07 富士通株式会社 先行制御方式
US4860192A (en) * 1985-02-22 1989-08-22 Intergraph Corporation Quadword boundary cache system
JP2539357B2 (ja) * 1985-03-15 1996-10-02 株式会社日立製作所 デ−タ処理装置
DE3752100T2 (de) * 1986-01-07 1997-12-11 Nippon Electric Co Befehlsvorabrufgerät mit einer Schaltung zum Prüfen der Vorhersage eines Verzweigungsbefehls vor seiner Ausführung
US4722050A (en) * 1986-03-27 1988-01-26 Hewlett-Packard Company Method and apparatus for facilitating instruction processing of a digital computer
EP0243879B1 (de) * 1986-04-23 1989-12-27 Siemens Aktiengesellschaft Verfahren und Anordnung zur Beschleunigung der Bereitstellung eines Befehles im Befehlsregister eines mikroprogrammgesteuerten Prozessors
JPH0810553B2 (ja) * 1986-06-13 1996-01-31 松下電器産業株式会社 記憶回路
JPS63163634A (ja) * 1986-12-26 1988-07-07 Hitachi Ltd 命令フエツチ方式
DE3802025C1 (de) * 1988-01-25 1989-07-20 Otto 7750 Konstanz De Mueller

Also Published As

Publication number Publication date
AU5394090A (en) 1991-12-19
DE68928236D1 (de) 1997-09-11
EP0380854A3 (de) 1993-01-07
CA1323937C (en) 1993-11-02
EP0380854B1 (de) 1997-08-06
DE68928236T2 (de) 1998-03-12
US5113515A (en) 1992-05-12
JPH02208728A (ja) 1990-08-20
EP0380854A2 (de) 1990-08-08
AU628527B2 (en) 1992-09-17

Similar Documents

Publication Publication Date Title
DE68928236D1 (de) Befehlspuffersystem für einen digitalen Rechner
EP0772131A3 (de) Verfahren und Gerät für die Unterstützung von virtuellen Datenübertragungskanälen
JP2004522215A (ja) プロセッサ・パイプライン内でのハードウェア命令翻訳
EP0366325A3 (de) Cachespeicherausfüllung mit veränderlicher Länge
US5467460A (en) M&A for minimizing data transfer to main memory from a writeback cache during a cache miss
US5835972A (en) Method and apparatus for optimization of data writes
KR960038620A (ko) 미참조 선인출 캐쉬(Non-Referenced Prefetch Cache)를 이용한 명령어 선인출 방법 및 그 회로
JPS5759253A (en) Branch instruction prefetch system
KR910005155A (ko) 마이크로 프로세서
KR920004280B1 (ko) 정보처리장치
JPS647145A (en) Software instruction endowing apparatus method for microprogramming system
JPS6462704A (en) High speed working system
JP2000148478A (ja) 中央処理装置及び中央処理システム
JPS54133854A (en) Pre-fetch buffer control system for channel command word
JPS57143640A (en) Data processing device
JPS61217834A (ja) デ−タ処理装置
JPS57138077A (en) Variable length string buffer device
JPS5940387A (ja) 仮想記憶制御方式
JPS6468868A (en) Buffer control system for bus adapter
JPS57197659A (en) Data processing device
JPS6421628A (en) Arithmetic processing unit
Jeremiassen A DSP with caches-a study of the GSM-EFR codec on the TI C6211
JPS5776604A (en) Numeric controller
JPS56169278A (en) Memory control system
KR100244429B1 (ko) 우수 및 기수 태그 어드레스 램구조를 갖는 캐시 메모리

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties