JPS56169278A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS56169278A
JPS56169278A JP7013580A JP7013580A JPS56169278A JP S56169278 A JPS56169278 A JP S56169278A JP 7013580 A JP7013580 A JP 7013580A JP 7013580 A JP7013580 A JP 7013580A JP S56169278 A JPS56169278 A JP S56169278A
Authority
JP
Japan
Prior art keywords
register
actual memory
memory area
bits
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7013580A
Other languages
Japanese (ja)
Inventor
Kenji Hayashi
Hiroo Miyadera
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7013580A priority Critical patent/JPS56169278A/en
Publication of JPS56169278A publication Critical patent/JPS56169278A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To execute access the entire actual memory area by minimizing the extent of the modification of software, by extending the capacity of an actual memory and by transferring data between an accessible area and the extended memory area through privileged instructions. CONSTITUTION:When a privileged instruction is generated and its operand is set in a register 1, the instruction code is set in an instruction code register 2 to turn off an address converting mechanism 8 via a decoder 3. Consequently, the low- order 24 bits in the register 1 are set in a register 7 as they are, and an actual memory area which is accessible by a CPU program, a channel, etc., is accessed. On the other hand, the output of the decoder 3 and an operand processing signal are ANDed to control a selector 5, and the high-order eight bits, etc., in the register 1 are supplied to the high-order 8 bits of the register 7 as they are to access the extended area of the actual memory. Thus, the extent of the modification of software is minimized and the actual memory area is entirely accessed without generating an overhead, etc.
JP7013580A 1980-05-28 1980-05-28 Memory control system Pending JPS56169278A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7013580A JPS56169278A (en) 1980-05-28 1980-05-28 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7013580A JPS56169278A (en) 1980-05-28 1980-05-28 Memory control system

Publications (1)

Publication Number Publication Date
JPS56169278A true JPS56169278A (en) 1981-12-25

Family

ID=13422813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7013580A Pending JPS56169278A (en) 1980-05-28 1980-05-28 Memory control system

Country Status (1)

Country Link
JP (1) JPS56169278A (en)

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