WO1996008767A2

WO1996008767A2 - Microcontroller system with a multiple-register stacking instruction

Info

Publication number: WO1996008767A2
Application number: PCT/IB1995/000677
Authority: WO
Inventors: Farrell Ostler; Neil Birns; Ori Mizrahi-Shalom
Original assignee: Philips Electronics N.V.; Philips Norden Ab
Priority date: 1994-09-16
Filing date: 1995-08-22
Publication date: 1996-03-21
Also published as: WO1996008767A3

Abstract

A microcontroller system transfers data between a memory stack and a plurality of general-purpose registers listed in an instruction in a single instruction cycle. An address generation circuit automatically generates register addresses only for those registers involved in the transfer. The stack pointer is modified or updated for each transfer.

Description

MICROCONTROLLER SYSTEM WITH A MULTIPLE-REGISTER STACKING INSTRUCTION

FIELD OF THE INVENTION

The present invention relates to a microcontroller comprising a multitude of registers and having at its disposal a stack memory. The microcontroller is operative to effect a transfer of data between the registers and the stack memory under control of an instruction. ^~

BACKGROUND ART

The operation of a microcontroller, in which multiple procedures or subroutines are performed, frequently requires the transfer of data between a general-purpose register and a stack memory of the microcontroller. This frequently performed operation and the instructions associated with the operation need to be fast and efficient in use of memory space. Conventional push/pop register instructions allow the data for a single register to be moved between the register and stack. When the microcontroller includes several general- purpose registers the operation of transferring between the plural registers and the stack requires plural instructions, each requiring memory space and a complete instruction execution cycle.

OBJECT OF THE INVENTION

What is needed is an instruction and system for performing a transfer instruction that transfers between plural general-purpose registers and the stack in a single instruction cycle. It is, therefore, an object of the present invention to provide a system for performing transfer of data between multiple general-purpose registers and a stack. It is another object of the present invention to provide an instruction which will perform the transfer in a single instruction cycle. It is also an object of the present invention to improve speed and memory utilization for transfers of the data between registers and a stack.

SUMMARY OF THE INVENTION

The above objects are attained by the microcontroller as specified in the preamble and characterized in that the instruction comprises an indication of a plurality of respective ones of the registers involved in the transfer, and in that the microcontroller comprises an address generator responsive to the indication and operative to generate a plurality of respective addresses for the respective ones of the registers.

The microcontroller system performs a transfer of data between plural general-purpose registers and a stack in a single instruction cycle. The address generator automatically generates addresses only for the registers designated in the instruction. Each time an address is generated the stack pointer is updated to point to the next location in the stack.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is explained in further detail and by way of example with reference to the accompanying drawing, wherein:

Figures 1A and IB depict a format of a push register list instruction according to d e present invention;

Figures 2A and 2B depict a format of a pop register list instruction according to the present invention;

Figure 3 illustrates the hardware architecture of the present invention; Figure 4 depicts a register address generation circuit 90; Figures 5-8 show organization of microcontroller memory space according to the present invention;

Figures 9 and 10 depict stack operations; Figure 11 illustrates a segment register; and

Figures 12 and 13 are flow charts of the microcode program controlled steps of the push/pop register list instructions.

Throughout the drawing, like reference signs indicate similar or corresponding features.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention includes push and pop instructions having mnemonics of PUSH Rlist, PUSHU Rlist, POP Rlist and POPU Rust. PUSH indicates the operation of pushing data onto a stack. POP indicates the operation of popping data off a stack. The suffix "U" indicates that a user stack rather than the current stack is involved. Rlist is a list of general-purpose registers, preferably up to eight, which include or will include the transferred data. These instructions allow data to be transferred between any combination of the registers and the current stack or the user stack. The push instruction pushes the contents of the specified registers onto the stack and the pop instruction pops the data for the registers off the stack and loads the registers.

The encoded formats of the two byte push instruction 2 and push user instruction 3 are depicted in Figures 1A and IB. Each instruction includes a first byte 4, which includes an operation code (opcode) represented by bits at locations seven, five, four two, one and zero, a bit (H/L) 5 at location six indicating whether the upper or lower half of the register file is involved, and a data size (DS) bit 6 at location three indicating whether a word transfer or a byte transfer is to occur. The second byte 7 of the instruction is a binary list of the registers involved in the transfer. For example, the 00000010 list indicates general purpose register number one (Rl) is involved in the transfer and 01000010 indicates registers R6 and Rl are involved in the transfer. The encoded formats of the corresponding pop instruction 8 and pop user instruction 9 are illustrated in Figures 2A and 2B. These instructions include the same fields as the instructions of Figures 1A and IB.

The architecture of the microcontroller system 10 of the present invention is illustrated in figure 3. This system 10 includes a single chip microcontroller 12 that performs 16 bit arithmetic operations and includes internal instruction and data storage. The microcontroller 12 supports external devices 14 and 16 and, through 24 bit external address capability, supports sixteen megabytes of external instruction storage 18 and sixteen megabytes of external data storage 20. The microcontroller 12 includes a bus interface unit 22 which communicates with the external memories 18 and 20 over an external bi-directional address and data bus 24. The microcontroller 12 communicates with the external devices 14 and 16 through I/O ports 26 - 28 which are addressable as special function registers (SFR) 40. The ports 26-28 as well as other special function registers are addressable over an internal peripheral bus 42 through the bus interface unit 22. The data memory 20 can also be accessed as off-chip memory mapped I/O through the I/O ports 26 - 28. The on-chip special function registers 40, some of which are bit addressable, also include a program status word (PS W) register 44 coupled to an interruption control unit 84 communicating with the external devices as well as the ALU the execution unit 70 and decoder unit 74 for flag and general control, an interrupt register 46, timer registers 50 and a system configuration register (SCR) 54 containing system configuration bits. The program status word register is addressable over the peripheral bus 42 for general register operations and is also addressable over a connection to the internal bus 86 for other execution related operations. The bus interface unit 22 isolates the peripheral special function registers 40 from the microcontroller core 60. The core 60 includes a microcode programmable execution unit 70 which controls execution of instructions by an ALU 72 and the other units. The instructions decoded by a decoder unit 74 are fetched from an internal EPROM 76, which is part of the instruction memory space, or from the external instruction memory 18 by a fetch unit 78. Static RAM 80 is available for data storage and is also part of the data memory space. The general-purpose registers R0- R7 are found in a register file 82 and are also available for instruction and data storage. To implement the push/pop register list instruction of the present invention the execution unit 70 includes a special address generation circuit 90, as illustrated in Figure 4. This circuit 90 generates a memory address for each register content to be transferred, based on the list of registers found in the second byte 7 of the instruction. Each time a register address is generated, the microcontroller 12 also increments/decrements, as appropriate, a stack pointer (SP) through the ALU 72, either the current stack pointer or the user stack pointer.

The address generation circuit 90 (figure 4) receives from the execution unit 70 the necessary start (EX STX) control signal and other control signals designated with prefix "EX", and from the decoder unit 74 the control signals designated with prefix "DC". The execution unit 70 causes a register 92 to be set at the following rising clock edge. This allows the initial register list, from the second byte 7 of the instruction carried by die signal DC.DATA1, to be passed to a priority encoder 94 through an eight-bit wide AND-circuit 96. The priority encoder 94 then searches for the first bit set on the list that indicates die first register and d e register address is encoded by an address encoder 98 using the high/low and size signals from the decoder unit 74. The search direction, from the left or right, in byte 7 depends on the opcode received from the decoder unit 74. The order of search is from the most significant bit to the least significant bit for PUSH, but in the opposite direction for POP. The output address is then sent to the register file 82 for register addressing. The information of the bit position for the first register is fed back through the circuit 100 and stored in the register 92. The purpose of this register 92 is to save the bit positions of the registers that have already been accessed. The register 92 output is enabled when die signal EX.REGMUX from the execution unit 70 is asserted. The first register bit on die list will be cleared and die second register bit becomes the first bit set on the list. The register 92 contents is again selected by die priority encoder 94 and encoded by d e address encoder 98 and sent to address the register file 82. The new selected bit position is fed back and stored in the register 92. When the next EX.REGMUX is asserted, both d e first and second set bits on die list will be cleared by die register 92 output. The third register bit is then ready to be selected. This cyclic operation continues until all the registers on the list are accessed. A signal RLEOI, which indicates the end of this instruction, is generated when d e circuit 94 detects that there is only one bit set on the remaining list and die current cycle is the next to the last cycle as indicated by die signal EX_IB_REG from the execution unit 70. The generation of RLEOI is further qualified by two signals: PUSHPOPRL and SQUELCH.. The signal PUSHPOPRL from the decoder unit 94 indicates die current instruction is the PUSH/POP Rlist instruction. The purpose of this signal is to prevent RLEOI from being generated during anotiier instruction. The signal SQUELCH indicates that the execution unit 70 is in a wait state, and is used to stall the instruction and properly resume operation at the end of die wait state.

The circuit of figure 4 has a long delay path from register 92 to die generation of output address by die encoder 98. The allowable time limit for this delay path during the POP Rlist instruction is normally one clock cycle. The architecture of figure 4 is sufficient for a design having an operating frequency of 20 MHz. For a microcontroller that requires a shorter clock period, a register can be placed immediately after the priority encoder 94 but before the feedback path. The enable signal for the register 92 is then moved to die new register. The delay of die address output is then only die delay of d e address encoder 98 which should be well within one clock cycle even for faster microcontrollers.

The microcontroller 12 includes a memory organization as illustrated in figures 5, 6, 7 and 8. Figure 5 illustrates d e organization into pages. Figure 6 depicts d e organization of a page in more detail. Figure 7 depicts the register file in more detail and figure 8 depicts die SFR space 40. As previously discussed, die microcontroller 12 has separate address spaces for instruction memory and data memory. The logical separation of program and data memory allows faster access of data memory which can be manipulated by a 16-bit ALU. All registers and on-chip memory are accessible (addressable) as bytes and/or words. Some dedicated data memory areas (SFR, RAM, and Register File) may also be accessed as bits (see figure 5). The term "data memory" refers to on-chip RAM 80, off-chip RAM 18 or off-chip memory mapped I/O.

The data memory space 118 is segmented into 64K byte pages 120, accessed via indirect addressing modes (die first IK block of each page is also- directly addressable). Preferably, 512 bytes of data memory are implemented as on-chip RAM 80, but there is no architectural limitation on die minimum or maximum data memory that may be on-chip. The microcontroller 12 architecture allows up to IK of direct addressing space 122 for data memory per page. There are four banks of registers RO through R7 (see figures 6 and 7) starting at address 0 in die on-chip RAM (in die register file 82) and going up to address IF hexadecimal. One of die four banks is selected as the active bank by two bits in die PSW register 44. The selected bank appears as the general-purpose registers and these are the registers whose contents are transferred in die present invention. When off-chip RAM 20 is mapped outside on-chip RAM 80 range, under microcode program control, any access to this address space will automatically fetch off-chip data, giving the microcontroller 12 a linear address space from 0 to 16 megabytes.

The bottom IK bytes 122 of every data memory segment, under microcode control, is directly addressable data space. This addressing mode contains the low 16 bits of the data address within the instruction. A segment register (SR) associated with the direct address space, which forms the upper byte of the 24-bit address, is always d e data segment (DS) register. This built-in protection mechanism prevents user level code from switching between direct address spaces in different segments. The 32 bytes 124 of this space at addresses 20 to 3F hex form the standard bit addressable RAM space (256 bits). In the native mode of d e microcontroller 12, all registers are confined to the register file 82 only and do not have any memory association. The direct address space in native mode thus starts from address 0 in data memory. However, the microcontroller internally addresses d e registers R0-R7 using a memory address.

The special function registers 40, which include d e segment registers used for addressing, are in the IK direct address block 139 from address 400 to 7FF hex (see figure 8). The first half 140 of this block is die on-chip SFR space. This area of SFRs is used to access SFR mapped registers, and control and data registers for on-chip peripherals and I/Os. The rest 142 is reserved for off-chip SFRs.

The SFR 139 space is always directly addressed. Although die SFR 139 space uses die same addressing mode as the IK of directed addressed data space, it is logically a separate space and should not be thought of as overlapping the indirect data space (See figures 7 and 8). The lowest 64 bytes in die SFR address space are the only bit addressable SFR locations. The architecture supports RAM space segmentation into 256 pages each 64K size. Direct addresses are limited to IK of each page of die segmented memory. A 24-bit direct address is formed by DS (upper 8-bits) and a 16-bit address of this IK direct space. Indirect addresses are formed by d e use of a 16-bit pointer register (from die register file) appended to the 8-bit data segment (DS) register or the extra segment (ES) register. This segmentation allows for streamlining the encoding and execution of memory access instructions as well as providing simple segregation of processes running under a multi-tasking system. Word registers RO - R7 are also used as address pointers during indirect and indirect-offset addressing modes. Word register R7 is particularly used as die stack pointer, either die system stack pointer or the current user stack pointer depending on whether the microcontroller 12 is in the system mode or user mode. The stack pointer is used during the transfer between the stack and registers of the present invention.

Memory in the system 10 is addressed in units of bytes, each byte consisting of 8-bits. A word is a 16-bit value, consisting of two contiguous bytes. The storage order for data in the microcontroller 12 is "Litde Endian" such that the lower byte of a word is stored at die lower address and die higher byte is stored at the next higher address. Word values are stored in RAM, registers, and word addressable SFRs with die least significant byte at the even address (die address that is specific in die code or in the pointer register) and die most significant byte at the next consecutive odd address (one greater than the address of the LSB). Under microcode program control it is not allowed in die microcontroller 12 architecture to place a word in memory such that its LSB is at an odd address. All 16-bit word addressable locations could be accessed as both bytes and words. It is therefore possible, for example, to increment only the low-order half, or to modify only the high-order byte of a word in data memory, by making appropriate references to their memory-mapped addresses. If a word access is made from an odd address, die access will always be from an even-boundary location which is one less than the specified odd address. The external bus 24 can be configured in 8 or 16-bit mode, selected during chip reset. Depending on die mode of operation selected, all 16-bit external data accesses could be strictiy words (16-bit mode) or bytes from consecutive memory locations (8-bit mode). An external word fetch in 8-bit mode results in 2 separate byte accesses (the result is d e same in a single word access if the data is on-chip).

The microcontroller 12 includes a number of different addressing modes. The basic addressing modes include a register mode which addresses die register file only. A direct addressing mode is included where the entire data address is included widiin the instruction. This mode can address die bottom IK of data memory in each data segment (DS) (which includes RO through R7 of all 4 banks of d e register file on segment 0). The 24-bit address includes 8-bits of d e DS register (MSB) and a 16-bit address from die IK direct address range in any page. A SFR addressing mode addresses die IK SFR space. Although encoded into the same instruction field as the direct addressing described above, this is actually a separate space. In indirect addressing mode die low order 16 bits of the address are taken from any word register in the register file 82. The upper 8 bits are taken from either de data segment (DS) or extra segment (ES) SFR. This mode can address an entire 64k data segment, which may be anywhere in the 16MB address space, depending on die segment register contents. Under microcode program control many instructions witii indirect addressing allow an option to automatically increment die specified address register after the memory access, such as in d e present invention with respect to the stack point register R7. The register will be incremented according to d e data size: by 1 for a byte operand and by 2 for a word operand. An indirect-offset addressing mode is provided and uses die sum of an address register and an immediate offset value as die effective address of d e operand. The offset can be either an 8-bit signed value witii a range of +127 to -128 bytes, or a 16-bit signed value witii a range of +32767 to -32768 bytes. This potentially provides access to an entire data segment witii this mode. In die immediate addressing mode a constant value is stored within the instruction. Depending on die instruction accessed, die value may be 4-bits, 8-bits, or 16-bits in size.

In die microcontroller 12 the stack 150 as illustrated figures 9 and 10 grows downward from high to low addresses. The microcontroller 12 architecture supports a UFO (last-in-first-out) stack. At any given time, the stack pointer (SP), which is located in register R7, points to die last word pushed onto the stack. When new data is pushed, die stack pointer is decremented prior to writing to memory. When data is popped from the stack, the stack pointer is incremented after the data is read from memory. Since the microcontroller 12 stores data in die memory MSB first, the stack pointer always points to die LSB of a word written onto the stack. This matches die way a general purpose pointer accesses data from memory, so that the stack pointer may be copied to a general-purpose pointer register and used to access parameters that reside on die stack. Stack operations are facilitated by die two stack pointers, a user stack pointer (USP) and a system stack pointer (SSP) located in the registers of register file 82. The 16-bit stack pointers are customary top- of-stack pointers, addressing die uppermost datum on die push-down stack. It is referenced implicidy by push and pop operations, such as in the invention, as well as subroutine calls, and interrupt operations. The stack is always word aligned. Any push to die stack (byte/word) decrements die stack pointer by two (SP = SP-2) and any pop (byte/word) increments the stack pointer by two (SP = SP+2). This stack alignment thus ensures that all stack operations are on word boundaries (an even address), eliminating alignment issues and reducing die interrupt latency time during pushes and pops as well as for other 16-bit or larger stack operations. In die microcontroller 12, a push or pop stack operation does not update any status flag in the PSW. The user stack pointer (USP) register may be written as well as read using its register address, and by doing so die user stack may be placed anywhere in the segment where the stack resides. For d e system stack, this is always page 0 (a 16-bit address only), while the user stack space is identified by die data segment (DS) register. The stack may be as deep as the available memory on its memory page permits. The bottom limit of the stack in all pages is set to address 80 hex, i.e a microcode program controlled stack overflow trap occurs at that address. However, there is an extra 64 byte space below this stack bottom limit, out of which 22 bytes could be reserved to accommodate die worst case scenario of having 16 bytes for a multiple register (RO-R15) PUSH and an additional 6 bytes to store the stack frame for the overflow trap. At power-on reset, the SP is always initialized to 100 hex, i.e., one byte above minimum on-chip RAM space (256 bytes). Since SP is pre-decremented prior to a push, die word-aligned stack grows from FE downwards.

The microcontroller provides a two-level user/supervisor protection mechanism. These are the user or application mode and d e system or supervisor mode. In a multitasking environment, tasks in a supervisor level are protected from tasks in the application level. As noted previously, the microcontroller has two stack pointers (in the register file) called d e system stack pointer (SSP) and die user stack pointer (USP). In multitasking systems one stack pointer is used for the supervisory system and another for the currently active task. This helps in the protection mechanism by providing isolation of system software from user applications. If die size of the user stack for a particular application exceeds die space available in die on-chip RAM 80, or on-chip RAM 80 is needed for other time-critical purposes (since on-chip RAM 80 is accessed more quickly than off-chip memory 20), the user stack can be put off-chip and die interrupt stack (using die System SP) may be put in on-chip RAM 80. The system stack is always forced to data memory segment 0 (the first 64K bytes of data memory), while the user stack is located on die segment chosen by the DS (data segment) register. The two stack pointers share the same register address. The stack pointer that will be used at any given time, and that will "appear" in the register file, is determined by die system mode bit (SM) in die program status word (PSW) register 44. The microcontroller 12 stack is automatically set via microcode program control to use the user stack pointer (USP) whenever code is executing in die user mode and die system stack pointer (SSP) when code is executing in the system mode. Shadowing d e two SPs allows the same procedures to run in both system and user modes, as in a compiler run-time package. The microcontroller 12 begins operation after reset in the system mode using the system stack for pushes, pops, subroutine return addresses, and interrupt return addresses. In die system mode, a program may set up die USP and activate a routine that runs in tiiat mode. In the user mode, all pushes, pops, and subroutine return addresses use die application or user stack. Interrupts, however, will always use the system stack. A user mode program cannot modify the system stack pointer (SSP) and the data segment (DS) register, but can only read diem. However, both read and write on the extra segment register (ES) is allowed in die user mode. To request use of a different stack or data segment, a user mode program has to call a system mode routine via a TRAP instruction, or signal the system code in some other fashion. A system mode routine can manipulate die segment register (or not, if it decides that the application code should not have access to that area) and return to die application code. In this manner, application code tasks may be easily limited to using certain areas of the total data space. System mode code can use die user stack by copying the user stack pointer (USP) to anotiier pointer register and access d e user stack through die data segment register (DS), or the system mode code can use die PUSHU and POPU instructions to directly access die user stack. Using these mechanisms, the system program can prepare the user stack for a task, or easily access parameters on die user stack when it is called by a TRAP instruction for some system service. Complete programs generally consist of many different modules or segments. However, at any given time during program execution, only a small subset of a program's segments are actually in use. Generally, this subset will include code and data. The microcontroller 12 architecture takes advantage of this by providing mechanisms to support direct access to die working set of a program's execution environment and access to additional segments on demand. At any given instant, two segments of memory are immediately accessible to an executing program. These are the data segment, where the stack and local variables reside, and die extra segment, which may be used to read remote data structures. Restricting die addressability of a software modules helps gaining complete control of system resources for efficient, reliable operation in a multi-tasking environment. A current working data segment 160 in the microcontroller includes a 16-bit address (pointer) 162 and an 8-bit segment 164 as illustrated in figure 11. The 8-bit segment registers DS or ES holds d e offset which is used to identify tins current segment. These segment registers are used as extension to 16-bit pointer registers and stack pointers to allow data to be accessed through the entire 16 megabyte address range. There are eight 16-bit registers in the register file. Of those eight, one (R7) is reserved for the stack pointer and die otiier seven (R0-R6) may be used as general-purpose pointer registers to access the different segments of die memory. A "byte" register in the SFR space contains bits that are associated witii each of the seven general-purpose pointer registers (i.e not the SP) that selects neidier DS or ES as die source for the most significant 8-bit for the 24-bit address. This register is called d e segment select register 166 or SSEL (see figure 11). The power-on state of the SSEL bits is reset, i.e, it defaults to die DS register. The stack pointer does not have a bit in SSEL 166 to determine its segment because it is always segment 0 in system mode and DS in user mode. This is true regardless of die mediod of access (e.g. PUSH, POP, or indirect register addressing). Segment registers are not automatically incremented or decremented along witii their associated pointer registers, but must be altered explicitly by instructions. Writes to the data segment register (manipulating die offset in DS) and writes through die extra segment register (manipulating the memory pointed to by ES:Rn) are programmably controlled. However, in user mode, writes through DS, writes to ES, and reads through ES are allowed. The operation, under microcode program control, of pushing the contents of designated registers on the stack starts, once the instruction is decoded by d e decode unit 74 and presented to die execution unit 70, by loading 200 die ALU 72 with die contents of the stack pointer register R7, as illustrated in figure 12. The ALU 72 decrements 202 die stack pointer. Using the stack pointer (SP) the stack address is generated 204. Next, die address generation circuit 90, based on die register list provided in the instruction, generates 206 the address of a register involved in die move. The contents of the addressed register are read 208 by the fetch unit 78. The fetched data is then stored 210 at die stack pointer address. If die end of register transfer signal has issued, die transfer is complete 212 and d e output of die ALU 72 is stored 214 back in die stack pointer register R7, ending die push register list instruction execution. If not die cycle continues with die register address generation circuit 90 generating addresses only for the registers involved in die transfer. That is, if only two registers are involved in the transfer die loop of figure 12 is only executed twice. In this way the transfer finishes at die earliest possible point and within a single cycle of the push register list instruction. The operations for performing d e pop register list instruction are illustrated in figure 13. The operation begins with loading 220 die ALU 72 with the stack pointer (SP). The stack address is then generated 222 followed by generation 224 of the register address. The data to be moved is then fetched 226 from the stack and stored 228 in the designated register. The contents (SP) of the ALU 72 are incremented 230 and a determination 232 is made as to whether the end of die list has been reached. If not, d e cycle continues and if so die stack pointer is stored 234.

The instructions of the present invention conserves on memory space compared to die prior art and performs multiple register stack operations faster than the prior art.

Claims

CLAIM?:

1. A microcontroller (10) comprising a multitude of registers (82; R0-R7), and having at its disposal a stack memory; and being operative to effect a transfer of data between the registers and die stack memory under control of an instruction; characterized, in that:

- the instruction comprises an indication (Rlist) of a plurality of respective ones of the registers involved in die transfer;

- the microcontroller comprises an address generator (90) responsive to die indication and operative to generate a plurality of respective addresses for the respective ones of die registers under control of the indication;

- die microcontroller is operative to update a stack pointer to point to a next location in die stack memory each time the address generator generates a next one of the addresses.

2. The microcontroller of claim 1, wherein die address generator comprises:

- a generator input (DC_DATA1) for receiving the indication; - a priority decoder (94) coupled to the generator input and operative to determine the respective ones of die registers referred to in the indication;

- an address encoder (98) coupled to die priority decoder and operative to generate a respective address for the respective register under control of die priority decoder.

3. The microcontroller of claim 2, wherein the address generator comprises means (92, 96, 100) operative to store a list of the respective registers for which a respective transfer has occurred and operative to control supply of die indication to the priority decoder.

4. A microcontroller (10) responsive to an instruction, characterized in that the instruction comprises:

- an operation code field (4) designating a transfer of data between a plurality of registers and a memory stack;

- a register list field (7) associated witii the operation code field and identifying at least two of the registers involved in die transfer.