JPS59112400U - memory device - Google Patents
memory deviceInfo
- Publication number
- JPS59112400U JPS59112400U JP18858083U JP18858083U JPS59112400U JP S59112400 U JPS59112400 U JP S59112400U JP 18858083 U JP18858083 U JP 18858083U JP 18858083 U JP18858083 U JP 18858083U JP S59112400 U JPS59112400 U JP S59112400U
- Authority
- JP
- Japan
- Prior art keywords
- data
- memory
- address
- storing
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はＩＤカードデータの読出し時のデータ形式を示
す図、第２図は第１図に示されるデータをメモリに格納
する場合の従来装置による格納方法を説明するための説
明図、第３図は本考案の一実施例としてのメモリ装置の
ブロック線図、第４図は第３図装置におけるデータメモ
リ及びパリティメモリの構成を示す構成図である。
１０・・・・・・記憶装置、１１・・・・・・直列／並
列変換回路、１７・・・・・・データメモリ、１８・・
・・・・パリティメモリ、１９．２０．２１．２２．２
３・・・・・・メモリチップ、Ａ１． Ａ２・・・、
Ａｎ・・・・・・アドレス、Ｄｌ、 Ｄ２゜・・・・・
・データビット、Ｐ□、Ｐ２．・・・・・・パリティビ
ット、Ｓ□・・・・・・読出し信号、Ｓ、・・・・・・
並列データビット信号、Ｓ５・・・・・・パリティビッ
ト信号、Ｗ１＊ Ｗａｓ・・・・・・文字データ。FIG. 1 is a diagram showing the data format when reading ID card data, FIG. 2 is an explanatory diagram for explaining a storage method using a conventional device when storing the data shown in FIG. 1 in a memory, and FIG. The figure is a block diagram of a memory device as an embodiment of the present invention, and FIG. 4 is a configuration diagram showing the configuration of a data memory and a parity memory in the device of FIG. 3. 10...Storage device, 11...Serial/parallel conversion circuit, 17...Data memory, 18...
...Parity memory, 19.20.21.22.2
3...Memory chip, A1. A2...,
An...Address, Dl, D2゜...
・Data bit, P□, P2.・・・・・・Parity bit, S□・・・Read signal, S, ・・・・・・
Parallel data bit signal, S5... Parity bit signal, W1* Was... Character data.
Claims (1)
゛ ビットのパリティビットとから成る文字データを、
読出し時には４Ｎ（Ｎは正の整数）個分一度に読み出せ
るように格納するメモリ装置であって、１アドレスの容
量が４ｎ ｘ ４Ｎビツトの第１メモリと、１アドレス
の容量が４Ｎビツトの第２メモリと、４Ｎ個の文字デニ
タを１単位データとし、各単位データ毎に単位データ中
のデータビット部分を前記第１メモリの１つのアドレス
に格納する手段と、該単位データ中のパリティビット部
分を前記１つのアドレイスに対応する前記第２メモリの
アドレスに格納する手段とを備えたことを特徴とするメ
モリ装置。 パ1 4n (n is a positive integer) data bits and 1
Character data consisting of ゛ bit parity bit,
This is a memory device that stores 4N (N is a positive integer) pieces of data so that they can be read at once during reading, and includes a first memory with a capacity of 4n x 4N bits per address, and a second memory with a capacity of 4N bits per address. 2 memories, means for storing 4N character data as one unit data, and storing a data bit part in the unit data for each unit data in one address of the first memory, and a parity bit part in the unit data. a memory device comprising: means for storing the second memory at an address in the second memory corresponding to the one address. pa
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18858083U JPS59112400U (en) | 1983-12-08 | 1983-12-08 | memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18858083U JPS59112400U (en) | 1983-12-08 | 1983-12-08 | memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59112400U true JPS59112400U (en) | 1984-07-28 |
| JPS6117480Y2 JPS6117480Y2 (en) | 1986-05-28 |
Family
ID=30406790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18858083U Granted JPS59112400U (en) | 1983-12-08 | 1983-12-08 | memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59112400U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9514283B2 (en) | 2008-07-09 | 2016-12-06 | Baxter International Inc. | Dialysis system having inventory management including online dextrose mixing |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50130331A (en) * | 1974-04-01 | 1975-10-15 | ||
| JPS5392633A (en) * | 1977-01-25 | 1978-08-14 | Mitsubishi Electric Corp | Read only memory unit |
-
1983
- 1983-12-08 JP JP18858083U patent/JPS59112400U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50130331A (en) * | 1974-04-01 | 1975-10-15 | ||
| JPS5392633A (en) * | 1977-01-25 | 1978-08-14 | Mitsubishi Electric Corp | Read only memory unit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6117480Y2 (en) | 1986-05-28 |
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