JPS60144148U - Storage device - Google Patents
Storage deviceInfo
- Publication number
- JPS60144148U JPS60144148U JP2854284U JP2854284U JPS60144148U JP S60144148 U JPS60144148 U JP S60144148U JP 2854284 U JP2854284 U JP 2854284U JP 2854284 U JP2854284 U JP 2854284U JP S60144148 U JPS60144148 U JP S60144148U
- Authority
- JP
- Japan
- Prior art keywords
- error
- information
- storage device
- storage element
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の記憶装置の構成例を示すブロック図、第
２図は本考案の実施例を示すブロック図である。
１・・・・・・制御回路、２・・・・・・データレジス
タ、３・・・・・・データ転送バッファ、７・・・・・
・誤り判断回路、８・・・・・・エラースティタスレジ
スタ（ＥＳＲ）、９． １０・・・・・・フリップフロ
ップ、１１・・曲゛オアケート、 □１２・・・・・
・アンドゲート。 −FIG. 1 is a block diagram showing an example of the configuration of a conventional storage device, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1... Control circuit, 2... Data register, 3... Data transfer buffer, 7...
-Error judgment circuit, 8...Error status register (ESR), 9. 10...Flip-flop, 11...Song or Kate, □12...
・And gate. −
Claims (1)
構成する記憶素子から読出される情報にエラーが生じた
場合、その不良記憶素子の位置判断を行なうための情報
が保持され、必要時ＣＰＵにより、その内容が繰出され
るレジスタと、゛上記記憶素子から得られる読出しデー
タの誤り発生の有無−を調べる誤り判断回路と、該判断
結果を保持し、ＣＰＵによる上記レジスタ情報の読取り
後にリセットされる誤り状態保持回路とを備え、−該保
持口２ 路が示す状態情報に従かい上記レジスタ情報
を出力することを特徴とする記憶装置。 −□' In a storage device with an error abort function, if an error occurs in the information read from a storage element constituting the storage device, the information for determining the location of the defective storage element is retained and can be retrieved by the CPU when necessary. , a register whose contents are read out, an error judgment circuit that checks whether or not an error has occurred in the read data obtained from the storage element, and holds the judgment result and is reset after the CPU reads the register information. an error state holding circuit, and outputs the register information according to the state information indicated by the holding port 2 path. −□
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2854284U JPS60144148U (en) | 1984-02-29 | 1984-02-29 | Storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2854284U JPS60144148U (en) | 1984-02-29 | 1984-02-29 | Storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60144148U true JPS60144148U (en) | 1985-09-25 |
Family
ID=30526515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2854284U Pending JPS60144148U (en) | 1984-02-29 | 1984-02-29 | Storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60144148U (en) |
-
1984
- 1984-02-29 JP JP2854284U patent/JPS60144148U/en active Pending
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