JPS60164258U - data transfer control device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of a conventional device, Fig. 2 is an electrical configuration diagram showing an embodiment of the present invention, Fig. 3 is a diagram showing a specific configuration of a data transfer control circuit, and Fig. 4 is a diagram showing each part. 5 is a timing chart showing operation waveforms. 1.2...CPU, 3,11...Memory, 4゜13...Data transfer control circuit, 5,6
...Data buffer, 12...Clock generator, 14...Address counter, 21,
22.24-27...Flip-flop, 23
...Inverter, 28.29...OR gate, 30,31...One-shot circuit.

Claims (2)

[Scope of utility model registration request] (1) When transferring data between a first CPU and a second CPU, a memory provided between these CPUs that can write and read data, and an address that gives an address to the memory. a counter, a clock generator that generates a reference clock, and receives an output of the clock generator and a multi-est signal from the first and second CPUs, and controls writing and reading of data to the memory; and a data transfer control circuit that provides a count control signal to the at/res counter and a first and second CPU haircut signal, and when the first and second CPUs receive the first signal simultaneously, A data transfer control device characterized in that these request signals are distributed according to the rising and falling edges of a generator's output clock. (2) The data transfer control device according to claim 1, wherein a FIFOH type RAM is used as the memory.