JPS59155639U - memory selection device - Google Patents
memory selection deviceInfo
- Publication number
- JPS59155639U JPS59155639U JP4763583U JP4763583U JPS59155639U JP S59155639 U JPS59155639 U JP S59155639U JP 4763583 U JP4763583 U JP 4763583U JP 4763583 U JP4763583 U JP 4763583U JP S59155639 U JPS59155639 U JP S59155639U
- Authority
- JP
- Japan
- Prior art keywords
- data
- memory selection
- selection device
- bus
- memories
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来におけるメモリ選択装置の構成図、第２図
は第１図に示すメモリバンクにおけるメモリ空間を説明
するための図、第３図は本考案に係るメモリ選択装置の
一実施例を示す構成図、第４図ａ、 ｂは本装置にお
けるメモリのメモリ空間を説明するための図である。
２０・・・中央処理装置（ＣＰＵ）、２１・・・ラッチ
回路、２２・・・アドレス変換部、２３’、２４．２５
・・・デコーダ、Ｍ１〜Ｍ２４・・・メモリ、ＤＢ・・
・データバス、ＡＢ川子アドレスバスFIG. 1 is a block diagram of a conventional memory selection device, FIG. 2 is a diagram for explaining the memory space in the memory bank shown in FIG. 1, and FIG. 3 is an example of a memory selection device according to the present invention. The configuration diagrams shown in FIGS. 4a and 4b are diagrams for explaining the memory space of the memory in this device. 20... Central processing unit (CPU), 21... Latch circuit, 22... Address conversion section, 23', 24.25
...Decoder, M1-M24...Memory, DB...
・Data bus, AB Kawako address bus
Claims (1)
ドレス情報を送るアドレスバスとの間に接続され前記デ
ータを記憶する複数のメモリと、前記データバスに送ら
れるデータをラッチするラッチ回路と、このラッチ回路
からの信号と前記アドレスバスに送られるアドレス情報
とに基づいて前記複数のメモリのうち所定のものを選択
してデータの記憶および転送を行なわせるメモリ選択部
とを具備したことを特徴とするメモリ選択装置。a plurality of memories that are connected between a data bus that sends data and an address bus that sends address information that are connected to a central processing unit and that store the data; a latch circuit that latches the data that is sent to the data bus; The present invention is characterized by comprising a memory selection unit that selects a predetermined one of the plurality of memories to store and transfer data based on a signal from a latch circuit and address information sent to the address bus. memory selection device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4763583U JPS59155639U (en) | 1983-03-31 | 1983-03-31 | memory selection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4763583U JPS59155639U (en) | 1983-03-31 | 1983-03-31 | memory selection device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59155639U true JPS59155639U (en) | 1984-10-19 |
Family
ID=30178184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4763583U Pending JPS59155639U (en) | 1983-03-31 | 1983-03-31 | memory selection device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59155639U (en) |
-
1983
- 1983-03-31 JP JP4763583U patent/JPS59155639U/en active Pending
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