JPS61643U - data input device - Google Patents
data input deviceInfo
- Publication number
- JPS61643U JPS61643U JP7337085U JP7337085U JPS61643U JP S61643 U JPS61643 U JP S61643U JP 7337085 U JP7337085 U JP 7337085U JP 7337085 U JP7337085 U JP 7337085U JP S61643 U JPS61643 U JP S61643U
- Authority
- JP
- Japan
- Prior art keywords
- start address
- data
- bytes
- memory
- storing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案によるデータ処理方式を説明するための図
である。
1・・・レジスタ、2・・・アドレス決定手段、3・・
・バツファ領域。The drawings are diagrams for explaining a data processing method according to the present invention. 1...Register, 2...Address determining means, 3...
・Batsufa area.
Claims (1)
装置Aから装置Bへ、Nビットのデータ種別を示すコー
ドとMビットのデータ部とからなる話を転送するシステ
ムにおいて、装置Bに、各記憶場所に格納先頭アドレス
とバイト数を記憶するメモリを持つアドレス決定手段と
、上記装置AからNビットのデータ種別を示すコードと
Mビットのデータ部とからなる語が送られて来た時に当
該コードに対応するメモリの記憶場所から格納先頭アド
レスを読出し当該読出し格納先頭アドレスで定まるバツ
ファ領域の記憶場所に当該語のデータ部を格納する手段
と、所定バイト数のデータが上記バツファ領域に格納さ
れる度に上記メモリの対応する格納先頭アドレスを単位
量だけ増加し対応するバイト数を単位量だけ減少する加
減算回路とを設置したことを特徴とするデータ処理方式
。In a system that transfers a story consisting of an N-bit data type code and an M-bit data section from device A to device B at a data transfer speed that exceeds the data processing capacity of device B, device B has data in each storage location. an address determination means having a memory for storing the start address and the number of bytes; and an address determining means having a memory for storing the start address and the number of bytes; means for reading a storage start address from a storage location in a corresponding memory and storing the data portion of the word in a storage location in a buffer area determined by the read storage start address, and each time a predetermined number of bytes of data is stored in the buffer area; and an addition/subtraction circuit that increases the corresponding storage start address of the memory by a unit amount and decreases the corresponding number of bytes by a unit amount.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7337085U JPS61643U (en) | 1985-05-16 | 1985-05-16 | data input device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7337085U JPS61643U (en) | 1985-05-16 | 1985-05-16 | data input device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61643U true JPS61643U (en) | 1986-01-06 |
JPS6132435Y2 JPS6132435Y2 (en) | 1986-09-20 |
Family
ID=30612669
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7337085U Granted JPS61643U (en) | 1985-05-16 | 1985-05-16 | data input device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61643U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000047882A (en) * | 1998-07-28 | 2000-02-18 | Nec Corp | Data processor |
-
1985
- 1985-05-16 JP JP7337085U patent/JPS61643U/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000047882A (en) * | 1998-07-28 | 2000-02-18 | Nec Corp | Data processor |
Also Published As
Publication number | Publication date |
---|---|
JPS6132435Y2 (en) | 1986-09-20 |
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