JPS635432A - Microprocessor - Google Patents

Abstract

PURPOSE:To upgrade the performance of a microprocessor succeeding a software based on an instruction structure by making the width of the data bus of the microprocessor integer-times of the processing bit number of an instruction execution unit. CONSTITUTION:An instruction execution unit 2 has an eight bit word length, and the data bus 3 has a 32 bit width. In case of accessing an instruction code, 32 bit is all at once stored in an instruction cue buffer 11, and outputted to the execution unit 2 in the unit of 8 bit. In case the instruction is an arithmetic operation between a memory and a memory, a data of 32 bit is stored in a data resister buffer 12 as a target data by the first access, by the following access, another data of 32 bit is stored in a data resister buffer 13, and outputted to the unit 2 being divided in divisions of 8 bit. The result of the arithmetic operation is returned to the buffer 12, and at the time when it is full, the results of 32 bit share are written all at once. Only necessary number of words can be read/written by a control part 8. With this constitution, the microprocessor can be speeded up, and the accessings to an external memories can be reduced, and a buse neck can be eliminated. Thus, the performance of the microcomputer is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor configured as an integrated circuit using MOS transistors and the like.

[Conventional technology]

Recently, personal computers have become extremely popular as information processing devices in offices. Competition to develop high-performance microprocessor products, which are mainly used as CPUs in these computers, is intensifying.

Conventionally, techniques for increasing the speed of microprocessors include methods such as increasing the number of processing bits of an internal arithmetic unit to twice the data width accessed from the outside in order to improve the internal instruction execution speed.

Advances in integrated circuit technology have made it possible to rapidly increase the number of transistors integrated into a single chip, and various parallel processing methods such as pipeline control have significantly improved the speed of the arithmetic units inside microprocessors. I've been doing it. As a result, even in microprocessors,
Compared to the internal calculation speed, bus usage waiting time due to improved bus usage efficiency has become a factor that cannot be ignored.

This is the occurrence of a so-called "pass neck."

Conventional microprocessors have adopted cache memory as a way to eliminate pathnecks, but the simplest method has always been to expand the data bus width.

[Problem that the invention seeks to solve]

-Generally, when the data bus is expanded to eliminate pathnecks, conventional microprocessors pursue efficiency;
The number of internally processed data bits is set equal to the number of bits of the data bus width, and the instruction architecture is often new, which makes existing software unusable, making it difficult to inherit software assets. be.

An object of the present invention is to provide a microprocessor that can directly inherit the software properties running on conventional microprocessors and has higher performance.

[Means for Solving the Problems] The device of the present invention has an instruction execution means with a word length of n bits (n is a natural number) that can be processed at a time, and a bit width of n×k bits (k is a natural number). i.e. a word data bus,
an instruction queue buffer having a capacity of k words, at least one data register buffer having a capacity of k words, and controlling signals independently generated in word units; control the exchange of data in an arbitrary number of words between the instruction execution means and at least one of the instruction queue buffer or the data register buffer, and exchange arbitrary word data in word units between the instruction execution means and at least one of the instruction queue buffer or the data register buffer; and a control means for controlling.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The microprocessor of FIG. 1 includes an instruction execution unit 2 that executes a conventional instruction architecture, and a data bus 3 that is expanded to an integral multiple of the internal processing words of the instruction execution unit 2.
, an instruction queue buffer 11 and data register buffers 12 and 13 placed between the instruction execution unit 2 and the data bus 3, and an instruction queue buffer 11 and data register buffers 12 and 13 placed between the instruction execution unit 2 and the data bus 3. The bus cycle control unit 1 includes a control section 14 that controls 15 control signals.

The instruction queue buffer 11 has a function of temporarily storing instructions accessed by the data bus 3 having a width that is an integral multiple of the word length processed by the conventional instruction execution unit 2, and sequentially sending them to the instruction execution unit 2.

The data register buffer 12 is a buffer that temporarily stores data other than instructions, and has a buffer function when reading/writing from/to the memory, and at the same time, the instruction execution unit 2 reads/writes any word in the buffer. It is structured so that it can be done. If the conventional instruction execution unit 2 has an operation instruction between memories, a data register buffer 13 is further provided and used together with the data register buffer 12 for a source register and a destination.

As mentioned above, the instruction execution unit 2 is a unit that executes software based on the conventional instruction architecture, and has a word length of 8 bits.

The data bus 3 as a microprocessor has a width of 32 bits.

When an instruction code is accessed, 32 bits are obtained at one time, stored in the instruction queue buffer 11, and outputted to the instruction execution unit 2 in 8 bits at a time.

If the instruction is a memory-to-memory operation, the first memory access stores 32 bits of data as destination data in the data register buffer 12, and the next memory access stores 32 bits of data in another memory location as source data. The data is stored in the data register buffer 13 as . In the next step, the data is divided into 8 bits and output to the instruction execution unit 2, and the operation result is returned to the data register buffer 12. Once the buffer is full, 32 bits can be written to memory.

Of course, since the bus control signal can be output independently for each 8-bit word, only the required number of words can be read/written depending on the command. This is controlled by the control section 14.

As described above, in this embodiment, although the data bus width is expanded compared to the conventional one, the data width for instruction execution remains the same as before, and existing software can be used.

〔Effect of the invention〕

As explained above, the present invention completely inherits the software assets accumulated based on the conventional instruction architecture by making the width of the data bus of the microprocessor an integral multiple of the number of processing bits of the conventional instruction execution unit. However, with advances in integrated circuit technology, the speed of microprocessors can be increased and accesses to external memory can be reduced, thereby eliminating bus necks.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Bus cycle control unit, 2... Instruction execution unit, 3... Data bus, 11... Instruction queue buffer, 12.13... Data register buffer, 1
4...Control unit, 15...Internal bus.

Claims (1)

[Scope of Claims] An instruction execution means with a word length of n bits (n is a natural number) that can be processed at one time, a data bus with a bit width of n×k bits (k is a natural number), that is, k words, and a capacity of k words. an instruction queue buffer having a capacity of k words, and at least one data register buffer having a capacity of k words; generating control signals independently in word units; control for controlling transfer of data in an arbitrary number of words between said instruction execution means and at least one of said instruction queue buffer or said data register buffer; A microprocessor comprising: means.