JPS58148798U - memory element - Google Patents

memory element

Info

Publication number
JPS58148798U
JPS58148798U JP4471182U JP4471182U JPS58148798U JP S58148798 U JPS58148798 U JP S58148798U JP 4471182 U JP4471182 U JP 4471182U JP 4471182 U JP4471182 U JP 4471182U JP S58148798 U JPS58148798 U JP S58148798U
Authority
JP
Japan
Prior art keywords
memory cell
parity
memory element
group selected
line direction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4471182U
Other languages
Japanese (ja)
Inventor
信生 山田
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP4471182U priority Critical patent/JPS58148798U/en
Publication of JPS58148798U publication Critical patent/JPS58148798U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図は本考案の一実施例を示すメモリ素子のメモリセル及
び周辺のコントロール回路を示す回路図である。 1・・・出力データセレクト、センスアンプ回路、2・
・・出力データバッファ、反転回路、3,4・・・セン
スアンプ、パリティジェネレート、パリティデータ比較
路、Qx−nx、xQ〜xn・・・パリティデータ記憶
用メモリセル。
The figure is a circuit diagram showing a memory cell and a peripheral control circuit of a memory device according to an embodiment of the present invention. 1... Output data select, sense amplifier circuit, 2...
. . . Output data buffer, inversion circuit, 3, 4 . . . sense amplifier, parity generator, parity data comparison path, Qx-nx, xQ to xn . . . Memory cell for storing parity data.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ワードライン方向及びビットライン方向にそれぞれパリ
ティジェネレータ及びパリティ情報記憶セルを設け、同
一ツー1’ラインで選択されたメモリセル群のパリティ
チェック結果と同二ビットラインで選択されるメモリセ
ル群のパリティチェック結果をもとにメモリセルi羊の
1ビット反転障害を自己修正する機能を具備したことを
特徴とするメモリ素子。
A parity generator and a parity information storage cell are provided in the word line direction and the bit line direction, respectively, and the parity check results of the memory cell group selected on the same two 1' lines and the parity check of the memory cell group selected on the same two bit lines are provided. A memory element characterized by having a function of self-correcting a 1-bit inversion fault in a memory cell i based on the result.
JP4471182U 1982-03-31 1982-03-31 memory element Pending JPS58148798U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4471182U JPS58148798U (en) 1982-03-31 1982-03-31 memory element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4471182U JPS58148798U (en) 1982-03-31 1982-03-31 memory element

Publications (1)

Publication Number Publication Date
JPS58148798U true JPS58148798U (en) 1983-10-06

Family

ID=30055759

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4471182U Pending JPS58148798U (en) 1982-03-31 1982-03-31 memory element

Country Status (1)

Country Link
JP (1) JPS58148798U (en)

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