JPS5839799U

JPS5839799U - Semiconductor read-only memory device

Info

Publication number: JPS5839799U
Application number: JP13150381U
Authority: JP
Inventors: 樋口　三左男
Original assignee: 日本電気株式会社
Priority date: 1981-09-04
Filing date: 1981-09-04
Publication date: 1983-03-15

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来のドツト表示法による漢字表示を説明する
ためのブロック図、第２図は従来のＲＯＭの一例のブロ
ック図、第３図はＲＯＭから読み出される文字の一例を
説明するための図、第４図はドツトアドレス数１６、文
字データ数ＭのＲＯＭのブロック図、第５図は本考案の
一実施例のブロック図である。１・・・・・・ＲＯＭセルアレイ、２・・・・・・Ｘデ
コーダ、３・・・・・・Ｙデコーダ、４・・・・・・Ｙ
セレクタ、５・・・、・・・出力バッファ、１１・・・
・・・Ｒ９Ｍセルアレイ、１２・・・・・・Ｘデコーダ
、１３・・・・・・Ｙデコーダ、１４・・・・・・Ｙセ
レクタ、１５・・・・・・出力バッファ、２１・・・・
・・ＲＯＭセルアレイ、２２・・・・・・Ｘデコーダ、
２４・・・・・・Ｙセレクタ、２６・・・・・・出力セ
ット回路。Figure 1 is a block diagram for explaining kanji display using the conventional dot display method, Figure 2 is a block diagram for an example of a conventional ROM, and Figure 3 is a diagram for explaining an example of characters read from the ROM. 4 is a block diagram of a ROM having 16 dot addresses and M character data, and FIG. 5 is a block diagram of an embodiment of the present invention. 1...ROM cell array, 2...X decoder, 3...Y decoder, 4...Y
Selector, 5..., Output buffer, 11...
...R9M cell array, 12...X decoder, 13...Y decoder, 14...Y selector, 15...output buffer, 21...・
...ROM cell array, 22...X decoder,
24...Y selector, 26...Output set circuit.

Claims

[Scope of utility model registration request]

In a semiconductor read-only memory device consisting of a capacity of M bits, a number of output bits of N bits, and a number of address addresses of M/N, the number of address addresses that are clearly not to be used is P1. When Q is the number of address addresses that are clearly determined to be either "1" or 64099, the memory cell section and decoder section selected by P or Q are omitted, and externally the number of address addresses is M/N, capacity M bits are maintained, and the number of address addresses (M/N-P-Q) is maintained internally.
) If the capacity is NX (M/N-P-Q) bit configuration and the address corresponding to Q is selected externally, the output N
A semiconductor read-only memory device comprising an output set circuit that outputs data indicating a background when not selected so that all bits become ``1'' or ``0''.