ZA200007686B - Multiple-valued logic circuit architecture: Supplementary symmetrical logic circuit structure (SUS-LOC). - Google Patents
Multiple-valued logic circuit architecture: Supplementary symmetrical logic circuit structure (SUS-LOC). Download PDFInfo
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- ZA200007686B ZA200007686B ZA200007686A ZA200007686A ZA200007686B ZA 200007686 B ZA200007686 B ZA 200007686B ZA 200007686 A ZA200007686 A ZA 200007686A ZA 200007686 A ZA200007686 A ZA 200007686A ZA 200007686 B ZA200007686 B ZA 200007686B
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09425—Multistate logic
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/086,869 US6133754A (en) | 1998-05-29 | 1998-05-29 | Multiple-valued logic circuit architecture; supplementary symmetrical logic circuit structure (SUS-LOC) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ZA200007686B true ZA200007686B (en) | 2002-01-30 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ZA200007686A ZA200007686B (en) | 1998-05-29 | 2000-12-20 | Multiple-valued logic circuit architecture: Supplementary symmetrical logic circuit structure (SUS-LOC). |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US6133754A (zh) |
| EP (1) | EP1092267A1 (zh) |
| JP (1) | JP4427188B2 (zh) |
| KR (1) | KR100683235B1 (zh) |
| CN (1) | CN1153349C (zh) |
| AU (1) | AU750648B2 (zh) |
| CA (1) | CA2333623C (zh) |
| WO (1) | WO1999063669A1 (zh) |
| ZA (1) | ZA200007686B (zh) |
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| US6963225B2 (en) * | 2001-01-22 | 2005-11-08 | Texas Instruments Incorporated | Quad state logic design methods, circuits, and systems |
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| US7548092B2 (en) | 2004-02-25 | 2009-06-16 | Ternarylogic Llc | Implementing logic functions with non-magnitude based physical phenomena |
| US7397690B2 (en) * | 2004-06-01 | 2008-07-08 | Temarylogic Llc | Multi-valued digital information retaining elements and memory devices |
| US7696785B2 (en) * | 2004-02-25 | 2010-04-13 | Ternarylogic Llc | Implementing logic functions with non-magnitude based physical phenomena |
| US7580472B2 (en) * | 2004-02-25 | 2009-08-25 | Ternarylogic Llc | Generation and detection of non-binary digital sequences |
| US8374289B2 (en) | 2004-02-25 | 2013-02-12 | Ternarylogic Llc | Generation and detection of non-binary digital sequences |
| US7218144B2 (en) * | 2004-02-25 | 2007-05-15 | Ternarylogic Llc | Single and composite binary and multi-valued logic functions from gates and inverters |
| US20060021003A1 (en) * | 2004-06-23 | 2006-01-26 | Janus Software, Inc | Biometric authentication system |
| US7562106B2 (en) * | 2004-08-07 | 2009-07-14 | Ternarylogic Llc | Multi-value digital calculating circuits, including multipliers |
| US20100164548A1 (en) * | 2004-09-08 | 2010-07-01 | Ternarylogic Llc | Implementing Logic Functions With Non-Magnitude Based Physical Phenomena |
| US7782089B2 (en) * | 2005-05-27 | 2010-08-24 | Ternarylogic Llc | Multi-state latches from n-state reversible inverters |
| JP4288355B2 (ja) | 2006-01-31 | 2009-07-01 | 国立大学法人北陸先端科学技術大学院大学 | 三値論理関数回路 |
| US8731410B2 (en) * | 2007-10-02 | 2014-05-20 | Luxtera, Inc. | Method and system for split voltage domain receiver circuits |
| US8975922B2 (en) | 2008-02-29 | 2015-03-10 | California Institute Of Technology | Method and apparatus for simultaneous processing of multiple functions |
| US8671369B2 (en) | 2009-12-08 | 2014-03-11 | University Of Seoul Industry Cooperation Foundation | Quantum Karnaugh map |
| US8412666B1 (en) | 2010-12-27 | 2013-04-02 | Michael S. Khvilivitzky | Method for logical processing of continuous-valued logical signals |
| JP5363511B2 (ja) * | 2011-01-14 | 2013-12-11 | 利康 鈴木 | 多値論理回路 |
| JP5249379B2 (ja) * | 2011-03-29 | 2013-07-31 | 利康 鈴木 | 多値用双方向性スイッチング手段 |
| US8847625B2 (en) * | 2012-02-16 | 2014-09-30 | Southern Methodist University | Single clock distribution network for multi-phase clock integrated circuits |
| CN103973296B (zh) * | 2013-01-29 | 2018-04-10 | 中国航空工业集团公司西安飞机设计研究所 | 一种基于时序逻辑的双座舱指令综合方法及其电路 |
| US10141930B2 (en) | 2013-06-04 | 2018-11-27 | Nvidia Corporation | Three state latch |
| US9576244B2 (en) * | 2013-09-03 | 2017-02-21 | Roger Midmore | Methods and systems of four-valued simulation |
| US9575951B2 (en) * | 2013-09-03 | 2017-02-21 | Roger Midmore | Methods and systems of four valued analogical transformation operators used in natural language processing and other applications |
| US9679540B2 (en) * | 2014-10-29 | 2017-06-13 | Kopin Corporation | Ternary addressable select scanner |
| CN104320128A (zh) * | 2014-11-14 | 2015-01-28 | 浙江工商大学 | 一种基于cmos的qbc23电路 |
| CN104320126A (zh) * | 2014-11-14 | 2015-01-28 | 浙江工商大学 | Qc变换bc21的电路单元 |
| CN104333370A (zh) * | 2014-11-14 | 2015-02-04 | 浙江工商大学 | 基于四二值时钟的qbc20电路 |
| CN104579310A (zh) * | 2014-11-14 | 2015-04-29 | 浙江工商大学 | 基于cmos的qb32模块电路单元 |
| CN104320127A (zh) * | 2014-11-14 | 2015-01-28 | 浙江工商大学 | 一种qc转换为bc13的cmos电路单元 |
| FI20150334A (fi) | 2015-01-14 | 2016-07-15 | Artto Mikael Aurola | Paranneltu puolijohdekokoonpano |
| KR101689159B1 (ko) * | 2015-07-10 | 2016-12-23 | 울산과학기술원 | 3진수 논리회로 |
| US9496872B1 (en) * | 2015-07-17 | 2016-11-15 | Infineon Technologies Ag | Method for manufacturing a digital circuit and digital circuit |
| WO2017160863A1 (en) | 2016-03-15 | 2017-09-21 | Louisiana Tech Research Corporation | Method and apparatus for constructing multivalued microprocessor |
| RU2618901C1 (ru) * | 2016-06-17 | 2017-05-11 | Сергей Петрович Маслов | Пороговый элемент троичной логики на токовых зеркалах |
| CN106847328B (zh) * | 2016-12-23 | 2018-09-18 | 宁波大学 | 一种利用cnfet实现的三值2-9线地址译码器 |
| CN108268240A (zh) * | 2017-01-03 | 2018-07-10 | 胡五生 | 多值寄存器 |
| RU2648565C1 (ru) * | 2017-06-01 | 2018-03-26 | Сергей Петрович Маслов | Устройство троичной схемотехники на токовых зеркалах |
| KR101928223B1 (ko) | 2017-12-29 | 2018-12-11 | 울산과학기술원 | 삼진 논리 회로 장치 |
| CN109376867B (zh) * | 2018-09-17 | 2021-05-07 | 合肥本源量子计算科技有限责任公司 | 两量子比特逻辑门的处理方法及装置 |
| KR102130980B1 (ko) * | 2018-12-31 | 2020-07-07 | 포항공과대학교 산학협력단 | 변조 퀸맥클러스키 알고리즘을 이용한 삼진 논리 합성 장치 및 방법 |
| DE102019123555B4 (de) | 2019-09-03 | 2022-12-01 | Infineon Technologies Ag | Physisch obfuskierter schaltkreis |
| CN112783472B (zh) * | 2019-11-05 | 2023-12-12 | 何群 | 多值逻辑宽位高速加法器 |
| US20220171601A1 (en) * | 2020-12-02 | 2022-06-02 | Danny Rittman | Electronic architecture and semiconductor devices based on a base 60 numeral system |
| WO2023027603A1 (fr) * | 2021-08-24 | 2023-03-02 | Cabinet Ccom 21 (Conseil, Consultance, Outils Manager Du 21 Ème Siècle) | Procédé de fabrication de dispositifs électroniques à l'aide de circuits numériques dans la base 3 |
Family Cites Families (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3129340A (en) * | 1960-08-22 | 1964-04-14 | Ibm | Logical and memory circuits utilizing tri-level signals |
| US3283256A (en) * | 1963-03-25 | 1966-11-01 | Hurowitz Mark | "n" stable multivibrator |
| US3492496A (en) * | 1966-12-12 | 1970-01-27 | Hughes Aircraft Co | Tristable multivibrator |
| US3508033A (en) * | 1967-01-17 | 1970-04-21 | Rca Corp | Counter circuits |
| US3671764A (en) * | 1971-02-05 | 1972-06-20 | Ibm | Auto-reset ternary latch |
| US3663837A (en) * | 1971-05-24 | 1972-05-16 | Itt | Tri-stable state circuitry for digital computers |
| US3969633A (en) * | 1975-01-08 | 1976-07-13 | Mostek Corporation | Self-biased trinary input circuit for MOSFET integrated circuit |
| JPS51144167A (en) * | 1975-06-04 | 1976-12-10 | Nec Corp | Digital phase modulation method |
| US4107549A (en) * | 1977-05-10 | 1978-08-15 | Moufah Hussein T | Ternary logic circuits with CMOS integrated circuits |
| US4217502A (en) * | 1977-09-10 | 1980-08-12 | Tokyo Shibaura Denki Kabushiki Kaisha | Converter producing three output states |
| DE2840006C2 (de) * | 1978-09-14 | 1980-10-02 | Deutsche Itt Industries Gmbh, 7800 Freiburg | CMOS-Schaltung zur Umwandlung eines Ternärsignals in zwei Binärsignale und Verwendung dieser CMOS-Schaltung |
| CA1228925A (en) * | 1983-02-25 | 1987-11-03 | Yoshikazu Yokomizo | Data decoding apparatus |
| US4737663A (en) * | 1984-03-01 | 1988-04-12 | Advanced Micro Devices, Inc. | Current source arrangement for three-level emitter-coupled logic and four-level current mode logic |
| US4814644A (en) * | 1985-01-29 | 1989-03-21 | K. Ushiku & Co. | Basic circuitry particularly for construction of multivalued logic systems |
| US4704544A (en) * | 1986-04-22 | 1987-11-03 | Unisearch Limited | Complementary current mirror logic |
| US4808854A (en) * | 1987-03-05 | 1989-02-28 | Ltv Aerospace & Defense Co. | Trinary inverter |
| US4990796A (en) * | 1989-05-03 | 1991-02-05 | Olson Edgar D | Tristable multivibrator |
| IT1250908B (it) * | 1990-06-22 | 1995-04-21 | St Microelectronics Srl | Struttura di porta d'uscita a tre stati particolarmente per circuiti integrati cmos |
| US5128894A (en) * | 1990-09-28 | 1992-07-07 | University Of Maryland | Multi-value memory cell using resonant tunnelling diodes |
| JPH04362759A (ja) * | 1991-06-10 | 1992-12-15 | Sharp Corp | 中央処理装置 |
| JP3429821B2 (ja) * | 1992-11-04 | 2003-07-28 | テキサス インスツルメンツ インコーポレイテツド | 多機能共鳴トンネリング論理ゲート |
| JPH0766671B2 (ja) * | 1992-12-09 | 1995-07-19 | 宮城工業高等専門学校長 | 多値置数電子装置 |
| KR940015920A (ko) * | 1992-12-30 | 1994-07-22 | 이대원 | 추론속도를 개선시킨 퍼지추론방법 |
| US5512764A (en) * | 1993-03-31 | 1996-04-30 | Texas Instruments Incorporated | Coupled-quantum-well field-effect resonant tunneling transistor for multi-valued logic/memory applications |
| US5469163A (en) * | 1993-05-24 | 1995-11-21 | Texas Instruments Incorporated | Multiple resonant tunneling circuits for positive digit range-4 base-2 to binary conversion |
| US5519393A (en) * | 1993-07-22 | 1996-05-21 | Bouens, Inc. | Absolute digital position encoder with multiple sensors per track |
| US5422845A (en) * | 1993-09-30 | 1995-06-06 | Intel Corporation | Method and device for improved programming threshold voltage distribution in electrically programmable read only memory array |
| US5457411A (en) * | 1994-12-02 | 1995-10-10 | Texas Instruments Incorporated | Trinary logic input gate |
| US5559734A (en) * | 1995-04-24 | 1996-09-24 | Saito; Tamio | Multiple voltage memory |
-
1998
- 1998-05-29 US US09/086,869 patent/US6133754A/en not_active Expired - Lifetime
-
1999
- 1999-05-21 AU AU44073/99A patent/AU750648B2/en not_active Ceased
- 1999-05-21 KR KR1020007013345A patent/KR100683235B1/ko not_active IP Right Cessation
- 1999-05-21 WO PCT/US1999/011349 patent/WO1999063669A1/en active IP Right Grant
- 1999-05-21 EP EP99927089A patent/EP1092267A1/en not_active Withdrawn
- 1999-05-21 JP JP2000552777A patent/JP4427188B2/ja not_active Expired - Fee Related
- 1999-05-21 CA CA002333623A patent/CA2333623C/en not_active Expired - Fee Related
- 1999-05-21 CN CNB998079677A patent/CN1153349C/zh not_active Expired - Fee Related
-
2000
- 2000-12-20 ZA ZA200007686A patent/ZA200007686B/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| KR100683235B1 (ko) | 2007-02-28 |
| EP1092267A1 (en) | 2001-04-18 |
| CN1153349C (zh) | 2004-06-09 |
| CA2333623A1 (en) | 1999-12-09 |
| CA2333623C (en) | 2009-12-22 |
| CN1307748A (zh) | 2001-08-08 |
| WO1999063669A1 (en) | 1999-12-09 |
| US6133754A (en) | 2000-10-17 |
| JP4427188B2 (ja) | 2010-03-03 |
| KR20010082557A (ko) | 2001-08-30 |
| AU750648B2 (en) | 2002-07-25 |
| AU4407399A (en) | 1999-12-20 |
| JP2002517937A (ja) | 2002-06-18 |
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