WO2025236229A1 - 显示基板及其驱动方法、显示装置 - Google Patents

显示基板及其驱动方法、显示装置

Info

Publication number
WO2025236229A1
WO2025236229A1 PCT/CN2024/093577 CN2024093577W WO2025236229A1 WO 2025236229 A1 WO2025236229 A1 WO 2025236229A1 CN 2024093577 W CN2024093577 W CN 2024093577W WO 2025236229 A1 WO2025236229 A1 WO 2025236229A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
signal line
gate electrode
electrode
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/093577
Other languages
English (en)
French (fr)
Other versions
WO2025236229A9 (zh
Inventor
青海刚
董向丹
皇甫鲁江
安成国
胡明
邱海军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to PCT/CN2024/093577 priority Critical patent/WO2025236229A1/zh
Priority to CN202480000946.XA priority patent/CN121359191A/zh
Publication of WO2025236229A1 publication Critical patent/WO2025236229A1/zh
Publication of WO2025236229A9 publication Critical patent/WO2025236229A9/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and its driving method, and a display device.
  • OLEDs Organic light-emitting diodes
  • QLEDs quantum dot light-emitting diodes
  • TFTs thin-film transistors
  • this disclosure provides a display substrate including multiple circuit units forming multiple cell rows and multiple cell columns.
  • At least one circuit unit includes a pixel driving circuit.
  • the pixel driving circuit includes at least a first capacitor, a second capacitor, a first transistor, a fourth transistor, an eighth transistor, a ninth transistor, and a third transistor as a driving transistor.
  • the second electrode of the first transistor is connected to the gate electrode of the third transistor and the first terminal of the first capacitor, respectively.
  • the first electrode of the ninth transistor is connected to the second terminal of the first capacitor and the second terminal of the second capacitor, respectively.
  • the second electrode of the ninth transistor is connected to the first electrode of the third transistor and the second electrode of the eighth transistor, respectively.
  • the first electrode of the fourth transistor is connected to a data signal line.
  • the pixel driving circuit further includes a second transistor, the first terminal of which is connected to the second terminal of the first transistor, the gate electrode of the third transistor, and the first terminal of the first capacitor, respectively, and the second terminal of the second transistor is connected to the second terminal of the third transistor.
  • the pixel driving circuit further includes a second transistor, the first terminal of which is connected to a second initial signal line, and the second terminal of which is connected to the second terminal of the third transistor.
  • the first transistor and the second transistor are connected to the same scan signal line.
  • the display substrate in a direction perpendicular to the display substrate, includes at least a first gate metal layer disposed on a substrate, a second gate metal layer disposed on a side of the first gate metal layer away from the substrate, and a first source/drain metal layer disposed on a side of the second gate metal layer away from the substrate.
  • the gate electrode of the first transistor and the gate electrode of the second transistor are disposed in the first gate metal layer, and the scan signal line is disposed in the first source/drain metal layer.
  • the gate electrode of the first transistor and the gate electrode of the second transistor are an integral structure that is interconnected.
  • the first transistor and the second transistor are dual-gate structures.
  • the gate electrode of the first transistor includes a first sub-gate electrode and a third sub-gate electrode
  • the gate electrode of the second transistor includes a second sub-gate electrode and a third sub-gate electrode.
  • the first transistor and the second transistor share the third sub-gate electrode.
  • the first sub-gate electrode and the second sub-gate electrode are strip-shaped extending along a first direction
  • the third sub-gate electrode is strip-shaped extending along a second direction, the first direction and the second direction intersect;
  • the first sub-gate electrode and the second sub-gate electrode are disposed on one side of the third sub-gate electrode in the first direction
  • the first sub-gate electrode is disposed on the side opposite to the second direction of the third sub-gate electrode
  • the second sub-gate electrode is disposed on one side of the third sub-gate electrode in the second direction, forming a "C" shape.
  • the second terminal of the fourth transistor is connected to the first terminal of the ninth transistor.
  • the second terminal of the fourth transistor is connected to the second terminal of the ninth transistor.
  • the first electrode of the first transistor is connected to the first initial signal line
  • the pixel driving circuit further includes a seventh transistor, the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the light-emitting device; the gate electrode of the seventh transistor and the gate electrode of the eighth transistor of the circuit unit in this unit row are connected to the first scan signal line in this unit row.
  • the first electrode of the first transistor is connected to the first initial signal line
  • the pixel driving circuit further includes a seventh transistor, the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the light-emitting device; the gate electrode of the seventh transistor of the circuit unit in this unit row is connected to the first scan signal line in the next unit row, and the gate electrode of the eighth transistor of the circuit unit in this unit row is connected to the first scan signal line in this unit row.
  • the pixel driving circuit further includes a seventh transistor, the first electrode of which is connected to the first electrode of the first transistor and the second initial signal line, and the second electrode of which is connected to the light-emitting device; the gate electrode of the seventh transistor and the gate electrode of the eighth transistor of the circuit unit in this unit row are connected to the first scan signal line in this unit row.
  • the pixel driving circuit further includes a seventh transistor, the first electrode of which is connected to the first electrode of the first transistor and the second initial signal line, and the second electrode of which is connected to the light-emitting device; the gate electrode of the seventh transistor of the circuit unit in this unit row is connected to the first scan signal line in the next unit row, and the gate electrode of the eighth transistor of the circuit unit in this unit row is connected to the first scan signal line in this unit row.
  • this disclosure also provides a display device including the aforementioned display substrate.
  • this disclosure also provides a driving method for a display substrate, the display substrate including multiple circuit units forming multiple cell rows and multiple cell columns, at least one circuit unit including a pixel driving circuit, the pixel driving circuit including at least a first capacitor, a second capacitor, a first transistor, a fourth transistor, an eighth transistor, a ninth transistor, and a third transistor as a driving transistor, the second terminal of the first transistor being connected to the gate electrode of the third transistor and the first terminal of the first capacitor respectively, the first terminal of the ninth transistor being connected to the second terminal of the first capacitor and the second terminal of the second capacitor respectively, the second terminal of the ninth transistor being connected to the first terminal of the third transistor and the second terminal of the eighth transistor respectively, and the first terminal of the fourth transistor being connected to a data signal line; the display substrate is configured to display corresponding display content, the display content including multiple display frames, at least one display frame including a refresh frame, the refresh frame including at least a compensation stage and a data writing stage performed sequentially, and the compensation stage sampling a threshold voltage by
  • the refresh frame includes at least an initialization phase, a compensation phase, and a data writing phase;
  • the eighth transistor and the ninth transistor are turned on, the third initial signal of the third initial signal line is written into the second terminal of the first capacitor and the second terminal of the second capacitor, and the second capacitor is charged.
  • the first transistor is turned on to initialize the gate electrode of the third transistor.
  • the first capacitor and the second capacitor discharge through the turned-on ninth transistor and the turned-on third transistor, so that the voltage difference across the first capacitor is
  • the fourth transistor is turned on, and the data signal of the data signal line is written to the second terminal of the first capacitor and the second terminal of the second capacitor.
  • the pixel driving circuit further includes a second transistor, the first terminal of which is connected to the second terminal of the first transistor, the gate electrode of the third transistor, and the first terminal of the first capacitor, respectively, and the second terminal of the second transistor is connected to the second terminal of the third transistor; during the compensation phase, the second transistor is turned on, and the first capacitor and the second capacitor discharge through the turned-on ninth transistor, the turned-on third transistor, and the turned-on second transistor.
  • the pixel driving circuit further includes a second transistor, wherein the first of the second transistor...
  • the second terminal of the second transistor is connected to the second initial signal line, and the second terminal of the second transistor is connected to the second terminal of the third transistor; during the compensation phase, the second transistor is turned on, and the first capacitor and the second capacitor discharge through the turned-on ninth transistor, the turned-on third transistor, and the turned-on second transistor.
  • the pixel driving circuit further includes a seventh transistor, the first terminal of which is connected to a second initial signal line, and the second terminal of which is connected to the light-emitting device; during the initialization phase, the seventh transistor is turned on, and the second initial signal of the second initial signal line initializes the light-emitting device; or, during the compensation phase, the seventh transistor is turned on, and the second initial signal of the second initial signal line initializes the light-emitting device.
  • At least one display frame further includes a hold frame, the hold frame including at least an adjustment phase;
  • the eighth transistor is turned on, and the third initial signal of the third initial signal line is written into the first terminal of the third transistor to adjust the bias state of the third transistor.
  • the pixel driving circuit further includes a seventh transistor, the first terminal of which is connected to a second initial signal line, and the second terminal of which is connected to the light-emitting device; during the adjustment phase, the seventh transistor is turned on, and the second initial signal of the second initial signal line initializes the light-emitting device.
  • Figure 1 is a schematic diagram of the structure of a display device
  • Figure 2 is a schematic diagram of a planar structure of a display substrate
  • Figure 3 is a schematic cross-sectional view of a display substrate
  • Figure 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure
  • Figure 5 is the driving timing diagram of the pixel driving circuit shown in Figure 4.
  • Figure 6 is a schematic diagram of the planar structure of a display substrate according to an exemplary embodiment of the present disclosure
  • Figure 7 is a schematic diagram of the structure of the first transistor and the second transistor in an exemplary embodiment of the present disclosure
  • Figure 8 is a schematic diagram of a display substrate after a semiconductor layer pattern has been formed in this disclosure.
  • Figures 9A and 9B are schematic diagrams of a display substrate after the formation of the first conductive layer pattern according to the present disclosure.
  • Figures 10A and 10B are schematic diagrams of a display substrate after the formation of a second conductive layer pattern according to the present disclosure
  • Figure 11 is a schematic diagram of a display substrate after the formation of a fourth insulating layer pattern according to the present disclosure
  • Figures 12A and 12B are schematic diagrams of a display substrate after the formation of a third conductive layer pattern according to the present disclosure
  • Figure 13 is a schematic diagram of a display substrate after the formation of a first planarization layer pattern according to the present disclosure
  • Figures 14A and 14B are schematic diagrams of a display substrate after the formation of a fourth conductive layer pattern according to the present disclosure.
  • Figure 15 is an equivalent circuit diagram of another pixel driving circuit of an exemplary embodiment of the present disclosure.
  • Figure 16 is a schematic diagram of the planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • Figure 17 is a schematic diagram of another display substrate after forming a semiconductor layer pattern according to the present disclosure.
  • Figures 18A and 18B are schematic diagrams of another display substrate after the formation of the first conductive layer pattern in this disclosure.
  • Figures 19A and 19B are schematic diagrams of another display substrate after the formation of the second conductive layer pattern in this disclosure.
  • Figure 20 is a schematic diagram of another display substrate after the formation of the fourth insulating layer pattern according to the present disclosure.
  • Figures 21A and 21B are schematic diagrams of another display substrate after the formation of the third conductive layer pattern in this disclosure.
  • Figure 22 is a schematic diagram of another display substrate after the formation of the first planarization layer pattern according to the present disclosure.
  • Figures 23A and 23B are schematic diagrams of another display substrate after the formation of the fourth conductive layer pattern in this disclosure.
  • Figure 24 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • Figure 25 is a schematic diagram of the planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • Figure 26 is a schematic diagram of another display substrate after a semiconductor layer pattern has been formed in this disclosure.
  • Figures 27A and 27B are schematic diagrams of a display substrate after the formation of the first conductive layer pattern in another embodiment of the present disclosure.
  • Figures 28A and 28B are schematic diagrams of a display substrate after the formation of a second conductive layer pattern in another embodiment of the present disclosure.
  • Figure 29 is a schematic diagram of another display substrate after the formation of the fourth insulating layer pattern according to the present disclosure.
  • Figures 30A and 30B are schematic diagrams of a display substrate after the formation of a third conductive layer pattern in this disclosure.
  • Figure 31 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • Figure 32 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • Figure 33 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • Figure 34 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • Figure 35 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • Figure 36 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • the scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto.
  • the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures.
  • the figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values shown in the figures.
  • connection should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.
  • a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to the region through which current primarily flows.
  • the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa.
  • the functions of the "source electrode” and “drain electrode” may sometimes be interchanged. Therefore, in this specification, the “source electrode” and “drain electrode” can be interchanged, and the “source terminal” and “drain terminal” can be interchanged.
  • electrical connection includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an “electrical function,” as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of “electrical functions” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°.
  • perpendicular refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced with “conductive film.”
  • insulating film may sometimes be replaced with “insulating layer.”
  • triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.
  • Figure 1 is a schematic diagram of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array.
  • the timing controller is connected to the data driver, the scan driver, and the light-emitting driver.
  • the data driver is connected to multiple data signal lines (D1 to Dn)
  • the scan driver is connected to multiple scan signal lines (S1 to Sm)
  • the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo).
  • the pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit.
  • the circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines.
  • the light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit.
  • the timing controller can provide grayscale values and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver.
  • a data driver can use grayscale values and control signals received from a timing controller to generate data voltages that will be supplied to data signal lines DATA1, D2, D3, ..., Dn.
  • the data driver can sample grayscale values using a clock signal and apply the data voltage corresponding to the grayscale value to data signal lines DATA1 through Dn, pixel by pixel, where n can be a natural number.
  • a scan driver can also generate data voltages from a timing controller... The controller receives clock signals, scan start signals, etc., to generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm.
  • the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm.
  • the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number.
  • the light-emitting driver can receive clock signals, transmit stop signals, etc., from a timing controller to generate transmit signals to light-emitting signal lines E1, E2, E3, ..., Eo.
  • the light-emitting driver can sequentially provide transmit signals with off-level pulses to light-emitting signal lines E1 to Eo.
  • the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.
  • a pixel array can be disposed on a display substrate.
  • Figure 2 is a schematic diagram of a planar structure of a display substrate.
  • the display substrate may include a display area and a border area surrounding the display area.
  • the display area of the display substrate may include a plurality of pixel units P arranged in a matrix.
  • At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light.
  • Each sub-pixel may include a circuit unit and a light-emitting unit.
  • the circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively.
  • the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line.
  • the light-emitting unit may include at least a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.
  • the first sub-pixel P1 can be a red sub-pixel (R) that emits red light
  • the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light
  • the third sub-pixel P3 can be a green sub-pixel (G) that emits green light.
  • the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal, vertical, or triangular manner, etc., which is not limited herein.
  • a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.
  • Figure 3 is a cross-sectional schematic diagram of a display substrate, illustrating the structure of three sub-pixels in the display substrate.
  • the display area of the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101.
  • the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.
  • the substrate 101 can be a flexible substrate or a rigid substrate.
  • the driving circuit layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit, and the pixel driving circuit can include multiple transistors and capacitors.
  • the light-emitting structure layer 103 can include multiple light-emitting units, each of which can include at least a light-emitting device.
  • the light-emitting device can include an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer.
  • the organic light-emitting layer emits light of a corresponding color under the driving of the anode and cathode.
  • the encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together.
  • the first and third encapsulation layers can be made of inorganic materials
  • the second encapsulation layer can be made of organic materials.
  • the second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic/organic/inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.
  • An exemplary embodiment of this disclosure provides a display substrate including a plurality of circuit units forming a plurality of cell rows and a plurality of cell columns.
  • At least one circuit unit includes a pixel driving circuit configured to output a driving current to a connected light-emitting device.
  • the pixel driving circuit includes at least a first capacitor, a second capacitor, a first transistor, a fourth transistor, an eighth transistor, a ninth transistor, and a third transistor as a driving transistor.
  • the second terminal of the body transistor is connected to the gate electrode of the third transistor and the first terminal of the first capacitor, respectively.
  • the first terminal of the ninth transistor is connected to the second terminal of the first capacitor and the second terminal of the second capacitor, respectively.
  • the second terminal of the ninth transistor is connected to the first terminal of the third transistor and the second terminal of the eighth transistor, respectively.
  • the first terminal of the fourth transistor is connected to the data signal line.
  • the pixel driving circuit further includes a second transistor, the first terminal of which is connected to the second terminal of the first transistor, the gate electrode of the third transistor, and the first terminal of the first capacitor, respectively, and the second terminal of the second transistor is connected to the second terminal of the third transistor.
  • the pixel driving circuit further includes a second transistor, the first terminal of which is connected to a second initial signal line, and the second terminal of which is connected to the second terminal of the third transistor.
  • the first transistor and the second transistor are connected to the same scan signal line.
  • the gate electrode of the first transistor and the gate electrode of the second transistor are an integral structure that is interconnected.
  • the first transistor and the second transistor are dual-gate structures.
  • the gate electrode of the first transistor includes a first sub-gate electrode and a third sub-gate electrode
  • the gate electrode of the second transistor includes a second sub-gate electrode and a third sub-gate electrode.
  • the first transistor and the second transistor share the third sub-gate electrode.
  • the second terminal of the fourth transistor is connected to the first terminal of the ninth transistor, or the second terminal of the fourth transistor is connected to the second terminal of the ninth transistor.
  • the display substrate of this disclosure will be illustrated by some exemplary embodiments below.
  • Figure 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • the pixel driving circuit of the exemplary embodiment of the present disclosure can be a 9T2C structure, which may include 9 transistors (first transistor T1 to ninth transistor T9) and 2 capacitors (first capacitor C1 and second capacitor C2).
  • the pixel driving circuit is connected to 11 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, fifth scan signal line S5, light emission signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA and first power supply line VDD).
  • the pixel driving circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5.
  • the first node N1 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first terminal of the first capacitor C1.
  • the second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fifth transistor T5, the second electrode of the eighth transistor T8, and the second electrode of the ninth transistor T9.
  • the third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.
  • the fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • the fifth node N5 is connected to the second electrode of the fourth transistor T4, the first electrode of the ninth transistor T9, the second terminal of the first capacitor C1, and the second terminal of the second capacitor C2.
  • the first end of the first capacitor C1 is connected to the first node N1
  • the second end of the first capacitor C1 is connected to the fifth node N5
  • the first end of the second capacitor C2 is connected to the first power line VDD
  • the second end of the second capacitor C2 is connected to the fifth node N5.
  • the first transistor T1 may be referred to as the first initialization transistor.
  • the gate electrode of the first transistor T1 is connected to the third scan signal line S3, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the first node N1.
  • the second transistor T2 can be referred to as a compensation transistor.
  • the gate electrode of the second transistor T2 is connected to the third scan signal line S3, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the gate electrode of the first transistor T1 and the gate electrode of the second transistor T2 are connected to the same third scan signal line S3, and the first transistor T1 and the second transistor T2 are simultaneously turned on and off.
  • the third transistor T3 can be referred to as a driving transistor.
  • the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the fourth transistor T4 can be referred to as a data write transistor.
  • the gate electrode of the fourth transistor T4 is connected to the fourth scan signal line S4, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the fifth node N5.
  • the fifth transistor T5 can be referred to as the first light-emitting control transistor.
  • the gate electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.
  • the sixth transistor T6 can be referred to as the second light-emitting control transistor.
  • the gate electrode of the sixth transistor T6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.
  • the seventh transistor T7 can be referred to as the second initialization transistor.
  • the gate electrode of the seventh transistor T7 is connected to the fifth scan signal line S5, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.
  • the fifth scan signal line S5 in a cell row can be the first scan signal line S1 in the next cell row, or the first scan signal line S1 in a cell row can be the fifth scan signal line S5 in the previous cell row.
  • the eighth transistor T8 can be referred to as the third initialization transistor.
  • the gate electrode of the eighth transistor T8 is connected to the first scan signal line S1, the first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is connected to the second node N2.
  • the ninth transistor T9 can be referred to as a charge-discharge transistor.
  • the gate electrode of the ninth transistor T9 is connected to the second scan signal line S2, the first electrode of the ninth transistor T9 is connected to the fifth node N5, and the second electrode of the ninth transistor T9 is connected to the second node N2.
  • the light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).
  • the first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS.
  • the signal of the first power line VDD is a continuously provided high-level signal
  • the signal of the second power line VSS is a continuously provided low-level signal
  • the first transistor T1 to the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are switching transistors.
  • the first transistor T1 to the ninth transistor T9 can be low-temperature polysilicon transistors (P-type transistors). Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield.
  • Figure 5 is the driving timing diagram of the pixel driving circuit shown in Figure 4. As shown in Figure 5, taking the example where the first transistor T1 to the ninth transistor T9 are all P-type transistors, the operation process of the pixel driving circuit can include:
  • the first stage, A can be called the initialization stage.
  • the signals of the third scan signal line S3, the fourth scan signal line S4, the fifth scan signal line S5, and the light emission signal line EM are high-level signals
  • the first scan signal line S1 and the second scan signal line S2 are low-level signals
  • the eighth transistor T8 and the ninth transistor T9 are turned on, and the other switching transistors are turned off.
  • the eighth transistor T8 When the eighth transistor T8 is turned on, the third initial signal of the third initial signal line INIT3 is written into the second node N2.
  • the ninth transistor T9 When the ninth transistor T9 is turned on, the signal of the second node N2 is written into the fifth node N5, charging the second capacitor C2. Since the eighth transistor T8 and the ninth transistor T9 are fully turned on in the charging path, the charging is completed quickly. When this stage is completed, the potentials of the second node N2 and the fifth node N5 are the voltage Vint3 of the third initial signal.
  • the second stage, B can be called the compensation stage.
  • the signals of the first scan signal line S1, the fourth scan signal line S4, and the light emission signal line EM are high-level signals, while the second scan signal line S2, the third scan signal line S3, and the fifth scan signal line S5 are low-level signals.
  • the first transistor T1, the second transistor T2, the seventh transistor T7, and the ninth transistor T9 are turned on, and the other switching transistors are turned off.
  • the seventh transistor T7 turns on, causing the second initial signal of the second initial signal line INIT2 to be written into the fourth node N4, initializing the fourth node N4 (light-emitting device).
  • the first transistor T1 turns on, causing the first initial signal of the first initial signal line INIT1 to be written into the first node N1, initializing the first node N1 (the gate electrode of the third transistor T3 and the first terminal of the first capacitor C1).
  • the potential of the first node N1 is the voltage Vint1 of the first initial signal. Since the voltage Vint1 of the first initial signal is low, the third transistor T3 turns on.
  • the second transistor T2 and the ninth transistor T9 turn on, causing the first capacitor C1 and the second capacitor C2 to discharge through the turned-on ninth transistor T9, the turned-on third transistor T3, and the turned-on second transistor T2, causing the potential of the fifth node N5 to gradually decrease until the third transistor T3 turns off.
  • the voltage difference across the first capacitor C1 is
  • the potential of the fifth node N5 is Vint1 +
  • the third stage, C can be called the data writing stage.
  • the signals of the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the fifth scan signal line S5, and the light emission signal line EM are high-level signals
  • the fourth scan signal line S4 is a low-level signal
  • the fourth transistor T4 is turned on
  • the other switching transistors are turned off.
  • the fourth transistor T4 is turned on, allowing the data signal on the data signal line to be written to the fifth node N5. Since the fourth transistor T4 is fully turned on, the data signal is written to the fifth node N5 relatively quickly.
  • the voltage difference across the first capacitor C1
  • the fourth stage, D can be called the light-emitting stage.
  • the signals of the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the fourth scan signal line S4, and the fifth scan signal line S5 are high-level signals
  • the light-emitting signal line EM is a low-level signal
  • the fifth transistor T5 and the sixth transistor T6 are turned on, and the other switching transistors are turned off.
  • the first power signal of the first power line VDD can provide driving current to the light-emitting device EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting device EL to emit light.
  • ) 2 K(Vdd-Vdata+
  • ) 2 K(Vdd-Vdata) 2 ;
  • K is a constant related to the process and design.
  • the fifth stage, E can be called the adjustment stage.
  • the signals of the second scan signal line S2, the third scan signal line S3, the fourth scan signal line S4, and the light emission signal line EM are high-level signals
  • the first scan signal line S1 and the fifth scan signal line S5 are low-level signals
  • the seventh transistor T7 and the eighth transistor T8 are turned on, and the other switching transistors are turned off.
  • the seventh transistor T7 is turned on, causing the second initial signal of the second initial signal line INIT2 to be written into the fourth node N4, re-initializing the fourth node N4 (the light-emitting device).
  • the eighth transistor T8 is turned on, causing the third initial signal of the third initial signal line INIT3 to be written into the second node N2 (the first terminal of the third transistor T3), adjusting the bias state of the third transistor T3. Because electrons are trapped in a trap when the third transistor T3 (i.e., the driving transistor) is in one state for a long time, hysteresis occurs.
  • the first scan signal line S1 can change from a high-level signal to a low-level signal at a first moment, and then change from a low-level signal to a high-level signal at a second moment; that is, the eighth transistor T8 is turned on at the first moment and turned off at the second moment.
  • the fifth scan signal line S5 can change from a high-level signal to a low-level signal at the second moment.
  • the signal level changes from low to high at the third moment, meaning the seventh transistor T7 turns on at the second moment and turns off at the third moment.
  • this stage first initializes the light-emitting device and then adjusts the bias state of the third transistor T3.
  • the sixth stage, F can be called the re-emission stage.
  • the signals of the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the fourth scan signal line S4, and the fifth scan signal line S5 are high-level signals
  • the emission signal line EM is a low-level signal
  • the fifth transistor T5 and the sixth transistor T6 are turned on, and the other switching transistors are turned off.
  • the first power signal of the first power line VDD can provide driving current to the light-emitting device EL through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T6, driving the light-emitting device EL to emit light again.
  • the first stage A, the second stage B, the third stage C, and the fourth stage D can form a refresh frame, which can be used to drive high-frequency displays (such as 90Hz and 120Hz). That is, high-frequency displays require four stages, from the first stage A to the fourth stage D.
  • the fifth stage E and the sixth stage F can form a hold frame.
  • the refresh frame and the hold frame together can be used to drive low-frequency displays (such as 60Hz). That is, low-frequency displays require six stages, from the first stage A to the sixth stage F.
  • the pixel driving circuit driving method provided in the exemplary embodiments of this disclosure by refreshing the frame including at least a compensation stage and a data writing stage performed sequentially, that is, separating the compensation stage and the data writing stage, can realize the writing of data signals faster, thus supporting higher frame rate displays.
  • This disclosure improves the compensation effect by sampling the threshold voltage using a capacitor self-discharge method during the compensation stage and storing the threshold voltage in the capacitor.
  • This disclosure effectively improves the hysteresis of the third transistor by applying a DC signal to the first electrode of the third transistor, which is beneficial for improving image retention and supporting low-frequency displays, thus improving the display effect.
  • Figure 6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure.
  • the display substrate may include a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate.
  • the driving circuit layer may include at least a plurality of circuit units, and the light-emitting structure layer may include at least a plurality of light-emitting units.
  • At least one circuit unit includes a pixel driving circuit, and at least one light-emitting unit includes a light-emitting device.
  • the light-emitting device is connected to the pixel driving circuit in the corresponding circuit unit, and the pixel driving circuit is configured to output a driving current to the connected light-emitting device.
  • the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit
  • the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device.
  • the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.
  • a plurality of circuit units arranged sequentially along a first direction X can be referred to as a unit row
  • a plurality of circuit units arranged sequentially along a second direction Y can be referred to as a unit column.
  • the plurality of unit rows and the plurality of unit columns constitute an array of circuit units arranged in an array, and the first direction X intersects with the second direction Y.
  • the pixel driving circuit can be connected to the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, the fourth scan signal line 34, the light emission signal line 35, the first power supply line 51, the data signal line 52, the first initial signal line 81, the second initial signal line 82, and the third initial signal line 83.
  • the multiple signal lines connected to the pixel driving circuit can be located within their respective circuit units.
  • the shapes of the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, the fourth scan signal line 34, the light emission signal line 35, the first initial signal line 81, the second initial signal line 82, and the third initial signal line 83 can be straight lines or broken lines extending along the first direction X of the main body, and the shapes of the first power line 51 and the data signal line 52 can be straight lines or broken lines extending along the second direction Y of the main body.
  • a extending along direction B means that A may include a main part and secondary parts connected to the main part.
  • the main part is a line, line segment, or strip-shaped body that extends along direction B.
  • the length of the main part extending in one direction is greater than the length of the secondary part extending in other directions.
  • “A extends along direction B” refers to "the main part of A extending along direction B”.
  • At least one pixel driving circuit may include a first capacitor, a second capacitor, and a plurality of transistors.
  • the plurality of transistors may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting control transistor, a sixth transistor T6 as a second light-emitting control transistor, a seventh transistor T7 as a second initialization transistor, an eighth transistor T8 as a third initialization transistor, and a ninth transistor T9 as a charge-discharge transistor.
  • the first transistor T1 to the ninth transistor T9 may be low-temperature polycrystalline silicon transistors.
  • the first capacitor may include a stacked first plate and a third plate
  • the second capacitor may include a stacked second plate and a fourth plate.
  • the gate electrode of the first transistor T1 is connected to the third scan signal line 33, the first terminal of the first transistor T1 is connected to the first initial signal line 81, and the second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2 and the first plate of the first capacitor, respectively.
  • the gate electrode of the second transistor T2 is connected to the third scan signal line 33, and the second terminal of the second transistor T2 is connected to the second terminal of the third transistor T3 and the first terminal of the sixth transistor T6, respectively.
  • the gate electrode of the third transistor T3 can serve as the first plate of the first capacitor, and the first terminal of the third transistor T3 is connected to the second terminals of the fifth transistor T5, the eighth transistor T8, and the ninth transistor T9, respectively.
  • the gate electrode of the fourth transistor T4 is connected to the fourth scan signal line 34, the first terminal of the fourth transistor T4 is connected to the data signal line 52, and the second terminal of the fourth transistor T4 is connected to the first terminal of the ninth transistor T9, the third plate of the first capacitor, and the second plate of the second capacitor, respectively.
  • the gate electrode of the fifth transistor T5 is connected to the light emission signal line 35, and the first terminal of the fifth transistor T5 is connected to the first power supply line 51.
  • the gate electrode of the sixth transistor T6 is connected to the light-emitting signal line 35, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7.
  • the gate electrode of the seventh transistor T7 is connected to the first scan signal line 31, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 82.
  • the gate electrode of the eighth transistor T8 is connected to the first scan signal line 31, and the first electrode of the eighth transistor T8 is connected to the third initial signal line 83.
  • the gate electrode of the ninth transistor T9 is connected to the second scan signal line 32.
  • connection of the gate electrode of the seventh transistor T7 to the first scan signal line 31 and the connection of the gate electrode of the eighth transistor T8 to the first scan signal line 31 means that the gate electrode of the seventh transistor T7 of the circuit unit in this unit row is connected to the first scan signal line 31 in the next unit row, and the gate electrode of the eighth transistor T8 of the circuit unit in this unit row is connected to the first scan signal line 31 in this unit row.
  • the first transistor T1 and the second transistor T2 are connected to the same scan signal line, that is, connected to the same third scan signal line 33.
  • At least one circuit unit may further include a power connection line 36.
  • the shape of the power connection line 36 may be a straight line or a broken line extending along the first direction X.
  • the power connection line 36 extending along the first direction X and the first power line 51 extending along the second direction Y are interconnected to form a mesh-like interconnected structure for transmitting the first power signal.
  • At least one circuit unit may further include a first initial connection line 84.
  • the shape of the first initial connection line 84 may be a straight line or a broken line extending along the second direction Y.
  • the interconnection of the first initial signal line 81 extending along the first direction X and the first initial connection line 84 extending along the second direction Y forms a mesh-like interconnected structure for transmitting the first initial signal.
  • At least one circuit unit may further include a second initial connection line 85.
  • the shape of the second initial connection line 85 may be a straight line or a broken line extending along the second direction Y.
  • the interconnection of the second initial signal line 82 extending along the first direction X and the second initial connection line 85 extending along the second direction Y forms a mesh-like interconnected structure for transmitting the second initial signal.
  • At least one circuit unit may further include a third initial connection line 86.
  • the shape of the third initial connection line 86 may be a straight line or a broken line extending along the second direction Y of the main body, along the first direction Y.
  • the interconnection of the third initial signal line 83 extending in the X direction and the third initial connection line 86 extending along the second direction Y forms a mesh-like interconnected structure for transmitting the third initial signal.
  • Figure 7 is a schematic diagram of the structure of the first transistor and the second transistor in an exemplary embodiment of the present disclosure.
  • the first transistor T1 may include at least a first active layer 11, a first gate electrode 21, a first source electrode (the first electrode of the first transistor T1), and a first drain electrode (the second electrode of the first transistor T1)
  • the second transistor T2 may include at least a second active layer 12, a second gate electrode 22, a second source electrode (the first electrode of the second transistor T2), and a second drain electrode (the second electrode of the second transistor T2), and the first drain electrode and the second source electrode are connected.
  • both the first transistor T1 and the second transistor T2 are dual-gate structures, and each can include two sub-active layers and two sub-gate electrodes.
  • the first active layer 11 may include a first sub-active layer 10-1 and a third sub-active layer 10-3.
  • the first sub-active layer 10-1 may be a strip extending along the second direction Y
  • the third sub-active layer 10-3 may be a strip extending along the first direction X.
  • the first sub-active layer 10-1 may be disposed on one side of the third sub-active layer 10-3 in the first direction X.
  • the first sub-active layer 10-1 In the second direction Y, the first sub-active layer 10-1 may be disposed on the opposite side of the third sub-active layer 10-3 in the second direction Y, and the ends of the first sub-active layer 10-1 and the third sub-active layer 10-3 that are close to each other are connected to form a... shape.
  • the second active layer 12 may include a second sub-active layer 10-2 and a third sub-active layer 10-3.
  • the second sub-active layer 10-2 may be a strip extending along the second direction Y.
  • the second sub-active layer 10-2 may be disposed on one side of the third sub-active layer 10-3 in the first direction X.
  • the second sub-active layer 10-2 may be disposed on one side of the third sub-active layer 10-3 in the second direction Y.
  • the ends of the second sub-active layer 10-2 and the third sub-active layer 10-3 that are close to each other are connected to form a... shape.
  • the first active layer 11 and the second active layer 12 together constitute... shape.
  • the third sub-active layer 10-3 serves as both a sub-active layer of the first active layer 11 and a sub-active layer of the second active layer 12, meaning that the first active layer 11 and the second active layer 12 share the same third sub-active layer 10-3.
  • the first active layer 11 and the second active layer 12 can be an integral structure that is interconnected.
  • the first gate electrode 21 may include a first sub-gate electrode 20-1 and a third sub-gate electrode 20-3.
  • the first sub-gate electrode 20-1 may be a strip extending along a first direction X, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first sub-active layer 10-1 on the substrate.
  • the third sub-gate electrode 20-3 may be a strip extending along a second direction Y, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the third sub-active layer 10-3 on the substrate.
  • the first sub-gate electrode 20-1 may be disposed on one side of the third sub-gate electrode 20-3 in the first direction X.
  • the first sub-gate electrode 20-1 may be disposed on the opposite side of the third sub-gate electrode 20-3 in the second direction Y, and the ends of the first sub-gate electrode 20-1 and the third sub-gate electrode 20-3 that are close to each other are connected to each other, forming... shape.
  • the second gate electrode 22 may include a second sub-gate electrode 20-2 and a third sub-gate electrode 20-3.
  • the shape of the second gate electrode 22 may be a strip extending along the first direction X.
  • the orthographic projection of the second gate electrode 22 on the substrate at least partially overlaps with the orthographic projection of the second sub-active layer 10-2 on the substrate.
  • the second sub-gate electrode 20-2 In the first direction X, the second sub-gate electrode 20-2 may be disposed on one side of the third sub-gate electrode 20-3 in the first direction X.
  • the second sub-gate electrode 20-2 may be disposed on one side of the third sub-gate electrode 20-3 in the second direction Y.
  • the ends of the second sub-gate electrode 20-2 and the third sub-gate electrode 20-3 that are close to each other are connected to each other, forming... shape.
  • the first gate electrode 21 and the second gate electrode 22 together form a "C" shape.
  • the third sub-gate electrode 20-3 serves as both a sub-gate electrode of the first gate electrode 21 and a sub-gate electrode of the second gate electrode 22, meaning that the first gate electrode 21 and the second gate electrode 22 share the same third sub-gate electrode. Sub-gate electrode 20-3.
  • first gate electrode 21 and the second gate electrode 22 can be an integral structure that is interconnected.
  • the display substrate may include a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source/drain metal layer, and a second source/drain metal layer sequentially disposed on a substrate.
  • the first active layer 11 and the second active layer 12 may be disposed in the semiconductor layer
  • the first gate electrode 21 and the second gate electrode 22 may be disposed in the first gate metal layer
  • the third scan signal line 33 may be disposed in the first source/drain metal layer
  • the third scan signal line 33 is connected to the integrally structured first gate electrode 21 and second gate electrode 22 through vias.
  • the first initial signal line 81 may be disposed in the second gate metal
  • the second initial signal line 82 and the third initial signal line 83 may be disposed in the first source-drain metal layer
  • the first initial connection line 84, the second initial connection line 85 and the third initial connection line 86 may be disposed in the second source-drain metal layer.
  • the power connection line 36 may be disposed in the first source-drain metal layer, and the first power line 51 may be disposed in the second source-drain metal layer.
  • the following description uses the fabrication process of a display substrate as an example.
  • the "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development.
  • Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used.
  • a “thin film” refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film” does not require a patterning process during the entire fabrication process, it can also be called a “layer.” If the "thin film” requires a patterning process during the entire fabrication process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern.”
  • the phrase “A and B are arranged in the same layer” in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • the fabrication process of the display substrate in this embodiment may include the following operations.
  • Forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film by a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, as shown in FIG8.
  • the semiconductor layer of each circuit unit in the display substrate may include at least: a first active layer 11 of a first transistor T1, a second active layer 12 of a second transistor T2, a third active layer 13 of a third transistor T3, a fourth active layer 14 of a fourth transistor T4, a fifth active layer 15 of a fifth transistor T5, a sixth active layer 16 of a sixth transistor T6, a seventh active layer 17 of a seventh transistor T7, an eighth active layer 18 of an eighth transistor T8, and a ninth active layer 19 of a ninth transistor T9, and the first active layer 11 to the ninth active layer 19 may be an integral structure interconnected with each other.
  • the first active layer 11, the second active layer 12, the sixth active layer 16, and the seventh active layer 17 may be located on one side of the third active layer 13 in the first direction X
  • the fifth active layer 15 and the eighth active layer 18 may be located on the opposite side of the third active layer 13 in the first direction X
  • the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 may be located on one side of the third active layer 13 in the second direction Y
  • the first active layer 11, the second active layer 12, the fourth active layer 14, the eighth active layer 18, and the ninth active layer 19 may be located on the opposite side of the third active layer 13 in the second direction Y.
  • the third active layer 13 can be shaped like an inverted " ⁇ "
  • the first active layer 11 and the second active layer 12 can be shaped like an "L”
  • the fourth active layer 14 the fifth active layer 15, and the sixth active layer 16...
  • the seventh active layer 17 and the eighth active layer 18 can be shaped like an "I”
  • the ninth active layer 19 can be shaped like a " ⁇ ”.
  • the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions.
  • the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be interconnected, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer.
  • the first region 13-1 of the third active layer, the second region 15-2 of the fifth active layer, the second region 18-2 of the eighth active layer, and the second region 19-2 of the ninth active layer may be interconnected, and the first region 13-1 of the third active layer may simultaneously serve as the second region 15-2 of the fifth active layer, the second region 18-2 of the eighth active layer, and the second region 19-2 of the ninth active layer, constituting the second node N2 of the pixel driving circuit.
  • the second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer can be interconnected.
  • the second region 13-2 of the third active layer can simultaneously serve as both the second region 12-2 of the second active layer and the first region 16-1 of the sixth active layer, forming the third node N3 of the pixel driving circuit.
  • the second region 14-2 of the fourth active layer and the first region 19-1 of the ninth active layer can be interconnected.
  • the second region 14-2 of the fourth active layer can serve as the first region 19-1 of the ninth active layer.
  • the second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer can be interconnected.
  • the second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer, forming the fourth node N4 of the pixel driving circuit.
  • the first active layer's first zone 11-1, the fourth active layer's first zone 14-1, the fifth active layer's first zone 15-1, the seventh active layer's first zone 17-1, and the eighth active layer's first zone 18-1 can be set individually.
  • the first transistor T1 has a dual-gate structure, including two sub-active layers.
  • the second transistor T2 has a dual-gate structure, including two sub-active layers.
  • the first active layer 11 may include a first sub-active layer 10-1 and a third sub-active layer 10-3.
  • the first sub-active layer 10-1 may be a strip extending along the second direction Y
  • the third sub-active layer 10-3 may be a strip extending along the first direction X.
  • the first sub-active layer 10-1 may be disposed on one side of the third sub-active layer 10-3 in the first direction X.
  • the first sub-active layer 10-1 In the second direction Y, the first sub-active layer 10-1 may be disposed on the opposite side of the third sub-active layer 10-3 in the second direction Y, and the ends of the first sub-active layer 10-1 and the third sub-active layer 10-3 that are close to each other are connected to form a... shape.
  • the second active layer 12 may include a second sub-active layer 10-2 and a third sub-active layer 10-3.
  • the second sub-active layer 10-2 may be a strip extending along the second direction Y.
  • the second sub-active layer 10-2 may be disposed on one side of the third sub-active layer 10-3 in the first direction X.
  • the second sub-active layer 10-2 may be disposed on one side of the third sub-active layer 10-3 in the second direction Y.
  • the ends of the second sub-active layer 10-2 and the third sub-active layer 10-3 that are close to each other are connected to form a... shape.
  • the first active layer 11 and the second active layer 12 together constitute... shape.
  • the third sub-active layer 10-3 serves as both a sub-active layer of the first active layer 11 and a sub-active layer of the second active layer 12, meaning that the first active layer 11 and the second active layer 12 share the same third sub-active layer 10-3.
  • the first semiconductor layer may be polycrystalline silicon (p-Si), i.e., the first transistor T1 to the ninth transistor T9 are LTPS transistors.
  • patterning the first semiconductor thin film using a patterning process may include: first forming an amorphous silicon (a-Si) thin film on a first insulating film; performing a hydrogen removal treatment on the amorphous silicon thin film; and then performing a crystallization treatment on the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form the pattern of the first semiconductor layer.
  • forming a first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer, as shown in Figures 9A and 9B, where Figure 9B is a schematic diagram of the first conductive layer in Figure 9A.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern of each circuit unit in the display substrate includes at least: a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, a seventh gate electrode 27, an eighth gate electrode 28, a ninth gate electrode 29, a gate connection line 30, a light-emitting signal line 35, a first electrode plate 71 of a first capacitor, and a second electrode plate 72 of a second capacitor.
  • the first electrode plate 71 of the first capacitor can be rectangular in shape, and the corners of the rectangle can be chamfered or grooved.
  • the orthographic projection of the first electrode plate 71 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate.
  • the first electrode plate 71 can simultaneously serve as the lower electrode plate of the first capacitor and the gate electrode of the third transistor T3.
  • the second electrode 72 of the second capacitor can be rectangular in shape, with chamfered or grooved corners. It can be located on one side of the first electrode 71 in the second direction Y.
  • the orthographic projection of the second electrode 72 onto the substrate does not overlap with the orthographic projection of the semiconductor layer onto the substrate.
  • the second electrode 72 can serve as the lower electrode of the second capacitor.
  • the first gate electrode 21 may be located on the side of the first electrode plate 71 away from the second electrode plate 72, and the region where the first gate electrode 21 overlaps with the first active layer may serve as the gate electrode of the first transistor T1 with a dual-gate structure.
  • the second gate electrode 22 may be located between the first gate electrode 21 and the first electrode plate 71, and the region where the second gate electrode 22 overlaps with the second active layer may serve as the gate electrode of the second transistor T2 with a dual-gate structure.
  • the first gate electrode 21 and the second gate electrode 22 can be connected to each other to form a "C" shape, and the first transistor T1 with a dual-gate structure and the second transistor T2 with a dual-gate structure share one of the sub-gate electrodes.
  • the first gate electrode 21 may include a first sub-gate electrode 20-1 and a third sub-gate electrode 20-3.
  • the first sub-gate electrode 20-1 may be a strip extending along a first direction X, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first sub-active layer 10-1 on the substrate.
  • the third sub-gate electrode 20-3 may be a strip extending along a second direction Y, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the third sub-active layer 10-3 on the substrate.
  • the first sub-gate electrode 20-1 may be disposed on one side of the third sub-gate electrode 20-3 in the first direction X.
  • the first sub-gate electrode 20-1 may be disposed on the opposite side of the third sub-gate electrode 20-3 in the second direction Y, and the ends of the first sub-gate electrode 20-1 and the third sub-gate electrode 20-3 that are close to each other are connected to each other, forming... shape.
  • the second gate electrode 22 may include a second sub-gate electrode 20-2 and a third sub-gate electrode 20-3.
  • the shape of the second gate electrode 22 may be a strip extending along the first direction X.
  • the orthographic projection of the second gate electrode 22 on the substrate at least partially overlaps with the orthographic projection of the second sub-active layer 10-2 on the substrate.
  • the second sub-gate electrode 20-2 In the first direction X, the second sub-gate electrode 20-2 may be disposed on one side of the third sub-gate electrode 20-3 in the first direction X.
  • the second sub-gate electrode 20-2 may be disposed on one side of the third sub-gate electrode 20-3 in the second direction Y.
  • the ends of the second sub-gate electrode 20-2 and the third sub-gate electrode 20-3 that are close to each other are connected to each other, forming... shape.
  • the first gate electrode 21 and the second gate electrode 22 together form a "C" shape.
  • the third sub-gate electrode 20-3 serves as both a sub-gate electrode of the first gate electrode 21 and a sub-gate electrode of the second gate electrode 22, meaning that the first gate electrode 21 and the second gate electrode 22 share the same third sub-gate electrode 20-3.
  • first gate electrode 21 and the second gate electrode 22 can be an integral structure that is interconnected.
  • the fourth gate electrode 24 may be in the shape of a "C" and may be located on the side of the first electrode plate 71 away from the second electrode plate 72.
  • the area where the fourth gate electrode 24 overlaps with the fourth active layer may serve as the gate electrode of the fourth transistor T4 in a dual-gate structure.
  • the shape of the seventh gate electrode 27 can be a strip shape extending along the first direction X, and it can be located on one side of the first electrode plate 71 in the second direction Y.
  • the area where the seventh gate electrode 27 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7.
  • the shape of the eighth gate electrode 28 can be a strip shape extending along the first direction X.
  • the region where the eighth gate electrode 28 overlaps with the eighth active layer, located on the side of the fourth gate electrode 24 away from the first plate 71, can serve as the gate electrode of the eighth transistor T8.
  • the ninth gate electrode 29 may be U-shaped and may be located between the fourth gate electrode 24 and the first plate 71.
  • the area where the ninth gate electrode 29 overlaps with the ninth active layer may serve as the gate electrode of the ninth transistor T9 in a dual-gate structure.
  • the gate connection line 30 can be a strip extending along the second direction Y, and can be located on the side of the seventh gate electrode 27 away from the first electrode plate 71.
  • the first end of the gate connection line 30 is connected to the seventh gate electrode 27 of the circuit unit in the current unit row, and the second end of the gate connection line 30 extends along the second direction Y and is connected to the eighth gate electrode 28 of the circuit unit in the next unit row, so that the seventh transistor T7 in the current unit row and the eighth transistor T8 in the next unit row are simultaneously turned on or off.
  • the first end of the gate connection line 30 is connected to the seventh gate electrode 27 of the circuit unit in the previous unit row, and the second end of the gate connection line 30 extends along the second direction Y and is connected to the eighth gate electrode 28 of the circuit unit in the current unit row, so that the seventh transistor T7 in the previous unit row and the eighth transistor T8 in the current unit row are simultaneously turned on or off.
  • the seventh gate electrode 27 of the circuit unit in the current row, the eighth gate electrode 28 of the circuit unit in the next row, and the gate connection line 30 can be an integral structure that is interconnected.
  • the seventh gate electrode 27 of the circuit unit in the previous row, the eighth gate electrode 28 of the circuit unit in the current row, and the gate connection line 30 can be an integral structure that is interconnected.
  • the shape of the light-emitting signal line 35 can be a straight line or a broken line extending along the first direction X of the main body, and can be located between the first electrode plate 71 and the second electrode plate 72.
  • the area where the light-emitting signal line 35 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5
  • the area where the light-emitting signal line 35 overlaps with the sixth active layer can serve as the gate electrode of the sixth transistor T6.
  • the first conductive layer can be used as a shield to conduct the semiconductor layer.
  • the semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor T1 to the ninth transistor T9.
  • the semiconductor layer in the region not shielded by the first conductive layer is conducted, that is, the first region and the second region of the first active layer to the ninth active layer are both conducted.
  • forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer, as shown in Figures 10A and 10B, where Figure 10B is a schematic diagram of the second conductive layer in Figure 10A.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern of each circuit unit in the display substrate includes at least: a third electrode 73 of a first capacitor, a fourth electrode 74 of a second capacitor, and a first initial signal line 81.
  • the outline shape of the third plate 73 of the first capacitor can be rectangular, and the corners of the rectangle can be chamfered or grooved.
  • the orthographic projection of the third plate 73 on the substrate at least partially overlaps with the orthographic projection of the first plate 71 on the substrate.
  • the third plate 73 can serve as the upper plate of the first capacitor.
  • the first plate 71 and the third plate 73 constitute the first capacitor of the pixel driving circuit.
  • the fourth electrode plate 74 of the second capacitor can be rectangular in shape, and the corners of the rectangle can be chamfered or grooved.
  • the orthographic projection of the fourth electrode plate 74 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 72 on the substrate.
  • the fourth electrode plate 74 can serve as the upper electrode plate of the second capacitor.
  • the second electrode plate 72 and the fourth electrode plate 74 constitute the second capacitor of the pixel driving circuit.
  • each circuit unit has a first opening 75 on its third electrode plate 73.
  • the first opening 75 can be block-shaped (e.g., rectangular) and can be located in the central region of the third electrode plate 73, forming a ring structure.
  • the first opening 75 exposes the third insulating layer covering the first electrode plate 71, and the orthographic projection of the first electrode plate 71 onto the substrate includes the orthographic projection of the first opening 75 onto the substrate.
  • the first opening 75 ... It is configured to accommodate a subsequently formed tenth via, which is located within the first opening 75 and exposes the first electrode 71, so that the subsequently formed first connecting electrode is connected to the first electrode 71.
  • a second opening 76 is provided on the fourth electrode plate 74 of each circuit unit.
  • the second opening 76 can be block-shaped (such as rectangular) and can be located on the side of the fourth electrode plate 74 near the third electrode plate 73.
  • the second opening 76 exposes the third insulating layer covering the second electrode plate 72, and the orthographic projection of the second electrode plate 72 on the substrate includes the orthographic projection of the second opening 76 on the substrate.
  • the second opening 76 is configured to accommodate a subsequently formed eleventh via, which is located within the second opening 76 and exposes the second electrode plate 72, allowing a subsequently formed second connection electrode to be connected to the second electrode plate 72.
  • the shape of the first initial signal line 81 can be a straight line or a broken line extending along the first direction X, and it can be located between the fourth gate electrode 24 and the eighth gate electrode 28.
  • a first initial connection block 81-1 can be provided on the first initial signal line 81.
  • the first initial connection block 81-1 can be provided in each circuit unit and connected to the first initial signal line 81.
  • the first initial connection block 81-1 is configured to be connected to the first region of the first active layer through a subsequently formed fifth connection electrode.
  • the first initial signal line 81 and the plurality of first initial connection blocks 81-1 can be an integral structure that is interconnected.
  • Forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein each circuit unit is provided with a plurality of vias, as shown in FIG11.
  • the plurality of vias in each circuit unit of the display substrate include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, and a seventeenth via V17.
  • the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the first region of the first active layer onto the substrate.
  • the fourth, third, and second insulating layers within the first via V1 are etched away, exposing the surface of the first region of the first active layer.
  • the first via V1 is configured to allow a subsequently formed fifth connection electrode to be connected to the first region of the first active layer through the via.
  • the orthographic projection of the second via V2 onto the substrate is located within the range of the orthographic projection of the second region of the first active layer (which is also the first region of the second active layer) onto the substrate.
  • the fourth insulating layer, the third insulating layer, and the second insulating layer within the second via V2 are etched away, exposing the surface of the second region of the first active layer (which is also the first region of the second active layer).
  • the second via V2 is configured to allow a subsequently formed first connection electrode to be connected to the second region of the first active layer (which is also the first region of the second active layer) through the via.
  • the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the first region of the fourth active layer onto the substrate.
  • the fourth insulating layer, the third insulating layer, and the second insulating layer within the third via V3 are etched away, exposing the surface of the first region of the fourth active layer.
  • the third via V3 is configured to allow a subsequently formed third connection electrode to be connected to the first region of the fourth active layer through the via.
  • the orthographic projection of the fourth via V4 onto the substrate is located within the range of the orthographic projection of the second region of the fourth active layer (which is also the first region of the ninth active layer) onto the substrate.
  • the fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away, exposing the surface of the second region of the fourth active layer (which is also the first region of the ninth active layer).
  • the fourth via V4 is configured to allow a subsequently formed second connection electrode to be connected to the second region of the fourth active layer (which is also the first region of the ninth active layer) through the via.
  • the orthographic projection of the fifth via V5 onto the substrate is within the range of the orthographic projection of the first region of the fifth active layer onto the substrate.
  • the fourth, third, and second insulating layers within the fifth via V5 are etched away, exposing the surface of the first region of the fifth active layer.
  • the fifth via V5 is configured to allow subsequently formed power connection lines to be connected to the first region of the fifth active layer through the via.
  • the orthographic projection of the sixth via V6 onto the substrate is located within the orthographic projection of the second region of the sixth active layer (which is also the second region of the seventh active layer) onto the substrate.
  • the fourth, third, and second insulating layers within the sixth via V6 are etched away, exposing the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer).
  • the sixth via V6 is configured to allow a subsequently formed fourth connection electrode to be connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the via.
  • the orthographic projection of the seventh via V7 onto the substrate is within the range of the orthographic projection of the first region of the seventh active layer onto the substrate.
  • the fourth, third, and second insulating layers within the seventh via V7 are etched away, exposing the surface of the first region of the seventh active layer.
  • the seventh via V7 is configured to allow a subsequently formed second initial signal line to be connected to the first region of the seventh active layer through the via.
  • the orthographic projection of the eighth via V8 onto the substrate is within the range of the orthographic projection of the first region of the eighth active layer onto the substrate.
  • the fourth, third, and second insulating layers within the eighth via V8 are etched away, exposing the surface of the first region of the eighth active layer.
  • the eighth via V8 is configured to allow a subsequently formed third initial signal line to be connected to the first region of the eighth active layer through the via.
  • the orthographic projection of the ninth via V9 on the substrate is within the range of the orthographic projection of the first initial connection block 81-1 on the substrate of the first initial signal line 81.
  • the fourth insulating layer in the ninth via V9 is etched away, exposing the surface of the first initial connection block 81-1.
  • the ninth via V9 is configured to allow the subsequently formed fifth connection electrode to be connected to the first initial connection block 81-1 through the via.
  • the orthographic projection of the tenth via V10 onto the substrate is within the range of the orthographic projection of the first opening 75 of the third electrode plate 73 onto the substrate.
  • the fourth and third insulating layers within the tenth via V10 are etched away, exposing the surface of the first electrode plate 71.
  • the tenth via V10 is configured to allow the subsequently formed first connection electrode to be connected to the first electrode plate 71 through the via.
  • the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the second opening 76 of the fourth electrode plate 74 onto the substrate.
  • the fourth and third insulating layers within the eleventh via V11 are etched away, exposing the surface of the second electrode plate 72.
  • the eleventh via V11 is configured to allow a subsequently formed second connection electrode to be connected to the second electrode plate 72 through the via.
  • the orthographic projection of the twelfth via V12 on the substrate is within the range of the orthographic projection of the third electrode plate 73 on the substrate.
  • the fourth insulating layer within the twelfth via V12 is etched away, exposing the surface of the third electrode plate 73.
  • the twelfth via V12 is configured to allow a subsequently formed second connection electrode to be connected to the third electrode plate 73 through the via.
  • the orthographic projection of the thirteenth via V13 on the substrate is within the range of the orthographic projection of the fourth electrode plate 74 on the substrate.
  • the fourth insulating layer within the thirteenth via V13 is etched away, exposing the surface of the fourth electrode plate 74.
  • the thirteenth via V13 is configured to allow subsequently formed power connection lines to be connected to the fourth electrode plate 74 through the via.
  • the orthographic projection of the fourteenth via V14 on the substrate is within the range of the orthographic projections of the first gate electrode 21 and the second gate electrode 22 of the integral structure on the substrate.
  • the fourth and third insulating layers within the fourteenth via V14 are etched away, exposing the surfaces of the first gate electrode 21 and the second gate electrode 22.
  • the fourteenth via V14 is configured to allow the subsequently formed third scan signal line to be connected to the first gate electrode 21 and the second gate electrode 22 through the via.
  • the orthogonal projection of the fifteenth via V15 onto the substrate is within the range of the orthogonal projection of the fourth gate electrode 24 onto the substrate.
  • the fourth insulating layer and the third insulating layer within the fifteenth via V15 are etched away, exposing the surface of the fourth gate electrode 24.
  • the fifteenth via V15 is configured to allow the subsequently formed fourth scan signal line to be connected to the fourth gate electrode 24 through the via.
  • the orthographic projection of the sixteenth via V16 onto the substrate lies within the range of the orthographic projection of the eighth gate electrode 28 onto the substrate.
  • the fourth and third insulating layers within the sixteenth via V16 are etched away, exposing the surface of the eighth gate electrode 28.
  • the sixteenth via V16 is configured to allow the subsequently formed first scan signal line to pass through it.
  • the via is connected to the eighth gate electrode 28.
  • the orthogonal projection of the seventeenth via V17 onto the substrate is within the range of the orthogonal projection of the ninth gate electrode 29 onto the substrate.
  • the fourth and third insulating layers within the seventeenth via V17 are etched away, exposing the surface of the ninth gate electrode 29.
  • the seventeenth via V17 is configured to allow the subsequently formed second scan signal line to be connected to the ninth gate electrode 29 through the via.
  • forming the third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on a fourth insulating layer, as shown in Figures 12A and 12B, where Figure 12B is a schematic diagram of the third conductive layer in Figure 12A.
  • the third conductive layer may be referred to as a first source/drain metal (SD1) layer.
  • the third conductive layer pattern of multiple circuit units in the display substrate may include: a first scan signal line 31, a second scan signal line 32, a third scan signal line 33, a fourth scan signal line 34, a power connection line 36, a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a second initial signal line 82, and a third initial signal line 83.
  • the shape of the first scan signal line 31 can be a straight line or a broken line extending along the first direction X of the main body. It can be located on the side of the first initial signal line 81 away from the third electrode plate 73.
  • the first scan signal line 31 is connected to the eighth gate electrode 28 in each circuit unit through the sixteenth via V16, thus realizing that the first scan signal line 31 is connected to the gate electrode of the eighth transistor T8 in each circuit unit.
  • the first scan signal line 31 can control the conduction and disconnection of the eighth transistor T8.
  • the first scan signal line 31 in this unit row is also connected to the gate electrode of the seventh transistor T7 of each circuit unit in the previous unit row.
  • the first scan signal line 31 in this unit row can simultaneously control the conduction and disconnection of the seventh transistor T7 of each circuit unit in the previous unit row.
  • the first scan signal line 31 controlling the eighth transistor T8 in this unit row can be used as the fifth scan signal line controlling the seventh transistor T7 in the previous unit row, or the fifth scan signal line controlling the seventh transistor T7 in this unit row can be implemented by the first scan signal line 31 controlling the eighth transistor T8 in the next unit row.
  • the shape of the second scan signal line 32 can be a straight line or a broken line extending along the first direction X of the main body, and can be located on the side of the third electrode plate 73 away from the fourth electrode plate 74.
  • the second scan signal line 32 is connected to the ninth gate electrode 29 in each circuit unit through the seventeenth via V17, thus realizing that the second scan signal line 32 is connected to the gate electrode of the ninth transistor T9 in each circuit unit.
  • the second scan signal line 32 can control the conduction and disconnection of the ninth transistor T9.
  • a scan connecting strip 32-1 may be provided on the second scan signal line 32, and the scan connecting strip 32-1 may be provided in each circuit unit.
  • the shape of the scan connecting strip 32-1 may be a strip shape extending along the second direction Y.
  • the first end of the scan connecting strip 32-1 is connected to the second scan signal line 32, and the second end of the scan connecting strip 32-1 extends towards the third electrode plate 73 and is connected to the ninth gate electrode 29 through the seventeenth via V17.
  • the second scan signal line 32 and the plurality of scan connecting strips 32-1 can be an integral structure that is interconnected.
  • the shape of the third scan signal line 33 can be a straight line or a broken line extending along the first direction X of the main body. It can be located on the side of the second scan signal line 32 away from the third electrode plate 73.
  • the third scan signal line 33 is connected to the first gate electrode 21 and the second gate electrode 22 of the integral structure in each circuit unit through the fourteenth via V14.
  • the third scan signal line 33 is connected to the gate electrode of the first transistor T1 and the gate electrode of the second transistor T2 in each circuit unit.
  • the third scan signal line 33 can control the first transistor T1 and the second transistor T2. T2 can be turned on and off simultaneously.
  • the shape of the fourth scan signal line 34 can be a straight line or a broken line extending along the first direction X of the main body, and can be located between the third scan signal line 33 and the first initial signal line 81.
  • the fourth scan signal line 34 is connected to the fourth gate electrode 24 in each circuit unit through the fifteenth via V15, thus realizing that the fourth scan signal line 34 is connected to the gate electrode of the fourth transistor T4 in each circuit unit.
  • the fourth scan signal line 34 can control the conduction and disconnection of the fourth transistor T4.
  • the power connection line 36 can be a straight line or a broken line extending along the first direction X, and can be located on the side of the light-emitting signal line 35 away from the third electrode plate 73.
  • the power connection line 36 is connected to the fourth electrode plate 74 in each circuit unit via the thirteenth via V13, and to the first region of the fifth active layer in each circuit unit via the fifth via V5. Since the power connection line 36 is configured to connect to the subsequently formed first power line, the first power line can write the first power signal into the first electrode and the fourth electrode plate 74 of the fifth transistor T5 in each circuit unit.
  • the power connection line 36 is also configured to connect to the subsequently formed first power line to form a mesh-like interconnected structure.
  • the orthographic projection of the power connection line 36 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate 74 on the substrate.
  • a power connection block 36-1 may be provided on the power connection line 36.
  • the power connection block 36-1 may be block-shaped (such as rectangular) and connected to the power connection line 36.
  • the power connection block 36-1 is configured to connect to the fourth electrode plate 74 through the thirteenth via V13 and to connect to the first power line formed subsequently.
  • a power connection strip 36-2 may be provided on the power connection line 36, and the power connection strip 36-2 may be provided in each circuit unit.
  • the shape of the power connection strip 36-2 may be a strip shape extending along the second direction Y. The first end of the power connection strip 36-2 is connected to the power connection line 36, and the second end of the power connection strip 36-2 extends toward the first region of the fifth active layer and is connected to the first region of the fifth active layer through the fifth via V5.
  • the power connection cable 36, the power connection block 36-1, and the power connection strip 36-2 can be an integral structure that is interconnected.
  • the shape of the second initial signal line 82 can be a straight line or a broken line extending along the first direction X of the main body, and can be located on the side of the power connection line 36 away from the third electrode plate 73.
  • the second initial signal line 82 is connected to the first region of the seventh active layer in each circuit unit through the seventh via V7, thus realizing the connection of the second initial signal line 82 to the first electrode of the seventh transistor T7.
  • the second initial signal line 82 can write the second initial signal to the first electrode of the seventh transistor T7.
  • the orthographic projection of the second initial signal line 82 onto the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate 74 onto the substrate.
  • a second initial connection block 82-1 is provided on the second initial signal line 82.
  • the second initial connection block 82-1 may be block-shaped (such as rectangular) and connected to the second initial signal line 82.
  • the second initial connection block 82-1 is configured to connect to the second initial connection line formed subsequently.
  • the second initial connection block 82-1 may be disposed in the circuit unit of the N+2th unit column.
  • the shape of the third initial signal line 83 can be a straight line or a broken line extending along the first direction X of the main body. It can be located on the side of the first scan signal line 31 away from the third electrode plate 73.
  • the third initial signal line 83 is connected to the first region of the eighth active layer in each circuit unit through the eighth via V8, thus realizing the connection of the third initial signal line 83 to the first electrode of the eighth transistor T8.
  • the third initial signal line 83 can write the third initial signal into the first electrode of the eighth transistor T8.
  • a third initial connection block 83-1 is provided on the third initial signal line 83.
  • the third initial connection block 83-1 may be block-shaped (such as rectangular) and connected to the third initial signal line 83.
  • the third initial connection block 83-1 is configured to connect to the subsequently formed third initial connection line.
  • the third initial signal line 83 may be disposed in the circuit cell of the N+1th cell column.
  • the first connecting electrode 41 can be a strip shape in which the main body extends along the second direction Y, and can be disposed between the second scan signal line 32 and the light emission signal line 35.
  • the first end of the first connecting electrode 41 is connected to the second region of the first active layer (which is also the first region of the second active layer) through the second via V2, and the second end of the first connecting electrode 41 is connected to the first electrode plate 71 through the tenth via V10. Since the first electrode plate 71 serves as the gate electrode of the third transistor T3, the first connecting electrode 41 realizes the interconnection between the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 71 of the first capacitor.
  • the first connecting electrode 41 can serve as the first node N1 of the pixel driving circuit.
  • the second connecting electrode 42 can be a strip shape in which the main body extends along the second direction Y, and can be disposed between the second scan signal line 32 and the power connection line 36.
  • the first end of the second connecting electrode 42 is connected to the second region of the fourth active layer (also the first region of the ninth active layer) through the fourth via V4, and the second end of the second connecting electrode 42 is connected to the second electrode plate 72 through the eleventh via V11.
  • the position between the first and second ends of the second connecting electrode 42 is connected to the third electrode plate 73 through the twelfth via V12.
  • the second connecting electrode 42 realizes the interconnection between the second electrode of the fourth transistor T4, the first electrode of the ninth transistor T9, the third electrode plate 73 of the first capacitor, and the second electrode plate 72 of the second capacitor.
  • the second connecting electrode 42 can serve as the fifth node N5 of the pixel driving circuit.
  • the third connection electrode 43 may be block-shaped (such as rectangular) and may be located between the fourth scan signal line 34 and the first initial signal line 81.
  • the third connection electrode 43 is connected to the first region of the fourth active layer through the third via V3 and is configured to be connected to the subsequently formed data signal line.
  • the fourth connection electrode 44 may be block-shaped (such as rectangular) and may be located between the light-emitting signal line 35 and the power connection line 36.
  • the fourth connection electrode 44 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the sixth via V6.
  • the fourth connection electrode 44 is configured to be connected to the anode connection electrode formed subsequently.
  • the fifth connection electrode 45 can be block-shaped (e.g., rectangular) and can be located between the first scan signal line 31 and the fourth scan signal line 34.
  • the first end of the fifth connection electrode 45 is connected to the first region of the first active layer through a first via V1
  • the second end of the fifth connection electrode 45 is connected to the first initial connection block 81-1 through a ninth via V9. Since the first initial connection block 81-1 is connected to the first initial signal line 81, the first initial signal line 81 is connected to the first electrode of the first transistor T1, and the first initial signal line 81 can write the first initial signal to the first electrode of the first transistor T1.
  • the fifth connection electrode 45 in at least one circuit unit is also configured to connect to a subsequently formed first initial connection line.
  • the first electrode plate 71 since the first electrode plate 71 has the potential of the first node N1 of the pixel driving circuit and the third electrode plate 73 has the potential of the fifth node N5 of the pixel driving circuit, the first electrode plate 71 (the first end of the first capacitor) having the potential of the first node N1 and the third electrode plate 73 (the second end of the first capacitor) having the potential of the fifth node N5 form the first capacitor of the pixel driving circuit.
  • the fourth electrode 74 is connected to the power connection line 36, which is configured to be connected to the subsequently formed first power line.
  • the fourth electrode 74 has the potential of the first power line, and thus the fourth electrode 74 (the first end of the second capacitor) having the potential of the first power line and the second electrode 72 (the second end of the second capacitor) having the potential of the fifth node N5 form the second capacitor of the pixel driving circuit.
  • forming a first planarization layer pattern may include: coating a first planarization film on a substrate on which the aforementioned pattern is formed, and patterning the first planarization film using a patterning process to form a first planarization layer covering a third conductive layer, wherein a plurality of vias are provided on the first planarization layer in each circuit unit, as shown in FIG13.
  • the plurality of vias in each circuit unit of the display substrate includes at least: a thirty-first via. V31, the thirty-second via V32, and the thirty-third via V33.
  • the orthographic projection of the 31st via V31 on the substrate is within the range of the orthographic projection of the power connection block 36-1 of the power connection line 36 on the substrate.
  • the first planarization layer within the 31st via V31 is removed, exposing the surface of the power connection block 36-1.
  • the 31st via V31 is configured to allow the subsequently formed first power line to pass through the via and connect to the power connection block 36-1.
  • the orthographic projection of the 32nd via V32 on the substrate is within the range of the orthographic projection of the third connecting electrode 43 on the substrate.
  • the first planarization layer within the 32nd via V32 is removed, exposing the surface of the third connecting electrode 43.
  • the 32nd via V32 is configured to allow subsequently formed data signal lines to be connected to the third connecting electrode 43 through the via.
  • the orthographic projection of the 33rd via V33 on the substrate is within the range of the orthographic projection of the fourth connecting electrode 44 on the substrate.
  • the first planarization layer within the 33rd via V33 is removed, exposing the surface of the fourth connecting electrode 44.
  • the 33rd via V33 is configured to allow a subsequently formed anode connecting electrode to be connected to the fourth connecting electrode 44 through the via.
  • At least one circuit unit may further include a thirty-fourth via V34.
  • the orthographic projection of the thirty-fourth via V34 onto the substrate lies within the range of the orthographic projection of the fifth connecting electrode 45 onto the substrate.
  • the first planarization layer within the thirty-fourth via V34 is removed, exposing the surface of the fifth connecting electrode 45.
  • the thirty-fourth via V34 is configured to allow a subsequently formed first initial connection line to be connected to the fifth connecting electrode 45 through the via.
  • the thirty-fourth via V34 may be disposed in the circuit cell of the Nth cell column.
  • At least one circuit unit may further include a thirty-fifth via V35.
  • the orthographic projection of the thirty-fifth via V35 onto the substrate lies within the range of the orthographic projection of the second initial connection block 82-1 onto the substrate.
  • the first planarization layer within the thirty-fifth via V35 is removed, exposing the surface of the second initial connection block 82-1.
  • the thirty-fifth via V35 is configured to allow subsequently formed second initial connection lines to connect to the second initial connection block 82-1 through the via.
  • the thirty-fifth via V35 may be disposed in the circuit cell of the N+2th cell column.
  • At least one circuit unit may further include a thirty-sixth via V36.
  • the orthographic projection of the thirty-sixth via V36 onto the substrate lies within the range of the orthographic projection of the third initial connection block 83-1 of the third initial signal line 83 onto the substrate.
  • the first planarization layer within the thirty-sixth via V36 is removed, exposing the surface of the third initial connection block 83-1.
  • the thirty-sixth via V36 is configured to allow subsequently formed third initial connection lines to be connected to the third initial connection block 83-1 through the via.
  • the thirty-sixth via V36 may be disposed in the circuit cell of the N+1th cell column.
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on a first planarization layer, as shown in Figures 14A and 14B, where Figure 14B is a schematic diagram of the fourth conductive layer in Figure 14A.
  • the fourth conductive layer may be referred to as a second source/drain metal (SD2) layer.
  • the fourth conductive layer pattern of multiple circuit units in the display substrate may include: a first power line 51, a data signal line 52, and an anode connection electrode 53.
  • the shape of the first power line 51 can be a straight line or a broken line extending along the second direction Y of the main body.
  • the first power line 51 is connected to the power connection block 36-1 through the thirty-first via V31. Since the power connection block 36-1 is connected to the power connection line 36, the power connection line 36 extending along the first direction X of the main body and the first power line 51 extending along the second direction Y of the main body are interconnected.
  • the first power line 51 and the power connection line 36 form a mesh-like interconnected structure on the display substrate for transmitting the first power signal. This not only effectively reduces the resistance of the first power line and reduces the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improving display uniformity and enhancing display quality.
  • the power connection line 36 of the third conductive layer can be disposed in each cell row, and the first power line 51 of the fourth conductive layer can be disposed in each cell column.
  • Multiple first power lines 51 are respectively connected to multiple power connection lines 36 to form a mesh-like interconnected structure for transmitting the first power signal.
  • the orthographic projection of the first power line 51 on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode 41 on the substrate. Since the first connecting electrode 41 serves as the first node N1 in the pixel driving circuit, the constant voltage of the first power line 51 can effectively shield the influence of other signals in the pixel driving circuit on the first node N1, preventing other signals (such as data voltage jumps) from affecting the potential of the first node N1 of the pixel driving circuit, thus improving the display effect.
  • the orthographic projection of the first power line 51 on the substrate at least partially overlaps with the orthographic projection of the second connecting electrode 42 on the substrate. Since the second connecting electrode 42 serves as the fifth node N5 in the pixel driving circuit, the constant voltage of the first power line 51 can effectively shield the influence of other signals in the pixel driving circuit on the fifth node N5, preventing other signals from affecting the potential of the fifth node N5 in the pixel driving circuit and improving the display effect.
  • the first power line 51 can be designed with non-uniform width.
  • the non-uniform width design of the first power line 51 not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the first power line and the data signal line.
  • the data signal line 52 can be a straight line or a broken line extending along the second direction Y of the main body.
  • the data signal line 52 is connected to the third connection electrode 43 through the thirty-second via V32. Since the third connection electrode 43 is connected to the first region of the fourth active layer through the via, the data signal line 52 writes the data signal to the first electrode of the fourth transistor T4.
  • the anode connection electrode 53 can be block-shaped (e.g., rectangular), and is connected to the fourth connection electrode 44 via the thirty-third via V33. Since the fourth connection electrode 44 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) via the via, the anode connection electrode 53 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In this exemplary embodiment, the anode connection electrode 53 is configured to connect to a subsequently formed anode, thus enabling the pixel driving circuit to drive the light-emitting device.
  • At least one circuit unit may further include a first initial connection line 84.
  • the shape of the first initial connection line 84 may be a straight line or a broken line extending along the second direction Y of the main body portion.
  • the first initial connection line 84 is connected to the fifth connection electrode 45 through the thirty-fourth via V34. Since the fifth connection electrode 45 is connected to the first initial signal line 81, the first initial signal line 81 extending along the first direction X of the main body portion and the first initial connection line 84 extending along the second direction Y of the main body portion are interconnected.
  • the first initial signal line 81 and the first initial connection line 84 form a mesh-like interconnected structure on the display substrate for transmitting the first initial signal. This not only effectively reduces the resistance of the first initial connection line and reduces the voltage drop of the first initial signal, but also effectively improves the uniformity of the first initial signal in the display substrate, effectively improving display uniformity, display quality, and display performance.
  • the first initial signal line 81 of the second conductive layer can be disposed in each cell row, and the first initial connection line 84 of the fourth conductive layer can be disposed every two cell columns.
  • the multiple first initial connection lines 84 are respectively connected to the multiple first initial signal lines 81 to form a mesh-like interconnected structure for transmitting the first initial signal.
  • the first initial connection line 84 may be provided in the circuit cell of the Nth cell column.
  • At least one circuit unit may further include a second initial connection line 85.
  • the shape of the second initial connection line 85 may be a straight line or a broken line extending along the second direction Y of the main body portion.
  • the second initial connection line 85 is connected to the second initial connection block 82-1 through a thirty-fifth via V35. Since the second initial connection block 82-1 is connected to the second initial signal line 82, the interconnection of the second initial signal line 82 extending along the first direction X of the main body portion and the second initial connection line 85 extending along the second direction Y of the main body portion is realized.
  • the second initial signal line 82 and the second initial connection line 85 form a mesh-like interconnected structure on the display substrate for transmitting the second initial signal. This not only effectively reduces the resistance of the second initial connection line and reduces the voltage drop of the second initial signal, but also effectively improves the display performance.
  • the uniformity of the second initial signal in the display substrate is improved, which effectively enhances display uniformity and improves display quality.
  • the second initial signal line 82 of the third conductive layer can be disposed in each cell row, and the second initial connection line 85 of the fourth conductive layer can be disposed every two cell columns.
  • Multiple second initial signal lines 82 are respectively connected to multiple second initial connection lines 85 to form a mesh-like interconnected structure for transmitting the second initial signal.
  • the second initial connection line 85 may be provided in the circuit cell of the N+2th cell column.
  • At least one circuit unit may further include a third initial connection line 86.
  • the shape of the third initial connection line 86 may be a straight line or a broken line extending along the second direction Y of the main body portion.
  • the third initial connection line 86 is connected to the third initial connection block 83-1 through the thirty-sixth via V36. Since the third initial connection block 83-1 is connected to the third initial signal line 83, the interconnection between the third initial signal line 83 extending along the first direction X of the main body portion and the third initial connection line 86 extending along the second direction Y of the main body portion is realized.
  • the third initial signal line 83 and the third initial connection line 86 form a mesh-like interconnected structure on the display substrate for transmitting the third initial signal. This not only effectively reduces the resistance of the third initial connection line and reduces the voltage drop of the third initial signal, but also effectively improves the uniformity of the third initial signal in the display substrate, effectively improving display uniformity, display quality, and display performance.
  • the third initial signal line 83 of the third conductive layer can be disposed in each cell row, and the third initial connection line 86 of the fourth conductive layer can be disposed every two cell columns.
  • Multiple third initial signal lines 83 are respectively connected to multiple third initial connection lines 86 to form a mesh-like interconnected structure for transmitting the third initial signal.
  • the third initial connection line 86 may be provided in the circuit cell of the N+1th cell column.
  • Subsequent fabrication processes may include forming a second planarization layer pattern, on which a plurality of anode vias are provided.
  • the orthographic projection of the anode vias onto the substrate is within the range of the orthographic projection of the anode connection electrode onto the substrate.
  • the second planarization layer within the anode vias is removed to expose the surface of the anode connection electrode.
  • the anode vias are configured to allow the subsequently formed anode to be connected to the anode connection electrode through the vias.
  • the driving circuit layer has been fabricated on the substrate.
  • a light-emitting structure layer and an encapsulation structure layer can be fabricated sequentially on the driving circuit layer, which will not be elaborated here.
  • the driving circuit layer may include multiple circuit units. At least one circuit unit may include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a fifth scan signal line, a light emission signal line, a first initial signal line, a second initial signal line, a third initial signal line, a first power supply line, and a data signal line connected to the pixel driving circuit.
  • the driving circuit layer may include at least a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planarization layer, a fourth conductive layer, and a second planarization layer sequentially stacked on the substrate.
  • the semiconductor layer may include at least a first active layer to a ninth active layer
  • the first conductive layer may include at least a first gate electrode, a second gate electrode, a fourth gate electrode, a seventh gate electrode, an eighth gate electrode, a ninth gate electrode, a gate connection line, a light-emitting signal line, a first electrode plate and a second electrode plate
  • the second conductive layer may include at least a third electrode plate, a fourth electrode plate and a first initial signal line
  • the third conductive layer may include at least a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a second initial signal line, a third initial signal line and a plurality of connection electrodes
  • the fourth conductive layer may include at least a first power line, a data signal line and an anode connection electrode.
  • the substrate can be a flexible substrate or a rigid substrate.
  • the rigid substrate can be, but is not limited to, one or more of glass and quartz
  • the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the flexible substrate can include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer.
  • the materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc.
  • the materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen.
  • the semiconductor layer can be amorphous silicon (a-Si).
  • the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo/Cu/Mo.
  • the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers.
  • the first planarization layer and the second planarization layer can be made of organic materials, such as resin.
  • the active layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc. That is, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • hexathiophene hexathiophene
  • polythiophene etc. That is, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, or organic technology.
  • An exemplary embodiment of this disclosure provides a display substrate.
  • a pixel driving circuit composed of nine transistors and two capacitors, it not only separates the compensation stage and data writing stage, enabling faster data signal writing and effectively ensuring the charge amount of the writing capacitor, but also effectively avoids uneven image quality issues in high-frequency displays and low grayscale images.
  • capacitor self-discharge to sample the threshold voltage in the compensation stage, it effectively avoids problems such as insufficient threshold compensation of the driving transistor, improves the compensation effect, and can support higher frame rate displays.
  • the first transistor T1 and the second transistor T2 are connected to the same scan signal line, and the first transistor T1 and the second transistor T2 share one of the sub-gate electrodes.
  • the display substrate has a power connection line extending along the first direction X and a first power line extending along the second direction Y in the main body.
  • the first power line and the first power connection line are interconnected to form a mesh-like interconnected structure on the display substrate. This not only effectively reduces the resistance of the first power line and the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, thereby improving display uniformity and display quality.
  • the present invention discloses a display substrate by setting a first initial signal line extending along a first direction X and a first initial connection line extending along a second direction Y in the main body portion, and the first initial signal line and the first initial connection line are interconnected to form a mesh-like interconnected structure on the display substrate. This not only effectively reduces the resistance of the first initial signal line and reduces the voltage drop of the first initial signal, but also effectively improves the uniformity of the first initial signal in the display substrate, thereby improving display uniformity, display quality, and display performance.
  • a second initial signal line extending along a first direction X and a second initial connection line extending along a second direction Y are provided on the main body portion, and the second initial signal line and the second initial connection line are interconnected to form a mesh-like interconnected structure on the display substrate.
  • a third initial signal line extending along the first direction X and a third initial connection line extending along the second direction Y of the main body are provided, and the third initial signal line and the third initial connection line are interconnected to form a mesh-like interconnected structure on the display substrate.
  • the preparation process disclosed herein is well compatible with existing preparation processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.
  • Figure 15 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • the pixel driving circuit of this embodiment can be a 9T2C structure, and the main structure is basically the same as that of the embodiment shown in Figure 4. The difference is that in this embodiment, the first terminal of the first transistor T1 and the first terminal of the seventh transistor T7 are connected to each other and are both connected to the second initial signal line INIT2. The second terminal of the seventh transistor T7 is connected to the fourth node N4.
  • the pixel driving circuit is connected to 10 signal lines, namely, a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, a fifth scan signal line S5, a light emission signal line EM, a second initial signal line INIT2, a third initial signal line INIT3, a data signal line DATA, and a first power supply line VDD.
  • this embodiment omits the first initial signal line, or it merges two initial signal lines into one.
  • the driving timing of the pixel driving circuit in this embodiment is basically the same as the driving timing shown in FIG5, and the driving current is also basically the same. The difference is that when the second stage B is completed, the potential of the fifth node N5 is Vint2+
  • Figure 16 is a schematic diagram of the planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • the main structure of the display substrate in this embodiment is basically the same as that in the embodiment shown in Figure 6.
  • the gate electrode of the first transistor T1 and the gate electrode of the second transistor T2 are connected to the same third scan signal line 33.
  • the gate electrode of the seventh transistor T7 in the circuit unit of this unit row is connected to the first scan signal line 31 in the next unit row.
  • the gate electrode of the eighth transistor T8 in the circuit unit of this unit row is connected to the first scan signal line 31 in this unit row.
  • the first electrode of the first transistor T1 and the first electrode of the seventh transistor T7 are connected to each other and are both connected to the second initial signal line 82. That is, the second conductive layer in this embodiment does not have a first initial signal line, and the fourth conductive layer does not have a first initial connection line.
  • the fabrication process of the display substrate may include the following operations.
  • the process of forming a semiconductor layer pattern and the resulting semiconductor layer pattern are substantially the same as those shown in FIG. 6. The difference is that, in this embodiment, the first region 11-1 of the first active layer of the circuit unit in this unit row is disposed in the circuit unit of the previous unit row and is interconnected with the first region 17-1 of the seventh active layer of the circuit unit in the previous unit row; or, the first region 11-1 of the first active layer of the circuit unit in the next unit row is disposed in the circuit unit of this unit row and the first region 17-1 of the seventh active layer of the circuit unit in this unit row is interconnected, as shown in FIG. 17.
  • the first region 11-1 of the first active layer can be used as the first region 17-1 of the seventh active layer and configured to be connected to the subsequently formed second initial signal line.
  • FIG. 18B is a schematic diagram of the first conductive layer in FIG. 18A.
  • FIG. 19B is a schematic diagram of the second conductive layer in FIG. 19A.
  • the process of forming the fourth insulating layer pattern and the plurality of vias formed are substantially the same as the scheme shown in FIG6, except that the plurality of vias of each circuit unit include at least the second via V2 to the eighth via V8, and the tenth via V10 to the seventeenth via V17, as shown in FIG20.
  • the seventh via V7 of the circuit unit in this unit row can serve as the first via of the circuit unit in the next unit row. Since the second conductive layer does not have a first initial signal line, this embodiment does not have a ninth via.
  • FIG. 21B is a schematic diagram of the third conductive layer in FIG. 21A.
  • the shape of the second initial signal line 82 can be a straight line or a broken line extending along the first direction X of the main body.
  • the second initial signal line 82 is connected to the first region of the seventh active layer (also the first region of the first active layer) in each circuit unit through the seventh via V7, thus realizing that the second initial signal line 82 can...
  • the second initial signal is written to the first terminal of the first transistor T1 and the first terminal of the seventh transistor T7.
  • a second initial connection block 82-1 is provided on the second initial signal line 82, and the second initial connection block 82-1 can be provided in the circuit unit of the Nth unit column and the N+2th unit column.
  • the shape of the third initial signal line 83 can be a straight line or a broken line extending along the first direction X of the main body.
  • the third initial signal line 83 is connected to the first region of the eighth active layer in each circuit unit through the eighth via V8, thereby enabling the third initial signal line 83 to write the third initial signal into the first pole of the eighth transistor T8.
  • a third initial connection block 83-1 is provided on the third initial signal line 83, and the third initial signal line 83 can be provided in the circuit unit of the N+1th unit column.
  • first planarization layer pattern Forming a first planarization layer pattern.
  • the process of forming the first planarization layer pattern and the multiple vias formed are substantially the same as those shown in FIG. 6, except that a thirty-fourth via is not provided on the first planarization layer, as shown in FIG. 22.
  • the 35th via V35 exposes the surface of the second initial connection block 82-1, and the 35th via V35 may be disposed in the circuit cells of the Nth and N+2nd cell columns.
  • the thirty-sixth via V36 exposes the surface of the third initial connection block 83-1, and the thirty-sixth via V36 may be disposed in the circuit cell of the N+1th cell column.
  • FIG. 23B is a schematic diagram of the fourth conductive layer in FIG. 23A.
  • the second initial connection line 85 is connected to the second initial connection block 82-1 through the thirty-fifth via V35, thereby realizing a mesh-like interconnection structure on the display substrate for transmitting the second initial signal by forming a mesh-like structure between the second initial signal line 82 and the second initial connection line 85.
  • the second initial signal line 82 of the third conductive layer can be provided in each cell row, and the second initial connection line 85 of the fourth conductive layer can be provided every other cell column.
  • the second initial connection line 85 may be disposed in the circuit cells of the Nth and N+2th cell columns.
  • the third initial connection line 86 is connected to the third initial connection block 83-1 through the thirty-sixth via V36, thereby realizing a mesh-like interconnection structure for transmitting the third initial signal formed on the display substrate by the third initial signal line 83 and the third initial connection line 86.
  • the third initial signal line 83 of the third conductive layer can be provided in each cell row, and the third initial connection line 86 of the fourth conductive layer can be provided every other cell column.
  • the third initial connection line 86 may be provided in the circuit cell of the N+1th cell column.
  • Subsequent fabrication processes may include forming a second planarization layer pattern, and sequentially fabricating a light-emitting structure layer and an encapsulation structure layer.
  • the formation process and pattern are basically the same as those shown in Figure 6, and will not be described in detail here.
  • the exemplary embodiments disclosed herein provide a display substrate that not only has the technical effects of the scheme shown in FIG6, but also optimizes the layout space and reduces the area occupied by the pixel driving circuit by reducing one initial signal line, which is beneficial to achieving high resolution.
  • Figure 24 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • the pixel driving circuit of this embodiment can be a 9T2C structure, and its main structure is basically the same as that of the embodiment shown in Figure 15. The difference is that the second terminal of the fourth transistor T4 in this embodiment is connected to the second node N2.
  • connection structure of the first node N1, the third node N3, and the fourth node N4 is basically the same as that shown in Figures 4 and 15.
  • the difference is that the second node N2 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, the second terminal of the fifth transistor T5, the second terminal of the eighth transistor T8, and the second terminal of the ninth transistor T9, respectively.
  • the fifth node N5 is connected to the first terminal of the ninth transistor T9, the first terminal of the fourth transistor T4, the second terminal of the fifth transistor T5, the second terminal of the eighth transistor T8, and the second terminal of the ninth transistor T9, respectively.
  • the second terminal of capacitor C1 is connected to the second terminal of capacitor C2.
  • the driving timing of the pixel driving circuit is basically the same as that shown in Figure 5, and the driving current is also basically the same.
  • the difference is that during the data writing stage, the second scan signal line S2 and the fourth scan signal line S4 are low-level signals, the fourth transistor T4 and the ninth transistor T9 are synchronously turned on, and the data signal line writes the data signal to the fifth node N5. Therefore, the pulse width of the low-level signal of the second scan signal line S2 in this embodiment is correspondingly widened.
  • Figure 25 is a schematic diagram of the planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • the main structure of the display substrate in this embodiment is basically the same as that in the embodiment shown in Figure 16.
  • the gate electrode of the first transistor T1 and the gate electrode of the second transistor T2 are connected to the same third scan signal line 33.
  • the gate electrode of the seventh transistor T7 in the circuit unit of this unit row is connected to the first scan signal line 31 in the next unit row.
  • the gate electrode of the eighth transistor T8 in the circuit unit of this unit row is connected to the first scan signal line 31 in this unit row.
  • the first electrode of the first transistor T1 and the first electrode of the seventh transistor T7 are connected to each other and are both connected to the second initial signal line 82.
  • the difference is that the connection relationship between the fourth transistor T4 and the ninth transistor T9 is different in this embodiment.
  • the fabrication process of the display substrate may include the following operations.
  • the process of forming a semiconductor layer pattern and the formed semiconductor layer pattern are basically the same as the scheme shown in FIG16.
  • the difference is that the first region 19-1 of the ninth active layer in this embodiment can be set separately, and the first region 13-1 of the third active layer can simultaneously serve as the second region 14-2 of the fourth active layer, the second region 15-2 of the fifth active layer, the second region 18-2 of the eighth active layer and the second region 19-2 of the ninth active layer, forming the second node N2 of the pixel driving circuit, as shown in FIG26.
  • the process of forming the first conductive layer pattern and the formed first conductive layer pattern are basically the same as those shown in FIG16.
  • the shape of the fourth gate electrode 24 can be a strip shape extending along the first direction X
  • the area where the fourth gate electrode 24 overlaps with the fourth active layer can be used as the gate electrode of the fourth transistor T4
  • the shape of the ninth gate electrode 29 can be "L" shaped
  • the area where the ninth gate electrode 29 overlaps with the ninth active layer can be used as the gate electrode of the ninth transistor T9 in a dual-gate structure, as shown in FIG27A and FIG27B.
  • FIG27B is a schematic diagram of the first conductive layer in FIG27A.
  • the process of forming the second conductive layer pattern and the formed second conductive layer pattern are substantially the same as the scheme shown in FIG16, as shown in FIG28A and FIG28B, FIG28B being a schematic diagram of the second conductive layer in FIG28A.
  • the process of forming the fourth insulating layer pattern and the plurality of vias formed are substantially the same as the scheme shown in FIG16, except that the orthographic projection of the fourth via V4 on the substrate is within the range of the orthographic projection of the first region of the ninth active layer on the substrate, and the fourth via V4 is configured to allow the subsequently formed second connection electrode to be connected to the first region of the ninth active layer through the via, as shown in FIG29.
  • the process of forming the third conductive layer pattern and the formed third conductive layer pattern are basically the same as the scheme shown in FIG16. The difference is that the first end of the second connecting electrode 42 is connected to the first region of the ninth active layer through the fourth via V4, the second end of the second connecting electrode 42 is connected to the second electrode plate 72 through the eleventh via V11, and the position between the first end and the second end of the second connecting electrode 42 is connected to the third electrode plate 73 through the twelfth via V12.
  • FIG30B is a schematic diagram of the third conductive layer in FIG30A.
  • Subsequent fabrication processes may include forming patterns of the first planarization layer, the fourth conductive layer, and the second planarization layer, as well as sequentially fabricating the light-emitting structure layer and the encapsulation structure layer.
  • the formation process and patterns are basically the same as those shown in Figure 16, and will not be described in detail here.
  • Figure 31 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • the pixel driving circuit of this embodiment can be a 9T2C structure, and its main structure is basically the same as that of the embodiment shown in Figure 4, except that...
  • the gate electrode of the seventh transistor T7 in the circuit unit of this unit row is connected to the first scan signal line 31 in this unit row. That is, the seventh transistor T7 and the eighth transistor T8 in the circuit unit of this unit row are connected to the same scan signal line, i.e., connected to the same first scan signal line 31.
  • the driving timing of the pixel driving circuit in this embodiment is basically the same as that shown in FIG5, and the driving current is also basically the same.
  • the first stage A further includes the seventh transistor T7 being turned on, and the second initial signal of the second initial signal line INIT2 being written to the fourth node N4 to initialize the fourth node N4 (light-emitting device).
  • the seventh transistor T7 and the eighth transistor T8 are turned on at the same time and turned off at the same time.
  • Figure 32 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • the pixel driving circuit of this embodiment can be a 9T2C structure, and the main structure is basically the same as that of the embodiment shown in Figure 15.
  • the gate electrode of the seventh transistor T7 of the circuit unit in this unit row is connected to the first scan signal line 31 in this unit row. That is, the seventh transistor T7 and the eighth transistor T8 of the circuit unit in this unit row are connected to the same scan signal line, i.e., connected to the same first scan signal line 31.
  • the driving timing of the pixel driving circuit in this embodiment is basically the same as that shown in FIG5, and the driving current is also basically the same.
  • the first stage A further includes the seventh transistor T7 being turned on, and the second initial signal of the second initial signal line INIT2 being written to the fourth node N4 to initialize the fourth node N4 (light-emitting device).
  • the seventh transistor T7 and the eighth transistor T8 are turned on at the same time and turned off at the same time.
  • Figure 33 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • the pixel driving circuit of this embodiment can be a 9T2C structure, and the main structure is basically the same as that of the embodiment shown in Figure 4. The difference is that in this embodiment, the gate electrode of the second transistor T2 is connected to the third scan signal line S3, the first electrode of the second transistor T2 is connected to the second initial signal line INIT2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the third transistor T3, and the first terminal of the first capacitor C1, respectively.
  • the structures of the other nodes are basically the same as those in the embodiment shown in FIG4.
  • the driving timing of the pixel driving circuit in this embodiment is basically the same as that shown in FIG5, and the driving current is also basically the same, which will not be described again here.
  • Figure 34 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • the pixel driving circuit of this embodiment can be a 9T2C structure, and the main structure is basically the same as that of the embodiment shown in Figure 33.
  • the difference is that the gate electrode of the seventh transistor T7 of the circuit unit in this unit row is connected to the first scan signal line 31 in this unit row. That is, the seventh transistor T7 and the eighth transistor T8 of the circuit unit in this unit row are connected to the same scan signal line, i.e., connected to the same first scan signal line 31.
  • the driving timing of the pixel driving circuit in this embodiment is basically the same as that shown in FIG5, and the driving current is also basically the same.
  • the first stage A further includes the seventh transistor T7 being turned on, and the second initial signal of the second initial signal line INIT2 being written to the fourth node N4 to initialize the fourth node N4 (light-emitting device).
  • the seventh transistor T7 and the eighth transistor T8 are turned on at the same time and turned off at the same time.
  • Figure 35 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • the pixel driving circuit of this embodiment can be a 9T2C structure, and the main structure is basically the same as that of the embodiment shown in Figure 4.
  • the difference is that the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 can be oxide transistors, and the other transistors are low-temperature polysilicon transistors.
  • low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors (OPTs) have advantages such as low leakage current.
  • This disclosure integrates LTPS and OPTs onto a single display substrate to form an LTPS+Oxide (LTPO) display substrate, leveraging the advantages of both to achieve low-temperature polysilicon transistors (LTPS) and OPTs. Frequency driving can reduce power consumption and improve display quality.
  • the driving timing of the pixel driving circuit in this embodiment is basically the same as the driving timing shown in Figure 5.
  • the corresponding driving signals are inverted, and the driving current is also basically the same, which will not be described again here.
  • Figure 36 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • the pixel driving circuit of this embodiment can be a 9T2C structure, and the main structure is basically the same as that of the embodiment shown in Figure 24.
  • the difference is that the first transistor T1, the second transistor T2 and the ninth transistor T9 can be oxide transistors, and the other transistors are low-temperature polysilicon transistors.
  • the driving timing of the pixel driving circuit in this embodiment is basically the same as the driving timing shown in Figure 5.
  • the corresponding driving signals are inverted, and the driving current is also basically the same, which will not be described again here.
  • the embodiments shown in Figures 15, 31, 32, 33, and 34 may also employ an LTPO structure, wherein at least one or more of the first transistor T1, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are oxide transistors, and the other transistors are low-temperature polysilicon transistors. This disclosure does not limit the implementation.
  • the embodiment shown in FIG24 may also employ a structure in which the gate electrode of the seventh transistor T7 in the circuit unit of this unit row is connected to the first scan signal line 31 in this unit row, and the first electrode of the second transistor T2 is connected to the second initial signal line INIT2, etc.
  • This disclosure does not limit it.
  • the display substrate disclosed herein can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.
  • pixel driving circuits such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc.
  • the display substrate includes a plurality of circuit units forming a plurality of cell rows and a plurality of cell columns.
  • At least one circuit unit includes a pixel driving circuit.
  • the pixel driving circuit includes at least a first capacitor, a second capacitor, a first transistor, a fourth transistor, an eighth transistor, a ninth transistor, and a third transistor as a driving transistor.
  • the second electrode of the first transistor is connected to the gate electrode of the third transistor and the first terminal of the first capacitor, respectively.
  • the first electrode of the ninth transistor is connected to the second terminal of the first capacitor and the second terminal of the second capacitor, respectively.
  • the second electrode of the ninth transistor is connected to the first electrode of the third transistor and the second electrode of the eighth transistor, respectively.
  • the first electrode of the fourth transistor is connected to a data signal line.
  • the display substrate is configured to display corresponding display content, the display content including a plurality of display frames, at least one display frame including a refresh frame, the refresh frame including at least a compensation stage and a data writing stage performed sequentially, and the compensation stage sampling a threshold voltage by capacitor self-discharge.
  • the refresh frame includes at least an initialization phase, a compensation phase, and a data writing phase;
  • the eighth transistor and the ninth transistor are turned on, the third initial signal of the third initial signal line is written into the second terminal of the first capacitor and the second terminal of the second capacitor, and the second capacitor is charged.
  • the first transistor is turned on to initialize the gate electrode of the third transistor.
  • the first capacitor and the second capacitor discharge through the turned-on ninth transistor and the turned-on third transistor, so that the voltage difference across the first capacitor is
  • the fourth transistor is turned on, and the data signal of the data signal line is written to the second terminal of the first capacitor and the second terminal of the second capacitor.
  • the pixel driving circuit further includes a second transistor, the first terminal of which is connected to the second terminal of the first transistor, the gate electrode of the third transistor, and the first terminal of the first capacitor, respectively; the second terminal of the second transistor is connected to the second terminal of the third transistor; in the compensation phase, the first...
  • the first capacitor and the second capacitor discharge through the turned-on ninth transistor, the turned-on third transistor, and the turned-on second transistor.
  • the pixel driving circuit further includes a second transistor, the first terminal of which is connected to a second initial signal line, and the second terminal of which is connected to the second terminal of the third transistor; during the compensation phase, the second transistor is turned on, and the first capacitor and the second capacitor discharge through the turned-on ninth transistor, the turned-on third transistor, and the turned-on second transistor.
  • the pixel driving circuit further includes a seventh transistor, the first terminal of which is connected to a second initial signal line, and the second terminal of which is connected to the light-emitting device; during the initialization phase, the seventh transistor is turned on, and the second initial signal of the second initial signal line initializes the light-emitting device; or, during the compensation phase, the seventh transistor is turned on, and the second initial signal of the second initial signal line initializes the light-emitting device.
  • At least one display frame further includes a hold frame, the hold frame including at least an adjustment phase;
  • the eighth transistor is turned on, and the third initial signal of the third initial signal line is written into the first terminal of the third transistor to adjust the bias state of the third transistor.
  • the pixel driving circuit further includes a seventh transistor, the first terminal of which is connected to a second initial signal line, and the second terminal of which is connected to the light-emitting device; during the adjustment phase, the seventh transistor is turned on, and the second initial signal of the second initial signal line initializes the light-emitting device.
  • the exemplary embodiments of this disclosure provide a driving method for a display substrate, which not only separates the compensation stage and the data writing stage, but also enables the sampling of the threshold voltage by capacitor self-discharge in the compensation stage, which can realize the writing of data signals faster, support higher frame rate displays, and improve the compensation effect.
  • the driving method of the display substrate disclosed herein can effectively improve the hysteresis of the third transistor by applying a DC signal to the first electrode of the third transistor, which is beneficial for image retention improvement and low-frequency display support, and thus improves the display effect.
  • the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

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Abstract

一种显示基板及其驱动方法、显示装置。显示基板包括多个电路单元，电路单元至少包括像素驱动电路，像素驱动电路至少包括第一电容(C1)、第二电容(C2)、第一晶体管(T1)、第三晶体管(T3)、第八晶体管(T8)和第九晶体管(T9)，第一晶体管(T1)的第二极分别与第三晶体管(T3)的栅电极和第一电容(C1)的第一端连接，第九晶体管(T9)的第一极分别与第一电容(C1)的第二端和第二电容(C2)的第二端连接，第九晶体管(T9)的第二极分别与第三晶体管(T3)的第一极和第八晶体管(T8)的第二极连接。

Description

显示基板及其驱动方法、显示装置 技术领域
本文涉及但不限于显示技术领域，具体涉及一种显示基板及其驱动方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路，所述像素驱动电路至少包括第一电容、第二电容、第一晶体管、第四晶体管、第八晶体管、第九晶体管、以及作为驱动晶体管的第三晶体管，所述第一晶体管的第二极分别与所述第三晶体管的栅电极和所述第一电容的第一端连接，所述第九晶体管的第一极分别与所述第一电容的第二端和所述第二电容的第二端连接，所述第九晶体管的第二极分别与所述第三晶体管的第一极和所述第八晶体管的第二极连接，所述第四晶体管的第一极与数据信号线连接。
在示例性实施方式中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极分别与所述第一晶体管的第二极、所述第三晶体管的栅电极和所述第一电容的第一端连接，所述第二晶体管的第二极与所述第三晶体管的第二极连接。
在示例性实施方式中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极与第二初始信号线连接，所述第二晶体管的第二极与所述第三晶体管的第二极连接。
在示例性实施方式中，所述第一晶体管和所述第二晶体管连接同一条扫描信号线。
在示例性实施方式中，在垂直于显示基板的方向上，所述显示基板至少包括设置在基底上的第一栅金属层、设置在所述第一栅金属层远离所述基底一侧的第二栅金属层、以及设置在所述第二栅金属层远离所述基底一侧的第一源漏金属层，所述第一晶体管的栅电极和所述第二晶体管的栅电极设置在所述第一栅金属层中，所述扫描信号线设置在所述第一源漏金属层中。
在示例性实施方式中，所述第一晶体管的栅电极和所述第二晶体管的栅电极为相互连接的一体结构。
在示例性实施方式中，所述第一晶体管和所述第二晶体管为双栅结构，所述第一晶体管的栅电极包括第一子栅电极和第三子栅电极，所述第二晶体管的栅电极包括第二子栅电极和第三子栅电极，所述第一晶体管和所述第二晶体管共用所述第三子栅电极。
在示例性实施方式中，所述第一子栅电极和所述第二子栅电极的形状为沿着第一方向延伸的条形状，所述第三子栅电极的形状为沿着第二方向延伸的条形状，所述第一方向和所述第二方向交叉；所述第一子栅电极和所述第二子栅电极设置在所述第三子栅电极所述第一方向的一侧，所述第一子栅电极设置在所述第三子栅电极所述第二方向的反方向的一侧，所述第二子栅电极设置在所述第三子栅电极所述第二方向的一侧，形成“C”字形状。
在示例性实施方式中，所述第四晶体管的第二极与所述所述第九晶体管的第一极连 接，或者，所述第四晶体管的第二极与所述所述第九晶体管的第二极连接。
在示例性实施方式中，所述第一晶体管的第一极与第一初始信号线连接，所述像素驱动电路还包括第七晶体管，所述第七晶体管的第一极与第二初始信号线连接，所述第七晶体管的第二极与所述发光器件连接；本单元行中电路单元的第七晶体管的栅电极和第八晶体管的栅电极与本单元行中的第一扫描信号线连接。
在示例性实施方式中，所述第一晶体管的第一极与第一初始信号线连接，所述像素驱动电路还包括第七晶体管，所述第七晶体管的第一极与第二初始信号线连接，所述第七晶体管的第二极与所述发光器件连接；本单元行中电路单元的第七晶体管的栅电极与下一单元行中的第一扫描信号线连接，本单元行中电路单元的第八晶体管的栅电极与本单元行中的第一扫描信号线连接。
在示例性实施方式中，所述像素驱动电路还包括第七晶体管，所述第七晶体管的第一极分别与所述第一晶体管的第一极和第二初始信号线连接，所述第七晶体管的第二极与所述发光器件连接；本单元行中电路单元的第七晶体管的栅电极和第八晶体管的栅电极与本单元行中的第一扫描信号线连接。
在示例性实施方式中，所述像素驱动电路还包括第七晶体管，所述第七晶体管的第一极分别与所述第一晶体管的第一极和第二初始信号线连接，所述第七晶体管的第二极与所述发光器件连接；本单元行中电路单元的第七晶体管的栅电极与下一单元行中的第一扫描信号线连接，本单元行中电路单元的第八晶体管的栅电极与本单元行中的第一扫描信号线连接。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板。
又一方面，本公开还提供了一种显示基板的驱动方法，所述显示基板包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路，所述像素驱动电路至少包括第一电容、第二电容、第一晶体管、第四晶体管、第八晶体管、第九晶体管、以及作为驱动晶体管的第三晶体管，所述第一晶体管的第二极分别与所述第三晶体管的栅电极和所述第一电容的第一端连接，所述第九晶体管的第一极分别与所述第一电容的第二端和所述第二电容的第二端连接，所述第九晶体管的第二极分别与所述第三晶体管的第一极和所述第八晶体管的第二极连接，所述第四晶体管的第一极与数据信号线连接；所述显示基板被配置为显示相应的显示内容，所述显示内容包括多个显示帧，至少一个显示帧包括刷新帧，所述刷新帧至少包括依次进行的补偿阶段和数据写入阶段，且所述补偿阶段通过电容自放电方式进行阈值电压的采样。
在示例性实施方式中，所述刷新帧至少包括初始化阶段、补偿阶段和数据写入阶段；
在所述初始化阶段，所述第八晶体管和所述第九晶体管导通，第三初始信号线的第三初始信号写入所述第一电容的第二端和所述第二电容的第二端，所述第二电容充电；
在所述补偿阶段，所述第一晶体管导通，对所述第三晶体管的栅电极进行初始化，所述第一电容和所述第二电容通过导通的第九晶体管和导通的第三晶体管放电，使所述第一电容两端的压差为|Vth|，Vth为所述第三晶体管的阈值电压；
在所述数据写入阶段，所述第四晶体管导通，所述数据信号线的数据信号写入所述第一电容的第二端和所述第二电容的第二端。
在示例性实施方式中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极分别与所述第一晶体管的第二极、所述第三晶体管的栅电极和所述第一电容的第一端连接，所述第二晶体管的第二极与所述第三晶体管的第二极连接；在所述补偿阶段，所述第二晶体管导通，所述第一电容和所述第二电容通过导通的第九晶体管、导通的第三晶体管和导通的第二晶体管放电。
在示例性实施方式中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一 极与第二初始信号线连接，所述第二晶体管的第二极与所述第三晶体管的第二极连接；在所述补偿阶段，所述第二晶体管导通，所述第一电容和所述第二电容通过导通的第九晶体管、导通的第三晶体管和导通的第二晶体管放电。
在示例性实施方式中，所述像素驱动电路还包括第七晶体管，所述第七晶体管的第一极与第二初始信号线连接，所述第七晶体管的第二极与所述发光器件连接；在所述初始化阶段，所述第七晶体管导通，所述第二初始信号线的第二初始信号对所述发光器件进行初始化，或者，在所述补偿阶段，所述第七晶体管导通，所述第二初始信号线的第二初始信号对所述发光器件进行初始化。
在示例性实施方式中，至少一个显示帧还包括保持帧，所述保持帧至少包括调整阶段；
在所述调整阶段，所述第八晶体管导通，第三初始信号线的第三初始信号写入所述第三晶体管的第一极，调整所述第三晶体管的偏压状态。
在示例性实施方式中，所述像素驱动电路还包括第七晶体管，所述第七晶体管的第一极与第二初始信号线连接，所述第七晶体管的第二极与所述发光器件连接；在所述调整阶段，所述第七晶体管导通，所述第二初始信号线的第二初始信号对所述发光器件进行初始化。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种显示基板的剖面结构示意图；
图4为本公开示例性实施例一种像素驱动电路的等效电路图；
图5为图4所示像素驱动电路的驱动时序图；
图6为本公开示例性实施例一种显示基板的平面结构示意图；
图7为本公开示例性实施例第一晶体管和第二晶体管的结构示意图；
图8为本公开一种显示基板形成半导体层图案后的示意图；
图9A和图9B为本公开一种显示基板形成第一导电层图案后的示意图；
图10A和图10B为本公开一种显示基板形成第二导电层图案后的示意图；
图11为本公开一种显示基板形成第四绝缘层图案后的示意图；
图12A和图12B为本公开一种显示基板形成第三导电层图案后的示意图；
图13为本公开一种显示基板形成第一平坦层图案后的示意图；
图14A和图14B为本公开一种显示基板形成第四导电层图案后的示意图；
图15为本公开示例性实施例另一种像素驱动电路的等效电路图；
图16为本公开示例性实施例另一种显示基板的平面结构示意图；
图17为本公开另一种显示基板形成半导体层图案后的示意图；
图18A和图18B为本公开另一种显示基板形成第一导电层图案后的示意图；
图19A和图19B为本公开另一种显示基板形成第二导电层图案后的示意图；
图20为本公开另一种显示基板形成第四绝缘层图案后的示意图；
图21A和图21B为本公开另一种显示基板形成第三导电层图案后的示意图；
图22为本公开另一种显示基板形成第一平坦层图案后的示意图；
图23A和图23B为本公开另一种显示基板形成第四导电层图案后的示意图；
图24为本公开示例性实施例又一种像素驱动电路的等效电路图；
图25为本公开示例性实施例又一种显示基板的平面结构示意图；
图26为本公开又一种显示基板形成半导体层图案后的示意图；
图27A和图27B为本公开又一种显示基板形成第一导电层图案后的示意图；
图28A和图28B为本公开又一种显示基板形成第二导电层图案后的示意图；
图29为本公开又一种显示基板形成第四绝缘层图案后的示意图；
图30A和图30B为本公开又一种显示基板形成第三导电层图案后的示意图；
图31为本公开示例性实施例又一种像素驱动电路的等效电路图；
图32为本公开示例性实施例又一种像素驱动电路的等效电路图；
图33为本公开示例性实施例又一种像素驱动电路的等效电路图；
图34为本公开示例性实施例又一种像素驱动电路的等效电路图；
图35为本公开示例性实施例又一种像素驱动电路的等效电路图；
图36为本公开示例性实施例又一种像素驱动电路的等效电路图。
附图标记说明:
11—第一有源层；            12—第二有源层；              13—第三有源层；
14—第四有源层；            15—第五有源层；              16—第六有源层；
17—第七有源层；            18—第八有源层；              19—第九有源层；
21—第一栅电极；            22—第二栅电极；              24—第四栅电极；
27—第七栅电极；            28—第八栅电极；              29—第九栅电极；
30—栅极连接线；            31—第一扫描信号线；          32—第二扫描信号线；
33—第三扫描信号线；        34—第四扫描信号线；          35—发光信号线；
36—电源连接线；            41—第一连接电极；            42—第二连接电极；
43—第三连接电极；          44—第四连接电极；            45—第五连接电极；
51—第一电源线；            52—数据信号线；              53—阳极连接电极；
71—第一极板；              72—第二极板；                73—第三极板；
74—第四极板；              75—第一开口；                76—第二开口；
81—第一初始信号线；        82—第二初始信号线；          83—第三初始信号线；
84—第一初始连接线；        85—第二初始连接线；          86—第三初始连接线；
101—基底；                 102—驱动电路层；             103—发光结构层；
104—封装结构层。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水 平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和发光单元，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、发光信号线和数据信号线连接，发光单元可以包括发光器件，发光器件与电路单元的像素驱动电路连接。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线DATA1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线DATA1至Dn，n可以是自然数。扫描驱动器可以通过从时序控 制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。在示例性实施方式中，像素阵列可以设置在显示基板上。
图2为一种显示基板的平面结构示意图。在示例性实施方式中，显示基板可以包括显示区域和位于显示区域周边的边框区域。如图2所示，显示基板的显示区域可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3。每个子像素可以包括电路单元和发光单元，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。发光单元可以至少包括发光器件，发光器件与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括四个子像素，四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。
图3为一种显示基板的剖面结构示意图，示意了显示基板中三个子像素的结构。如图4所示，在垂直于显示基板的平面上，显示基板的显示区域可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装结构层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。驱动电路层102可以包括多个电路单元，电路单元可以至少包括像素驱动电路，像素驱动电路可以包括多个晶体管和电容。发光结构层103可以包括多个发光单元，发光单元可以至少包括发光器件，发光器件可以包括阳极、有机发光层和阴极，阳极与像素驱动电路连接，有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。封装结构层104可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界水汽无法进入发光结构层103。
本公开示例性实施例提供了一种显示基板，包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路，所述像素驱动电路被配置为向所连接的发光器件输出驱动电流；所述像素驱动电路至少包括第一电容、第二电容、第一晶体管、第四晶体管、第八晶体管、第九晶体管、以及作为驱动晶体管的第三晶体管，所述第一晶 体管的第二极分别与所述第三晶体管的栅电极和所述第一电容的第一端连接，所述第九晶体管的第一极分别与所述第一电容的第二端和所述第二电容的第二端连接，所述第九晶体管的第二极分别与所述第三晶体管的第一极和所述第八晶体管的第二极连接，所述第四晶体管的第一极与数据信号线连接。
在一种示例性实施方式中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极分别与所述第一晶体管的第二极、所述第三晶体管的栅电极和所述第一电容的第一端连接，所述第二晶体管的第二极与所述第三晶体管的第二极连接。
在另一种示例性实施方式中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极与第二初始信号线连接，所述第二晶体管的第二极与所述第三晶体管的第二极连接。
在示例性实施方式中，所述第一晶体管和所述第二晶体管连接同一条扫描信号线。
在示例性实施方式中，所述第一晶体管的栅电极和所述第二晶体管的栅电极为相互连接的一体结构。
在示例性实施方式中，所述第一晶体管和所述第二晶体管为双栅结构，所述第一晶体管的栅电极包括第一子栅电极和第三子栅电极，所述第二晶体管的栅电极包括第二子栅电极和第三子栅电极，所述第一晶体管和所述第二晶体管共用所述第三子栅电极。
在示例性实施方式中，所述第四晶体管的第二极与所述所述第九晶体管的第一极连接，或者，所述第四晶体管的第二极与所述所述第九晶体管的第二极连接。
下面通过一些示例性实施例对本公开显示基板进行举例说明。
图4为本公开示例性实施例一种像素驱动电路的等效电路图。如图4所示，本公开示例性实施例的像素驱动电路可以为9T2C结构，可以包括9个晶体管(第一晶体管T1至第九晶体管T9)和2个电容(第一电容C1和第二电容C2)，像素驱动电路分别与11条信号线(第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、第四扫描信号线S4、第五扫描信号线S5、发光信号线EM、第一初始信号线INIT1、第二初始信号线INIT2、第三初始信号线INIT3、数据信号线DATA和第一电源线VDD)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2、第三节点N3、第四节点N4和第五节点N5。其中，第一节点N1分别与第一晶体管T1的第二极、第二晶体管T2的第一极、第三晶体管T3的栅电极和第一电容C1的第一端连接，第二节点N2分别与第三晶体管T3的第一极、第五晶体管T5的第二极、第八晶体管T8的第二极和第九晶体管T9的第二极连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接，第四节点N4分别与第六晶体管T6的第二极和第七晶体管T7的第二极连接，第五节点N5分别与第四晶体管T4的第二极、第九晶体管T9的第一极、第一电容C1的第二端和第二电容C2的第二端连接。
在示例性实施方式中，第一电容C1的第一端与第一节点N1连接，第一电容C1的第二端与第五节点N5连接，第二电容C2的第一端与第一电源线VDD连接，第二电容C2的第二端与第五节点N5连接。
在示例性实施方式中，第一晶体管T1可以称为第一初始化晶体管，第一晶体管T1的栅电极与第三扫描信号线S3连接，第一晶体管T1的第一极与第一初始信号线INIT1连接，第一晶体管的第二极与第一节点N1连接。
在示例性实施方式中，第二晶体管T2可以称为补偿晶体管，第二晶体管T2的栅电极与第三扫描信号线S3连接，第二晶体管T2的第一极与第一节点N1连接，第二晶体管T2的第二极与第三节点N3连接。
在示例性实施方式中，本公开的第一晶体管T1的栅电极和第二晶体管T2的栅电极连接同一条第三扫描信号线S3，第一晶体管T1和第二晶体管T2同时导通和同时断开。
在示例性实施方式中，第三晶体管T3可以称为驱动晶体管，第三晶体管T3的栅电极与第一节点N1连接，第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。
在示例性实施方式中，第四晶体管T4可以称为数据写入晶体管，第四晶体管T4的栅电极与第四扫描信号线S4连接，第四晶体管T4的第一极与数据信号线DATA连接，第四晶体管T4的第二极与第五节点N5连接。
在示例性实施方式中，第五晶体管T5可以称为第一发光控制晶体管，第五晶体管T5的栅电极与发光信号线EM连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第二节点N2连接。
在示例性实施方式中，第六晶体管T6可以称为第二发光控制晶体管，第六晶体管T6的栅电极与发光信号线EM连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与第四节点N4连接。
在示例性实施方式中，第七晶体管T7可以称为第二初始化晶体管，第七晶体管T7的栅电极与第五扫描信号线S5连接，第七晶体管T7的第一极与第二初始信号线INIT2连接，第七晶体管T7的第二极与第四节点N4连接。在示例性实施方式中，一个单元行中的第五扫描信号线S5可以是下一单元行中的第一扫描信号线S1，或者，一个单元行中的第一扫描信号线S1可以是上一单元行中的第五扫描信号线S5。
在示例性实施方式中，第八晶体管T8可以称为第三初始化晶体管，第八晶体管T8的栅电极与第一扫描信号线S1连接，第八晶体管T8的第一极与第三初始信号线INIT3连接，第八晶体管T8的第二极与第二节点N2连接。
在示例性实施方式中，第九晶体管T9可以称为充放电晶体管，第九晶体管T9的栅电极与第二扫描信号线S2连接，第九晶体管T9的第一极与第五节点N5连接，第九晶体管T9的第二极与第二节点N2连接。
在示例性实施方式中，发光器件EL可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。发光器件EL的第一极与第四节点N4连接，发光器件EL的第二极与第二电源线VSS连接。
在示例性实施方式中，第一电源线VDD的信号为持续提供的高电平信号，第二电源线VSS的信号为持续提供的低电平信号。
在示例性实施方式中，第一晶体管T1至第二晶体管T2、第四晶体管T4第九晶体管T9为开关晶体管。
在示例性实施方式中，第一晶体管T1至第九晶体管T9可以是低温多晶硅晶体管(P型晶体管)。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。
图5为图4所示像素驱动电路的驱动时序图。如图5所示，以第一晶体管T1至第九晶体管T9均为P型晶体管为例，像素驱动电路的工作过程可以包括：
第一阶段A，可以称为初始化阶段。该阶段中，第三扫描信号线S3、第四扫描信号线S4、第五扫描信号线S5和发光信号线EM的信号为高电平信号，第一扫描信号线S1和第二扫描信号线S2为低电平信号，第八晶体管T8和第九晶体管T9导通，其它开关晶体管断开。
第八晶体管T8导通使得第三初始信号线INIT3的第三初始信号写入第二节点N2，第九晶体管T9导通使得第二节点N2的信号写入第五节点N5，对第二电容C2进行充电。由于充电路径上第八晶体管T8和第九晶体管T9完全导通，因而充电会很快完成。本阶段完成时，第二节点N2和第五节点N5的电位为第三初始信号的电压Vint3。
第二阶段B，可以称为补偿阶段。该阶段中，第一扫描信号线S1、第四扫描信号线S4和发光信号线EM的信号为高电平信号，第二扫描信号线S2、第三扫描信号线S3和第五扫描信号线S5为低电平信号，第一晶体管T1、第二晶体管T2、第七晶体管T7和第九晶体管T9导通，其它开关晶体管断开。
第七晶体管T7导通使得第二初始信号线INIT2的第二初始信号写入第四节点N4，对第四节点N4(发光器件)进行初始化。第一晶体管T1导通使得第一初始信号线INIT1的第一初始信号写入第一节点N1，对第一节点N1(第三晶体管T3的栅电极和第一电容C1的第一端)进行初始化，第一节点N1的电位为第一初始信号的电压Vint1。由于第一初始信号的电压Vint1较低，因此第三晶体管T3导通。第二晶体管T2和第九晶体管T9导通使得第一电容C1和第二电容C2通过导通的第九晶体管T9、导通的第三晶体管T3和导通的第二晶体管T2放电，使得第五节点N5的电位逐渐降低，直到第三晶体管T3断开。本阶段完成时，第一电容C1两端的压差为|Vth|，第五节点N5的电位为Vint1+|Vth|，Vth为第三晶体管T3的阈值电压。
第三阶段C，可以称为数据写入阶段。该阶段中，第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、第五扫描信号线S5和发光信号线EM的信号为高电平信号，第四扫描信号线S4为低电平信号，第四晶体管T4导通，其它开关晶体管断开。
第四晶体管T4导通使得数据信号线的数据信号写入第五节点N5，由于第四晶体管T4完全导通，因此数据信号写入第五节点N5较快。本阶段完成时，第一电容C1两端的压差为|Vth|，第二电容C2的两端的压差为VDD-Vdata，第三晶体管T3栅电极和第一极两端的压差Vsg为第一电容C1和第二电容C2两端的压差之和，即Vsg＝Vdd-Vdata+|Vth|，Vdata为数据信号的电压，Vdd为第一电源线VDD的第一电源信号的电压。
第四阶段D，可以称为发光阶段。该阶段中，第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、第四扫描信号线S4和第五扫描信号线S5的信号为高电平信号，发光信号线EM为低电平信号，第五晶体管T5和第六晶体管T6导通，其它开关晶体管断开。
第五晶体管T5和第六晶体管T6导通使得第一电源线VDD的第一电源信号可以通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光器件EL提供驱动电流，驱动发光器件EL发光。驱动电流为：
IEL＝K(Vsg-|Vth|)2＝K(Vdd-Vdata+|Vth|-|Vth|)2＝K(Vdd-Vdata)2；
其中，K为与工艺和设计有关的常数。
第五阶段E，可以称为调整阶段。该阶段中，第二扫描信号线S2、第三扫描信号线S3、第四扫描信号线S4和发光信号线EM的信号为高电平信号，第一扫描信号线S1和第五扫描信号线S5为低电平信号，第七晶体管T7和第八晶体管T8导通，其它开关晶体管断开。
第七晶体管T7导通使得第二初始信号线INIT2的第二初始信号写入第四节点N4，对第四节点N4(发光器件)再次进行初始化。第八晶体管T8导通使得第三初始信号线INIT3的第三初始信号写入第二节点N2(第三晶体管T3的第一极)，以调整第三晶体管T3的偏压状态。由于第三晶体管T3(即驱动晶体管)长期处于一种状态时，电子会被俘获在陷阱中，造成磁滞。本阶段通过向第三晶体管T3的第一极施加直流信号，改变第二节点N2的电位，可以有效改善驱动晶体管的磁滞情况，有利于残像改善和支持低频显示，有利于提高显示效果。
在示例性实施方式中，本阶段中，第一扫描信号线S1可以在第一时刻从高电平信号变为低电平信号，并在第二时刻从低电平信号变为高电平信号，即第八晶体管T8在第一时刻导通，并在第二时刻断开。第五扫描信号线S5可以在第二时刻从高电平信号变为低 电平信号，并在第三时刻从低电平信号变为高电平信号，即第七晶体管T7在第二时刻导通，并在第三时刻断开。也就是说，本阶段先对发光器件进行初始化，然后调整第三晶体管T3的偏压状态。
第六阶段F，可以称为再次发光阶段。该阶段中，第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、第四扫描信号线S4和第五扫描信号线S5的信号为高电平信号，发光信号线EM为低电平信号，第五晶体管T5和第六晶体管T6导通，其它开关晶体管断开。
第五晶体管T5和第六晶体管T6导通使得第一电源线VDD的第一电源信号可以通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光器件EL提供驱动电流，驱动发光器件EL再次发光。
在示例性实施方式中，第一阶段A、第二阶段B、第三阶段C和第四阶段D可以组成刷新帧，可以用于高频显示(如90Hz和120Hz)的驱动，即高频显示需要第一阶段A至第四阶段D共四个阶段。第五阶段E和第六阶段F可以组成保持帧，刷新帧和保持帧一起可以用于低频显示(如60Hz)的驱动，即低频显示需要第一阶段A至第六阶段F共六个阶段。
本公开示例性实施例所提供的像素驱动电路的驱动方法，通过刷新帧至少包括依次进行的补偿阶段和数据写入阶段，即将补偿阶段和数据写入两个阶段分离，可以较快地实现数据信号的写入，因而可以支持更高帧频的显示。本公开通过在补偿阶段采用电容自放电方式进行阈值电压的采样，并将阈值电压保存在电容中，提高了补偿效果。本公开通过向第三晶体管的第一极施加直流信号，可以有效改善第三晶体管的磁滞情况，有利于残像改善和支持低频显示，有利于提高显示效果。
图6为本公开示例性实施例一种显示基板的平面结构示意图。在示例性实施方式中，显示基板可以包括设置在基底上的驱动电路层以及设置在驱动电路层远离基底一侧的发光结构层，驱动电路层可以至少包括多个电路单元，发光结构层至少包括多个发光单元，至少一个电路单元包括像素驱动电路，至少一个发光单元包括发光器件，发光器件与对应电路单元中的像素驱动电路连接，像素驱动电路被配置为向所连接的发光器件输出驱动电流。
在示例性实施方式中，本公开中所说的电路单元，是指按照像素驱动电路划分的区域，本公开中所说的发光单元，是指按照发光器件划分的区域。在示例性实施例中，发光单元在基底上正投影的位置与电路单元在基底上正投影的位置可以是对应的，或者，发光单元在基底上正投影的位置与电路单元在基底上正投影的位置可以是不对应的。
在示例性实施例中，沿着第一方向X依次设置的多个电路单元可以称为单元行，沿着第二方向Y依次设置的多个电路单元可以称为单元列，多个单元行和多个单元列构成阵列排布的电路单元阵列，第一方向X与第二方向Y交叉。
如图6所示，至少一个电路单元中，像素驱动电路可以与第一扫描信号线31、第二扫描信号线32、第三扫描信号线33、第四扫描信号线34、发光信号线35、第一电源线51、数据信号线52、第一初始信号线81、第二初始信号线82和第三初始信号线83连接。其中，与像素驱动电路连接的多条信号线可以位于相应电路单元内。
在示例性实施方式中，第一扫描信号线31、第二扫描信号线32、第三扫描信号线33、第四扫描信号线34、发光信号线35、第一初始信号线81、第二初始信号线82和第三初始信号线83的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，第一电源线51和数据信号线52的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状。
本公开中，A沿着B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿着B方向伸展，且主要部分沿着B 方向伸展的长度大于次要部分沿着其它方向伸展的长度。以下描述中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
在示例性实施方式中，至少一个像素驱动电路可以包括第一电容、第二电容和多个晶体管，多个晶体管可以包括作为第一初始化晶体管的第一晶体管T1、作为补偿晶体管的第二晶体管T2、作为驱动晶体管的第三晶体管T3、作为数据写入晶体管的第四晶体管T4、作为第一发光控制晶体管的第五晶体管T5、作为第二发光控制晶体管的第六晶体管T6、作为第二初始化晶体管的第七晶体管T7、作为第三初始化晶体管的第八晶体管T8、以及作为充放电晶体管的第九晶体管T9。其中，第一晶体管T1至第九晶体管T9可以为低温多晶硅晶体管。第一电容可以包括叠设的第一极板和第三极板，第二电容可以包括叠设的第二极板和第四极板。
在示例性实施方式中，第一晶体管T1的栅电极与第三扫描信号线33连接，第一晶体管T1的第一极与第一初始信号线81连接，第一晶体管T1的第二极分别与第二晶体管T2的第一极和第一电容的第一极板连接。第二晶体管T2的栅电极与第三扫描信号线33连接，第二晶体管T2的第二极分别与第三晶体管T3的第二极和第六晶体管T6的第一极连接。第三晶体管T3的栅电极可以作为第一电容的第一极板，第三晶体管T3的第一极分别与第五晶体管T5的第二极、第八晶体管T8的第二极和第九晶体管T9的第二极连接。第四晶体管T4的栅电极与第四扫描信号线34连接，第四晶体管T4的第一极与数据信号线52连接，第四晶体管T4的第二极分别与第九晶体管T9的第一极、第一电容的第三极板和第二电容的第二极板连接。第五晶体管T5的栅电极与发光信号线35连接，第五晶体管T5的第一极与第一电源线51连接。第六晶体管T6的栅电极与发光信号线35连接，第六晶体管T6的第二极与第七晶体管T7的第二极连接。第七晶体管T7的栅电极与第一扫描信号线31连接，第七晶体管T7的第一极与第二初始信号线82连接。第八晶体管T8的栅电极与第一扫描信号线31连接，第八晶体管T8的第一极与第三初始信号线83连接，第九晶体管T9的栅电极与第二扫描信号线32连接。
在示例性实施方式中，第七晶体管T7的栅电极与第一扫描信号线31连接、第八晶体管T8的栅电极与第一扫描信号线31连接是指：本单元行中电路单元的第七晶体管T7的栅电极与下一单元行中的第一扫描信号线31连接，本单元行中电路单元的第八晶体管T8的栅电极与本单元行中的第一扫描信号线31连接。
在示例性实施方式中，第一晶体管T1和第二晶体管T2连接同一条扫描信号线，即连接同一条第三扫描信号线33。
在示例性实施方式中，至少一个电路单元还可以包括电源连接线36。电源连接线36的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，沿着第一方向X延伸的电源连接线36和沿着第二方向Y延伸的第一电源线51相互连接，形成传输第一电源信号的网状连通结构。
在示例性实施方式中，至少一个电路单元还可以包括第一初始连接线84。第一初始连接线84的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，沿着第一方向X延伸的第一初始信号线81与沿着第二方向Y延伸的第一初始连接线84的相互连接，形成传输第一初始信号的网状连通结构。
在示例性实施方式中，至少一个电路单元还可以包括第二初始连接线85。第二初始连接线85的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，沿着第一方向X延伸的第二初始信号线82与沿着第二方向Y延伸的第二初始连接线85的相互连接，形成传输第二初始信号的网状连通结构。
在示例性实施方式中，至少一个电路单元还可以包括第三初始连接线86。第三初始连接线86的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，沿着第一方 向X延伸的第三初始信号线83与沿着第二方向Y延伸的第三初始连接线86的相互连接，形成传输第三初始信号的网状连通结构。
图7为本公开示例性实施例第一晶体管和第二晶体管的结构示意图。如图6和图7所示，第一晶体管T1可以至少包括第一有源层11、第一栅电极21、第一源电极(第一晶体管T1的第一极)和第一漏电极(第一晶体管T1的第二极)，第二晶体管T2可以至少包括第二有源层12、第二栅电极22、第二源电极(第二晶体管T2的第一极)和第二漏电极(第二晶体管T2的第二极)，且第一漏电极和第二源电极连接。
在示例性实施方式中，第一晶体管T1和第二晶体管T2均为双栅结构，均可以包括两个子有源层和两个子栅电极。
在示例性实施方式中，第一有源层11可以包括第一子有源层10-1和第三子有源层10-3，第一子有源层10-1的形状可以为沿着第二方向Y延伸的条形状，第三子有源层10-3的形状可以为沿着第一方向X延伸的条形状。在第一方向X上，第一子有源层10-1可以设置在第三子有源层10-3第一方向X的一侧，在第二方向Y上，第一子有源层10-1可以设置在第三子有源层10-3第二方向Y的反方向的一侧，且第一子有源层10-1和第三子有源层10-3相互靠近的一端相互连接，形成形状。
在示例性实施方式中，第二有源层12可以包括第二子有源层10-2和第三子有源层10-3，第二子有源层10-2的形状可以为沿着第二方向Y延伸的条形状。在第一方向X上，第二子有源层10-2可以设置在第三子有源层10-3第一方向X的一侧，在第二方向Y上，第二子有源层10-2可以设置在第三子有源层10-3第二方向Y的一侧，且第二子有源层10-2和第三子有源层10-3相互靠近的一端相互连接，形成形状。
在示例性实施方式中，由于第一子有源层10-1和第二子有源层10-2均与第三子有源层10-3连接，因而第一有源层11第二有源层12一起组成形状。
在示例性实施方式中，第三子有源层10-3既作为第一有源层11的一个子有源层，又作为第二有源层12的一个子有源层，即第一有源层11和第二有源层12共用同一个第三子有源层10-3。
在示例性实施方式中，第一有源层11第二有源层12可以为相互连接的一体结构。
在示例性实施方式中，第一栅电极21可以包括第一子栅电极20-1和第三子栅电极20-3，第一子栅电极20-1的形状可以为沿着第一方向X延伸的条形状，第一子栅电极20-1在基底上的正投影与第一子有源层10-1在基底上的正投影至少部分交叠，第三子栅电极20-3的形状可以为沿着第二方向Y延伸的条形状，第三子栅电极20-3在基底上的正投影与第三子有源层10-3在基底上的正投影至少部分交叠。在第一方向X上，第一子栅电极20-1可以设置在第三子栅电极20-3第一方向X的一侧，在第二方向Y上，第一子栅电极20-1可以设置在第三子栅电极20-3第二方向Y的反方向的一侧，且第一子栅电极20-1和第三子栅电极20-3相互靠近的一端相互连接，形成形状。
在示例性实施方式中，第二栅电极22可以包括第二子栅电极20-2和第三子栅电极20-3，第二栅电极22的形状可以为沿着第一方向X延伸的条形状，第二栅电极22在基底上的正投影与第二子有源层10-2在基底上的正投影至少部分交叠。在第一方向X上，第二子栅电极20-2可以设置在第三子栅电极20-3第一方向X的一侧，在第二方向Y上，第二子栅电极20-2可以设置在第三子栅电极20-3第二方向Y的一侧，且第二子栅电极20-2和第三子栅电极20-3相互靠近的一端相互连接，形成形状。
在示例性实施方式中，由于第一子栅电极20-1和第二子栅电极20-2均与第三子栅电极20-3连接，因而第一栅电极21和第二栅电极22一起组成“C”字形状。
在示例性实施方式中，第三子栅电极20-3既作为第一栅电极21的一个子栅电极，又作为第二栅电极22的一个子栅电极，即第一栅电极21和第二栅电极22共用同一个第三 子栅电极20-3。
在示例性实施方式中，第一栅电极21和第二栅电极22可以为相互连接的一体结构。
在示例性实施方式中，在垂直于显示基板的平面上，显示基板可以包括在基底上依次设置的半导体层、第一栅金属层、第二栅金属层、第一源漏金属层和第二源漏金属层。第一有源层11第二有源层12可以设置在半导体层中，第一栅电极21和第二栅电极22可以设置在第一栅金属层中，第三扫描信号线33可以设置在第一源漏金属层中，且第三扫描信号线33通过过孔与一体结构的第一栅电极21和第二栅电极22连接。
在示例性实施方式中，第一初始信号线81可以设置在第二栅金属中，第二初始信号线82和第三初始信号线83可以设置在第一源漏金属层中，第一初始连接线84、第二初始连接线85和第三初始连接线86可以设置在第二源漏金属层。
在示例性实施方式中，电源连接线36可以设置在第一源漏金属层中，第一电源线51可以设置在第二源漏金属层中。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以第M单元行中3个电路单元为例，本实施例显示基板的制备过程可以包括如下操作。
(11)形成半导体层图案。在示例性实施方式中，形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的半导体层，如图8所示。
在示例性实施方式中，显示基板中每个电路单元的半导体层可以至少包括：第一晶体管T1的第一有源层11、第二晶体管T2的第二有源层12、第三晶体管T3的第三有源层13、第四晶体管T4的第四有源层14、第五晶体管T5的第五有源层15、第六晶体管T6的第六有源层16、第七晶体管T7的第七有源层17、第八晶体管T8的第八有源层18和第九晶体管T9的第九有源层19，且第一有源层11至第九有源层19可以为相互连接的一体结构。
在示例性实施方式中，在第一方向X上，第一有源层11、第二有源层12、第六有源层16和第七有源层17可以位于第三有源层13第一方向X的一侧，第五有源层15和第八有源层18可以位于第三有源层13第一方向X的反方向的一侧。在第二方向Y上，第五有源层15、第六有源层16和第七有源层17可以位于第三有源层13第二方向Y的一侧，第一有源层11、第二有源层12、第四有源层14、第八有源层18和第九有源层19可以位于第三有源层13第二方向Y的反方向的一侧。
在示例性实施方式中，第三有源层13的形状可以呈倒“Ω”字形状，第一有源层11和第二有源层12的形状可以呈“L”字形状，第四有源层14、第五有源层15、第六有源层16、 第七有源层17和第八有源层18的形状可以呈“I”字形状，第九有源层19的形状可以呈“一”字形状。
在示例性实施方式中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第一有源层的第二区11-2和第二有源层的第一区12-1可以相互连接，第一有源层的第二区11-2可以作为第二有源层的第一区12-1。第三有源层的第一区13-1、第五有源层的第二区15-2、第八有源层的第二区18-2和第九有源层的第二区19-2可以相互连接，第三有源层的第一区13-1可以同时作为第五有源层的第二区15-2、第八有源层的第二区18-2和第九有源层的第二区19-2，构成像素驱动电路的第二节点N2。第二有源层的第二区12-2、第三有源层的第二区13-2和第六有源层的第一区16-1可以相互连接，第三有源层的第二区13-2可以同时作为第二有源层的第二区12-2和第六有源层的第一区16-1，构成像素驱动电路的第三节点N3。第四有源层的第二区14-2和第九有源层的第一区19-1可以相互连接，第四有源层的第二区14-2可以作为第九有源层的第一区19-1。第六有源层的第二区16-2和第七有源层的第二区17-2可以相互连接，第六有源层的第二区16-2可以作为第七有源层的第二区17-2，构成像素驱动电路的第四节点N4。第一有源层的第一区11-1、第四有源层的第一区14-1、第五有源层的第一区15-1、第七有源层的第一区17-1和第八有源层的第一区18-1可以单独设置。
在示例性实施方式中，第一晶体管T1为双栅结构，包括两个子有源层。第二晶体管T2为双栅结构，包括两个子有源层。
在示例性实施方式中，第一有源层11可以包括第一子有源层10-1和第三子有源层10-3，第一子有源层10-1的形状可以为沿着第二方向Y延伸的条形状，第三子有源层10-3的形状可以为沿着第一方向X延伸的条形状。在第一方向X上，第一子有源层10-1可以设置在第三子有源层10-3第一方向X的一侧，在第二方向Y上，第一子有源层10-1可以设置在第三子有源层10-3第二方向Y的反方向的一侧，且第一子有源层10-1和第三子有源层10-3相互靠近的一端相互连接，形成形状。
在示例性实施方式中，第二有源层12可以包括第二子有源层10-2和第三子有源层10-3，第二子有源层10-2的形状可以为沿着第二方向Y延伸的条形状。在第一方向X上，第二子有源层10-2可以设置在第三子有源层10-3第一方向X的一侧，在第二方向Y上，第二子有源层10-2可以设置在第三子有源层10-3第二方向Y的一侧，且第二子有源层10-2和第三子有源层10-3相互靠近的一端相互连接，形成形状。
在示例性实施方式中，由于第一子有源层10-1和第二子有源层10-2均与第三子有源层10-3连接，因而第一有源层11第二有源层12一起组成形状。
在示例性实施方式中，第三子有源层10-3既作为第一有源层11的一个子有源层，又作为第二有源层12的一个子有源层，即第一有源层11和第二有源层12共用同一个第三子有源层10-3。
在示例性实施方式中，第一半导体层可以采用多晶硅(p-Si)，即第一晶体管T1至第九晶体管T9为LTPS晶体管。在示例性实施方式中，通过图案化工艺对第一半导体薄膜进行图案化可以包括：先在第一绝缘薄膜上形成非晶硅(a-si)薄膜，对非晶硅薄膜进行脱氢处理，对脱氢处理后的非晶硅薄膜进行结晶处理，形成多晶硅薄膜。随后，对多晶硅薄膜进行图案化，形成第一半导体层图案。
(12)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，如图9A和图9B所示，图9B为图9A中第一导电层的示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，显示基板中每个电路单元的第一导电层图案至少包括：第一栅电极21、第二栅电极22、第四栅电极24、第七栅电极27、第八栅电极28、第九栅电极29、栅极连接线30、发光信号线35、第一电容的第一极板71和第二电容的第二极板72。
在示例性实施方式中，第一电容的第一极板71的形状可以为矩形状，矩形状的角部可以设置倒角或者凹槽，第一极板71在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影至少部分重叠，第一极板71可以同时作为第一电容的下极板和第三晶体管T3的栅电极。
在示例性实施方式中，第二电容的第二极板72的形状可以为矩形状，矩形状的角部可以设置倒角或者凹槽，可以位于第一极板71第二方向Y的一侧，第二极板72在基底上的正投影与半导体层在基底上的正投影没有交叠。在示例性实施方式中，第二极板72可以作为第二电容的下极板。
在示例性实施方式中，第一栅电极21可以位于第一极板71远离第二极板72的一侧，第一栅电极21与第一有源层相重叠的区域可以作为双栅结构的第一晶体管T1的栅电极。
在示例性实施方式中，第二栅电极22可以位于第一栅电极21和第一极板71之间，第二栅电极22与第二有源层相重叠的区域可以作为双栅结构的第二晶体管T2的栅电极。
在示例性实施方式中，第一栅电极21和第二栅电极22可以相互连接，形成“C”字形状，且双栅结构的第一晶体管T1和双栅结构的第二晶体管T2共用其中一个子栅电极。
在示例性实施方式中，第一栅电极21可以包括第一子栅电极20-1和第三子栅电极20-3，第一子栅电极20-1的形状可以为沿着第一方向X延伸的条形状，第一子栅电极20-1在基底上的正投影与第一子有源层10-1在基底上的正投影至少部分交叠，第三子栅电极20-3的形状可以为沿着第二方向Y延伸的条形状，第三子栅电极20-3在基底上的正投影与第三子有源层10-3在基底上的正投影至少部分交叠。在第一方向X上，第一子栅电极20-1可以设置在第三子栅电极20-3第一方向X的一侧，在第二方向Y上，第一子栅电极20-1可以设置在第三子栅电极20-3第二方向Y的反方向的一侧，且第一子栅电极20-1和第三子栅电极20-3相互靠近的一端相互连接，形成形状。
在示例性实施方式中，第二栅电极22可以包括第二子栅电极20-2和第三子栅电极20-3，第二栅电极22的形状可以为沿着第一方向X延伸的条形状，第二栅电极22在基底上的正投影与第二子有源层10-2在基底上的正投影至少部分交叠。在第一方向X上，第二子栅电极20-2可以设置在第三子栅电极20-3第一方向X的一侧，在第二方向Y上，第二子栅电极20-2可以设置在第三子栅电极20-3第二方向Y的一侧，且第二子栅电极20-2和第三子栅电极20-3相互靠近的一端相互连接，形成形状。
在示例性实施方式中，由于第一子栅电极20-1和第二子栅电极20-2均与第三子栅电极20-3连接，因而第一栅电极21和第二栅电极22一起组成“C”字形状。
在示例性实施方式中，第三子栅电极20-3既作为第一栅电极21的一个子栅电极，又作为第二栅电极22的一个子栅电极，即第一栅电极21和第二栅电极22共用同一个第三子栅电极20-3。
在示例性实施方式中，第一栅电极21和第二栅电极22可以为相互连接的一体结构。
在示例性实施方式中，第四栅电极24的形状可以呈“C”字形状，可以位于第一极板71远离第二极板72的一侧，第四栅电极24与第四有源层相重叠的区域可以作为双栅结构的第四晶体管T4的栅电极。
在示例性实施方式中，第七栅电极27的形状可以沿着第一方向X延伸的条形状，可以位于第一极板71第二方向Y的一侧，第七栅电极27与第七有源层相重叠的区域可以作为第七晶体管T7的栅电极。
在示例性实施方式中，第八栅电极28的形状可以沿着第一方向X延伸的条形状，可 以位于第四栅电极24远离第一极板71的一侧，第八栅电极28与第八有源层相重叠的区域可以作为第八晶体管T8的栅电极。
在示例性实施方式中，第九栅电极29的形状可以呈“U”字形状，可以位于第四栅电极24和第一极板71之间，第九栅电极29与第九有源层相重叠的区域可以作为双栅结构的第九晶体管T9的栅电极。
在示例性实施方式中，栅极连接线30的形状可以为沿着第二方向Y延伸的条形状，可以位于第七栅电极27远离第一极板71的一侧。栅极连接线30的第一端与本单元行中电路单元的第七栅电极27连接，栅极连接线30的第二端沿着第二方向Y延伸后，与下一单元行中电路单元的第八栅电极28连接，使得本单元行中的第七晶体管T7和下一单元行中的第八晶体管T8同时导通或者同时断开。或者，栅极连接线30的第一端与上一单元行中电路单元的第七栅电极27连接，栅极连接线30的第二端沿着第二方向Y延伸后，与本单元行中电路单元的第八栅电极28连接，使得上一单元行中的第七晶体管T7和本单元行中的第八晶体管T8同时导通或者同时断开。
在示例性实施方式中，本单元行中电路单元的第七栅电极27、下一单元行中电路单元的第八栅电极28以及栅极连接线30可以为相互连接的一体结构。或者，上一单元行中电路单元的第七栅电极27、本单元行中电路单元的第八栅电极28以及栅极连接线30可以为相互连接的一体结构。
在示例性实施方式中，发光信号线35的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，可以位于第一极板71和第二极板72之间，发光信号线35与第五有源层相重叠的区域可以作为第五晶体管T5的栅电极，发光信号线35与第六有源层相重叠的区域可以作为第六晶体管T6的栅电极。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管T1至第九晶体管T9的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一有源层至第九有源层的第一区和第二区均被导体化。
(13)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，如图10A和图10B所示，图10B为图10A中第二导电层的示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，显示基板中每个电路单元的第二导电层图案至少包括：第一电容的第三极板73、第二电容的第四极板74和第一初始信号线81。
在示例性实施方式中，第一电容的第三极板73的轮廓形状可以为矩形状，矩形状的角部可以设置倒角或者凹槽，第三极板73在基底上的正投影与第一极板71在基底上的正投影至少部分重叠，第三极板73可以作为第一电容的上极板，第一极板71和第三极板73构成像素驱动电路的第一电容。
在示例性实施方式中，第二电容的第四极板74的形状可以为矩形状，矩形状的角部可以设置倒角或者凹槽，第四极板74在基底上的正投影与第二极板72在基底上的正投影至少部分重叠，第四极板74可以作为第二电容的上极板，第二极板72和第四极板74构成像素驱动电路的第二电容。
在示例性实施方式中，每个电路单元的第三极板73上设置有第一开口75，第一开口75的形状可以为块形(如矩形等)状，可以位于第三极板73中的中部区域，使第三极板73形成环形结构。第一开口75暴露出覆盖第一极板71的第三绝缘层，且第一极板71在基底上的正投影包含第一开口75在基底上的正投影。在示例性实施方式中，第一开口75 被配置为容置后续形成的第十过孔，第十过孔位于第一开口75内并暴露出第一极板71，使后续形成的第一连接电极与第一极板71连接。
在示例性实施方式中，每个电路单元的第四极板74上设置有第二开口76，第二开口76的形状可以为块形(如矩形等)状，可以位于第四极板74靠近第三极板73的一侧。第二开口76暴露出覆盖第二极板72的第三绝缘层，且第二极板72在基底上的正投影包含第二开口76在基底上的正投影。在示例性实施方式中，第二开口76被配置为容置后续形成的第十一过孔，第十一过孔位于第二开口76内并暴露出第二极板72，使后续形成的第二连接电极与第二极板72连接。
在示例性实施方式中，第一初始信号线81的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，可以位于第四栅电极24和第八栅电极28之间。在示例性实施方式中，第一初始信号线81上可以设置有第一初始连接块81-1，第一初始连接块81-1可以设置在每个电路单元中，且与第一初始信号线81连接，第一初始连接块81-1被配置为通过后续形成的第五连接电极与第一有源层的第一区连接。
在示例性实施方式中，第一初始信号线81和多个第一初始连接块81-1可以为相互连接的一体结构。
(14)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上，沉积第四绝缘薄膜，采用图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层，每个电路单元中设置有多个过孔，如图11所示。
在示例性实施方式中，显示基板中每个电路单元的多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10、第十一过孔V11、第十二过孔V12、第十三过孔V13、第十四过孔V14、第十五过孔V15、第十六过孔V16和第十七过孔V17。
在示例性实施方式中，第一过孔V1在基底上的正投影位于第一有源层的第一区在基底上的正投影的范围之内，第一过孔V1内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第一区的表面，第一过孔V1被配置为使后续形成的第五连接电极通过该过孔与第一有源层的第一区连接。
在示例性实施方式中，第二过孔V2在基底上的正投影位于第一有源层的第二区(也是第二有源层的第一区)在基底上的正投影的范围之内，第二过孔V2内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第二区(也是第二有源层的第一区)的表面，第二过孔V2被配置为使后续形成的第一连接电极通过该过孔与第一有源层的第二区(也是第二有源层的第一区)连接。
在示例性实施方式中，第三过孔V3在基底上的正投影位于第四有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面，第三过孔V3被配置为使后续形成的第三连接电极通过该过孔与第四有源层的第一区连接。
在示例性实施方式中，第四过孔V4在基底上的正投影位于第四有源层的第二区(也是第九有源层的第一区)在基底上的正投影的范围之内，第四过孔V4内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第二区(也是第九有源层的第一区)的表面，第四过孔V4被配置为使后续形成的第二连接电极通过该过孔与第四有源层的第二区(也是第九有源层的第一区)连接。
在示例性实施方式中，第五过孔V5在基底上的正投影位于第五有源层的第一区在基底上的正投影的范围之内，第五过孔V5内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面，第五过孔V5被配置为使后续形成的电源连接线通过该过孔与第五有源层的第一区连接。
在示例性实施方式中，第六过孔V6在基底上的正投影位于第六有源层的第二区(也是第七有源层的第二区)在基底上的正投影的范围之内，第六过孔V6内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区(也是第七有源层的第二区)的表面，第六过孔V6被配置为使后续形成的第四连接电极通过该过孔与第六有源层的第二区(也是第七有源层的第二区)连接。
在示例性实施方式中，第七过孔V7在基底上的正投影位于第七有源层的第一区在基底上的正投影的范围之内，第七过孔V7内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区的表面，第七过孔V7被配置为使后续形成的第二初始信号线通过该过孔与第七有源层的第一区连接。
在示例性实施方式中，第八过孔V8在基底上的正投影位于第八有源层的第一区在基底上的正投影的范围之内，第八过孔V8内的第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第八有源层的第一区的表面，第八过孔V8被配置为使后续形成的第三初始信号线通过该过孔与第八有源层的第一区连接。
在示例性实施方式中，第九过孔V9在基底上的正投影位于第一初始信号线81的第一初始连接块81-1在基底上的正投影的范围之内，第九过孔V9内的第四绝缘层被刻蚀掉，暴露出第一初始连接块81-1的表面，第九过孔V9被配置为使后续形成的第五连接电极通过该过孔与第一初始连接块81-1连接。
在示例性实施方式中，第十过孔V10在基底上的正投影位于第三极板73的第一开口75在基底上的正投影的范围之内，第十过孔V10内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板71的表面，第十过孔V10被配置为使后续形成的第一连接电极通过该过孔与第一极板71连接。
在示例性实施方式中，第十一过孔V11在基底上的正投影位于第四极板74的第二开口76在基底上的正投影的范围之内，第十一过孔V11内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第二极板72的表面，第十一过孔V11被配置为使后续形成的第二连接电极通过该过孔与第二极板72连接。
在示例性实施方式中，第十二过孔V12在基底上的正投影位于第三极板73在基底上的正投影的范围之内，第十二过孔V12内的第四绝缘层被刻蚀掉，暴露出第三极板73的表面，第十二过孔V12被配置为使后续形成的第二连接电极通过该过孔与第三极板73连接。
在示例性实施方式中，第十三过孔V13在基底上的正投影位于第四极板74在基底上的正投影的范围之内，第十三过孔V13内的第四绝缘层被刻蚀掉，暴露出第四极板74的表面，第十三过孔V13被配置为使后续形成的电源连接线通过该过孔与第四极板74连接。
在示例性实施方式中，第十四过孔V14在基底上的正投影位于一体结构的第一栅电极21和第二栅电极22在基底上的正投影的范围之内，第十四过孔V14内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一栅电极21和第二栅电极22的表面，第十四过孔V14被配置为使后续形成的第三扫描信号线通过该过孔与第一栅电极21和第二栅电极22连接。
在示例性实施方式中，第十五过孔V15在基底上的正投影位于第四栅电极24在基底上的正投影的范围之内，第十五过孔V15内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第四栅电极24的表面，第十五过孔V15被配置为使后续形成的第四扫描信号线通过该过孔与第四栅电极24连接。
在示例性实施方式中，第十六过孔V16在基底上的正投影位于第八栅电极28在基底上的正投影的范围之内，第十六过孔V16内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第八栅电极28的表面，第十六过孔V16被配置为使后续形成的第一扫描信号线通过该 过孔与第八栅电极28连接。
在示例性实施方式中，第十七过孔V17在基底上的正投影位于第九栅电极29在基底上的正投影的范围之内，第十七过孔V17内的第四绝缘层和第三绝缘层被刻蚀掉，暴露出第九栅电极29的表面，第十七过孔V17被配置为使后续形成的第二扫描信号线通过该过孔与第九栅电极29连接。
(15)形成第三导电层图案。在示例性实施方式中，形成第三导电层可以包括：在形成前述图案的基底上，沉积第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成设置在第四绝缘层上的第三导电层，如图12A和图12B所示，图12B为图12A中第三导电层的示意图。在示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，显示基板中多个电路单元的第三导电层图案均可以包括：第一扫描信号线31、第二扫描信号线32、第三扫描信号线33、第四扫描信号线34、电源连接线36、第一连接电极41、第二连接电极42、第三连接电极43、第四连接电极44、第五连接电极45、第二初始信号线82和第三初始信号线83。
在示例性实施方式中，第一扫描信号线31的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，可以位于第一初始信号线81远离第三极板73的一侧，第一扫描信号线31通过第十六过孔V16与每个电路单元中的第八栅电极28连接，因而实现了第一扫描信号线31连接每个电路单元中的第八晶体管T8的栅电极，第一扫描信号线31可以控制第八晶体管T8的导通和断开。
在示例性实施方式中，由于本单元行中电路单元的第七栅电极27通过栅极连接线30与下一单元行中电路单元的第八栅电极28连接，或者，本单元行中电路单元的第八栅电极28通过栅极连接线30与上一单元行中电路单元的第七栅电极27连接，因而本单元行中的第一扫描信号线31还连接上一单元行中每个电路单元的第七晶体管T7的栅电极，本单元行中的第一扫描信号线31可以同时控制上一单元行中每个电路单元的第七晶体管T7的导通和断开。
在示例性实施方式中，本单元行中控制第八晶体管T8的第一扫描信号线31可以作为上一单元行中控制第七晶体管T7的第五扫描信号线，或者，本单元行中控制第七晶体管T7的第五扫描信号线是由下一单元行中控制第八晶体管T8的第一扫描信号线31实现的。
在示例性实施方式中，第二扫描信号线32的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，可以位于第三极板73远离第四极板74的一侧，第二扫描信号线32通过第十七过孔V17与每个电路单元中的第九栅电极29连接，因而实现了第二扫描信号线32连接每个电路单元中的第九晶体管T9的栅电极，第二扫描信号线32可以控制第九晶体管T9的导通和断开。
在示例性实施方式中，第二扫描信号线32上可以设置有扫描连接条32-1，扫描连接条32-1可以设置在每个电路单元中。扫描连接条32-1的形状可以为沿着第二方向Y延伸的条形状，扫描连接条32-1的第一端与第二扫描信号线32连接，扫描连接条32-1的第二端向着靠近第三极板73的方向延伸后，通过第十七过孔V17与第九栅电极29连接。
在示例性实施方式中，第二扫描信号线32和多个扫描连接条32-1可以为相互连接的一体结构。
在示例性实施方式中，第三扫描信号线33的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，可以位于第二扫描信号线32远离第三极板73的一侧，第三扫描信号线33通过第十四过孔V14与每个电路单元中一体结构的第一栅电极21和第二栅电极22连接，因而实现了第三扫描信号线33连接每个电路单元中的第一晶体管T1的栅电极和第二晶体管T2的栅电极，第三扫描信号线33可以控制第一晶体管T1和第二晶体管 T2的同时导通和同时断开。
在示例性实施方式中，第四扫描信号线34的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，可以位于第三扫描信号线33和第一初始信号线81之间，第四扫描信号线34通过第十五过孔V15与每个电路单元中的第四栅电极24连接，因而实现了第四扫描信号线34连接每个电路单元中的第四晶体管T4的栅电极，第四扫描信号线34可以控制第四晶体管T4的导通和断开。
在示例性实施方式中，电源连接线36的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，可以位于发光信号线35远离第三极板73的一侧，电源连接线36一方面通过第十三过孔V13与每个电路单元中的第四极板74连接，另一方面通过第五过孔V5与每个电路单元中的第五有源层的第一区连接。由于电源连接线36被配置为与后续形成的第一电源线连接，因而实现了第一电源线可以将第一电源信号写入每个电路单元中的第五晶体管T5的第一极和第四极板74。在示例性实施方式中，电源连接线36还被配置为与后续形成的第一电源线连接形成网状连通结构的结构。
在示例性实施方式中，电源连接线36在基底上的正投影与第四极板74在基底上的正投影至少部分交叠。
在示例性实施方式中，电源连接线36上可以设置有电源连接块36-1。电源连接块36-1的形状可以为块形(如矩形)状，且与电源连接线36连接，电源连接块36-1一方面被配置为通过第十三过孔V13与第四极板74连接，另一方面被配置为与后续形成的第一电源线连接。
在示例性实施方式中，电源连接线36上可以设置有电源连接条36-2，电源连接条36-2可以设置在每个电路单元中。电源连接条36-2的形状可以为沿着第二方向Y延伸的条形状，电源连接条36-2的第一端与电源连接线36连接，电源连接条36-2的第二端向着靠近第五有源层的第一区的方向延伸后，通过第五过孔V5与第五有源层的第一区连接。
在示例性实施方式中，电源连接线36、电源连接块36-1和电源连接条36-2可以为相互连接的一体结构。
在示例性实施方式中，第二初始信号线82的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，可以位于电源连接线36远离第三极板73的一侧，第二初始信号线82通过第七过孔V7与每个电路单元中的第七有源层的第一区连接，因而实现了第二初始信号线82连接第七晶体管T7的第一极，第二初始信号线82可以将第二初始信号写入第七晶体管T7的第一极。
在示例性实施方式中，第二初始信号线82在基底上的正投影与第四极板74在基底上的正投影至少部分交叠。
在示例性实施方式中，第二初始信号线82上设置有第二初始连接块82-1。第二初始连接块82-1的形状可以为块形(如矩形)状，且与第二初始信号线82连接，第二初始连接块82-1被配置为与后续形成的第二初始连接线连接。
在示例性实施方式中，第二初始连接块82-1可以设置在第N+2单元列的电路单元中。
在示例性实施方式中，第三初始信号线83的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，可以位于第一扫描信号线31远离第三极板73的一侧，第三初始信号线83通过第八过孔V8与每个电路单元中的第八有源层的第一区连接，因而实现了第三初始信号线83连接第八晶体管T8的第一极，第三初始信号线83可以将第三初始信号写入第八晶体管T8的第一极。
在示例性实施方式中，第三初始信号线83上设置有第三初始连接块83-1。第三初始连接块83-1的形状可以为块形(如矩形)状，且与第三初始信号线83连接，第三初始连接块83-1被配置为与后续形成的第三初始连接线连接。
在示例性实施方式中，第三初始信号线83可以设置在第N+1单元列的电路单元中。
在示例性实施方式中，第一连接电极41的形状可以为主体部分沿着第二方向Y延伸的条形状，可以设置在第二扫描信号线32和发光信号线35之间。第一连接电极41的第一端与通过第二过孔V2与第一有源层的第二区(也是第二有源层的第一区)连接，第一连接电极41的第二端通过第十过孔V10与第一极板71连接。由于第一极板71作为第三晶体管T3的栅电极，因而第一连接电极41实现了第一晶体管T1的第二极、第二晶体管T2的第一极、第三晶体管T3的栅电极和第一电容的第一极板71之间的相互连接，第一连接电极41可以作为像素驱动电路的第一节点N1。
在示例性实施方式中，第二连接电极42的形状可以为主体部分沿着第二方向Y延伸的条形状，可以设置在第二扫描信号线32和电源连接线36之间。第二连接电极42的第一端与通过第四过孔V4与第四有源层的第二区(也是第九有源层的第一区)连接，第二连接电极42的第二端通过第十一过孔V11与第二极板72连接，第二连接电极42的第一端与第二端之间的位置通过第十二过孔V12与第三极板73连接。第二连接电极42实现了第四晶体管T4的第二极、第九晶体管T9的第一极、第一电容的第三极板73和第二电容的第二极板72之间的相互连接，第二连接电极42可以作为像素驱动电路的第五节点N5。
在示例性实施方式中，第三连接电极43的形状可以为块形(如矩形等)状，可以位于第四扫描信号线34和第一初始信号线81之间，第三连接电极43通过第三过孔V3与第四有源层的第一区连接，第三连接电极43被配置为与后续形成的数据信号线连接。
在示例性实施方式中，第四连接电极44的形状可以为块形(如矩形等)状，可以位于发光信号线35和电源连接线36之间，第四连接电极44通过第六过孔V6与第六有源层的第二区(也是第七有源层的第二区)连接，第四连接电极44被配置为与后续形成的阳极连接电极连接。
在示例性实施方式中，第五连接电极45的形状可以为块形(如矩形等)状，可以位于第一扫描信号线31和第四扫描信号线34之间，第五连接电极45的第一端通过第一过孔V1与第一有源层的第一区连接，第五连接电极45的第二端通过第九过孔V9与第一初始连接块81-1连接。由于第一初始连接块81-1与第一初始信号线81连接，因而实现了第一初始信号线81连接第一晶体管T1的第一极，第一初始信号线81可以将第一初始信号写入第一晶体管T1的第一极。在示例性实施方式中，至少一个电路单元中的第五连接电极45还被配置为与后续形成的第一初始连接线连接。
在示例性实施方式中，由于第一极板71具有像素驱动电路的第一节点N1的电位，第三极板73具有像素驱动电路的第五节点N5的电位，因而具有第一节点N1的电位的第一极板71(第一电容的第一端)与具有第五节点N5的电位的第三极板73(第一电容的第二端)形成像素驱动电路的第一电容。
在示例性实施方式中，由于第二极板72具有像素驱动电路的第五节点N5的电位，第四极板74与电源连接线36连接，电源连接线36被配置为与后续形成的第一电源线连接，第四极板74具有第一电源线的电位，因而具有第一电源线的电位的第四极板74(第二电容的第一端)和具有第五节点N5的电位的第二极板72(第二电容的第二端)形成像素驱动电路的第二电容。
(16)形成第一平坦层图案。在示例性实施方式中，形成第一平坦层图案可以包括：在形成前述图案的基底上，涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，形成覆盖第三导电层的第一平坦层，每个电路单元中的第一平坦上设置有多个过孔，如图13所示。
在示例性实施方式中，显示基板中每个电路单元的多个过孔至少包括：第三十一过孔 V31、第三十二过孔V32和第三十三过孔V33。
在示例性实施方式中，第三十一过孔V31在基底上的正投影位于电源连接线36的电源连接块36-1在基底上的正投影的范围之内，第三十一过孔V31内的第一平坦层被去掉，暴露出电源连接块36-1的表面，第三十一过孔V31被配置为使后续形成的第一电源线通过该过孔与电源连接块36-1。
在示例性实施方式中，第三十二过孔V32在基底上的正投影位于第三连接电极43在基底上的正投影的范围之内，第三十二过孔V32内的第一平坦层被去掉，暴露出第三连接电极43的表面，第三十二过孔V32被配置为使后续形成的数据信号线通过该过孔与第三连接电极43连接。
在示例性实施方式中，第三十三过孔V33在基底上的正投影位于第四连接电极44在基底上的正投影的范围之内，第三十三过孔V33内的第一平坦层被去掉，暴露出第四连接电极44的表面，第三十三过孔V33被配置为使后续形成的阳极连接电极通过该过孔与第四连接电极44连接。
在示例性实施方式中，至少一个电路单元中，还可以包括第三十四过孔V34。第三十四过孔V34在基底上的正投影位于第五连接电极45在基底上的正投影的范围之内，第三十四过孔V34内的第一平坦层被去掉，暴露出第五连接电极45的表面，第三十四过孔V34被配置为使后续形成的第一初始连接线通过该过孔与第五连接电极45连接。
在示例性实施方式中，第三十四过孔V34可以设置在第N单元列的电路单元中。
在示例性实施方式中，至少一个电路单元中，还可以包括第三十五过孔V35。第三十五过孔V35在基底上的正投影位于第二初始信号线82的第二初始连接块82-1在基底上的正投影的范围之内，第三十五过孔V35内的第一平坦层被去掉，暴露出第二初始连接块82-1的表面，第三十五过孔V35被配置为使后续形成的第二初始连接线通过该过孔与第二初始连接块82-1连接。
在示例性实施方式中，第三十五过孔V35可以设置在第N+2单元列的电路单元中。
在示例性实施方式中，至少一个电路单元中，还可以包括第三十六过孔V36。第三十六过孔V36在基底上的正投影位于第三初始信号线83的第三初始连接块83-1在基底上的正投影的范围之内，第三十六过孔V36内的第一平坦层被去掉，暴露出第三初始连接块83-1的表面，第三十六过孔V36被配置为使后续形成的第三初始连接线通过该过孔与第三初始连接块83-1连接。
在示例性实施方式中，第三十六过孔V36可以设置在第N+1单元列的电路单元中。
(17)形成第四导电层图案。在示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第一平坦层上的第四导电层，如图14A和14B所示，图14B为图14A中第四导电层的示意图。在示例性实施方式中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，显示基板中多个电路单元的第四导电层图案均可以包括：第一电源线51、数据信号线52和阳极连接电极53。
在示例性实施方式中，第一电源线51的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，第一电源线51通过第三十一过孔V31与电源连接块36-1。由于电源连接块36-1与电源连接线36连接，因而实现了主体部分沿着第一方向X延伸的电源连接线36与主体部分沿着第二方向Y延伸的第一电源线51的相互连接，第一电源线51和电源连接线36在显示基板上形成网状的传输第一电源信号的网状连通结构，不仅可以有效降低第一电源线的电阻，减小第一电源信号的压降，而且可以有效提升显示基板中第一电源信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，第三导电层的电源连接线36可以设置在每个单元行中，第四导电层的第一电源线51可以设置在每个单元列中，多条第一电源线51分别连接多条电源连接线36，形成传输第一电源信号的网状连通结构。
在示例性实施方式中，第一电源线51在基底上的正投影与第一连接电极41在基底上的正投影至少部分交叠。由于第一连接电极41作为像素驱动电路中的第一节点N1，因而恒定电压的第一电源线51可以有效屏蔽像素驱动电路中其它信号对第一节点N1的影响，避免了其它信号(如数据电压跳变)影响像素驱动电路的第一节点N1的电位，提高了显示效果。
在示例性实施方式中，第一电源线51在基底上的正投影与第二连接电极42在基底上的正投影至少部分交叠。由于第二连接电极42作为像素驱动电路中的第五节点N5，因而恒定电压的第一电源线51可以有效屏蔽像素驱动电路中其它信号对第五节点N5的影响，避免了其它信号影响像素驱动电路的第五节点N5的电位，提高了显示效果。
在示例性实施方式中，第一电源线51可以为非等宽度设计，采用非等宽度设计的第一电源线51不仅可以便于像素结构的布局，而且可以降低第一电源线与数据信号线之间的寄生电容。
在示例性实施方式中，数据信号线52的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，数据信号线52通过第三十二过孔V32与第三连接电极43连接。由于第三连接电极43通过过孔与第四有源层的第一区连接，因而实现了数据信号线52将数据信号写入第四晶体管T4的第一极。
在示例性实施方式中，阳极连接电极53的形状可以为块形(如矩形等)状，阳极连接电极53通过第三十三过孔V33与第四连接电极44连接。由于第四连接电极44通过过孔与第六有源层的第二区(也是第七有源层的第二区)连接，因而实现了阳极连接电极53与第六晶体管T6的第二极和第七晶体管T7的第二极连接。在示例性实施方式中，阳极连接电极53被配置为与后续形成的阳极连接，因而可以实现像素驱动电路驱动发光器件。
在示例性实施方式中，至少一个电路单元中还可以包括第一初始连接线84。第一初始连接线84的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，第一初始连接线84通过第三十四过孔V34与第五连接电极45连接。由于第五连接电极45与第一初始信号线81连接，因而实现了主体部分沿着第一方向X延伸的第一初始信号线81与主体部分沿着第二方向Y延伸的第一初始连接线84的相互连接，第一初始信号线81和第一初始连接线84在显示基板上形成网状的传输第一初始信号的网状连通结构，不仅可以有效降低第一初始连接线的电阻，减小第一初始信号的压降，而且可以有效提升显示基板中第一初始信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，第二导电层的第一初始信号线81可以设置在每个单元行中，第四导电层的第一初始连接线84可以每隔2个单元列设置一条，多条第一初始连接线84分别连接多条第一初始信号线81，形成传输第一初始信号的网状连通结构。
在示例性实施方式中，第一初始连接线84可以设置在第N单元列的电路单元中。
在示例性实施方式中，至少一个电路单元中还可以包括第二初始连接线85。第二初始连接线85的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，第二初始连接线85通过第三十五过孔V35与第二初始连接块82-1连接。由于第二初始连接块82-1与第二初始信号线82连接，因而实现了主体部分沿着第一方向X延伸的第二初始信号线82与主体部分沿着第二方向Y延伸的第二初始连接线85的相互连接，第二初始信号线82和第二初始连接线85在显示基板上形成网状的传输第二初始信号的网状连通结构，不仅可以有效降低第二初始连接线的电阻，减小第二初始信号的压降，而且可以有效提升显 示基板中第二初始信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，第三导电层的第二初始信号线82可以设置在每个单元行中，第四导电层的第二初始连接线85可以每隔2个单元列设置一条，多条第二初始信号线82分别连接多条第二初始连接线85，形成传输第二初始信号的网状连通结构。
在示例性实施方式中，第二初始连接线85可以设置在第N+2单元列的电路单元中。
在示例性实施方式中，至少一个电路单元中还可以包括第三初始连接线86。第三初始连接线86的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，第三初始连接线86通过第三十六过孔V36与第三初始连接块83-1连接。由于第三初始连接块83-1与第三初始信号线83连接，因而实现了主体部分沿着第一方向X延伸的第三初始信号线83与主体部分沿着第二方向Y延伸的第三初始连接线86的相互连接，第三初始信号线83和第三初始连接线86在显示基板上形成网状的传输第三初始信号的网状连通结构，不仅可以有效降低第三初始连接线的电阻，减小第三初始信号的压降，而且可以有效提升显示基板中第三初始信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，第三导电层的第三初始信号线83可以设置在每个单元行中，第四导电层的第三初始连接线86可以每隔2个单元列设置一条，多条第三初始信号线83分别连接多条第三初始连接线86，形成传输第三初始信号的网状连通结构。
在示例性实施方式中，第三初始连接线86可以设置在第N+1单元列的电路单元中。
后续制备过程可以包括形成第二平坦层图案，第二平坦层上设置有多个阳极过孔，阳极过孔在基底上的正投影位于阳极连接电极在基底上的正投影的范围之内，阳极过孔内的第二平坦层被去掉，暴露出阳极连接电极的表面，阳极过孔被配置为使后续形成的阳极通过该过孔与阳极连接电极连接。
至此，在基底上制备完成驱动电路层。在示例性实施方式中，制备完成驱动电路层后，可以在驱动电路层上依次制备发光结构层和封装结构层，这里不再赘述。
在示例性实施方式中，在平行于显示基板的平面内，驱动电路层可以包括多个电路单元，至少一个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、第三扫描信号线、第四扫描信号线、第五扫描信号线、发光信号线、第一初始信号线、第二初始信号线、第三初始信号线、第一电源线和数据信号线。在垂直于显示基板的平面内，驱动电路层可以至少包括在基底上依次叠设的第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第三导电层、第一平坦层、第四导电层和第二平坦层。
在示例性实施方式中，半导体层可以至少包括第一有源层至第九有源层，第一导电层可以至少包括第一栅电极、第二栅电极、第四栅电极、第七栅电极、第八栅电极、第九栅电极、栅极连接线、发光信号线、第一极板和第二极板，第二导电层可以至少包括第三极板、第四极板和第一初始信号线，第三导电层可以至少包括第一扫描信号线、第二扫描信号线、第三扫描信号线、第四扫描信号线、第二初始信号线、第三初始信号线和多个连接电极，第四导电层可以至少包括第一电源线、数据信号线和阳极连接电极。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性衬底可以为但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的 材料可以采用非晶硅(a-si)。
在示例性实施方式中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一平坦层和第二平坦层可以采用有机材料，如树脂等。有源层可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。
本公开示例性实施例提供了一种显示基板，通过九个晶体管和2个电容组成的像素驱动电路，不仅实现了补偿阶段和数据写入两个阶段分离，可以较快地实现数据信号的写入，有效保证了写入电容的电荷量，有效避免了高频显示和低灰阶画面下显示不均等画质问题，而且通过补偿阶段采用电容自放电方式进行阈值电压的采样，有效避免了驱动晶体管阈值补偿不充分等问题，提高了补偿效果，可以支持更高帧频的显示。
本公开实施例像素驱动电路中的第一晶体管T1和第二晶体管T2连接同一条扫描信号线，且第一晶体管T1和第二晶体管T2共用其中一个子栅电极，通过晶体管布局的灵活设计，可以优化布局空间，减小像素驱动电路的占用面积，有利于实现高分辨率。
本公开实施例显示基板通过设置主体部分沿着第一方向X延伸的电源连接线和主体部分沿着第二方向Y延伸的第一电源线，且第一电源线与第一电源连接线相互连接，在显示基板上形成网状连通结构，不仅可以有效降低第一电源线的电阻，减小第一电源信号的压降，而且可以有效提升显示基板中第一电源信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
本公开实施例显示基板通过设置主体部分沿着第一方向X延伸的第一初始信号线和主体部分沿着第二方向Y延伸的第一初始连接线，且第一初始信号线和第一初始连接线相互连接，在显示基板上形成网状连通结构，不仅可以有效降低第一初始信号线的电阻，减小第一初始信号的压降，而且可以有效提升显示基板中第一初始信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
本公开实施例显示基板通过设置主体部分沿着第一方向X延伸的第二初始信号线和主体部分沿着第二方向Y延伸的第二初始连接线，且第二初始信号线与第二初始连接线相互连接，在显示基板上形成网状连通结构，不仅可以有效降低第二初始信号线的电阻，减小第二初始信号的压降，而且可以有效提升显示基板中第二初始信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
本公开实施例显示基板通过设置主体部分沿着第一方向X延伸的第三初始信号线和主体部分沿着第二方向Y延伸的第三初始连接线，且第三初始信号线与第三初始连接线相互连接，在显示基板上形成网状连通结构，不仅可以有效降低第三初始信号线的电阻，减小第三初始信号的压降，而且可以有效提升显示基板中第三初始信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
图15为本公开示例性实施例另一种像素驱动电路的等效电路图。如图15所示，本实施例的像素驱动电路可以为9T2C结构，主体结构与图4所示实施例基本上相同，所不同的是，本实施例第一晶体管T1的第一极和第七晶体管T7的第一极相互连接，且均与第二初始信号线INIT2连接，第七晶体管T7的第二极与第四节点N4连接。
在示例性实施方式中，本实施例像素驱动电路分别与10条信号线连接，10条信号线分别为第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、第四扫描信号线S4、第五扫描信号线S5、发光信号线EM、第二初始信号线INIT2、第三初始信号线INIT3、数据信号线DATA和第一电源线VDD。与图4所示实施例不同的是，本实施例将第一初始信号线去掉，或者，本实施例将两条初始信号线合并为一条初始信号线。
在示例性实施方式中，本实施例像素驱动电路的驱动时序与图5所示驱动时序基本上相同，驱动电流也基本上相同，所不同的是，第二阶段B完成时，第五节点N5的电位为Vint2+|Vth|，Vint2为第二初始信号线INIT2的第二初始信号的电压。
图16为本公开示例性实施例另一种显示基板的平面结构示意图。如图16所示，本实施例显示基板主体结构与图6所示实施例基本上相同，本实施例第一晶体管T1的栅电极和第二晶体管T2的栅电极连接同一条第三扫描信号线33，本单元行中电路单元的第七晶体管T7的栅电极与下一单元行中的第一扫描信号线31连接，本单元行中电路单元的第八晶体管T8的栅电极与本单元行中的第一扫描信号线31连接。所不同的是，本实施例第一晶体管T1的第一极和第七晶体管T7的第一极相互连接，且均与第二初始信号线82连接，即本实施例的第二导电层中没有设置第一初始信号线，第四导电层中没有设置第一初始连接线。
在示例性实施方式中，本实施例显示基板的制备过程可以包括如下操作。
(21)形成半导体层图案。在示例性实施方式中，形成半导体层图案的过程以及所形成的半导体层图案与图6所示方案基本上相同。所不同的是，本实施例中，本单元行中电路单元的第一有源层的第一区11-1设置在上一单元行的电路单元中，且与上一单元行中电路单元的第七有源层的第一区17-1相互连接，或者，下一单元行中电路单元的第一有源层的第一区11-1设置在本单元行的电路单元中，且本单元行中电路单元的第七有源层的第一区17-1相互连接，如图17所示。
在示例性实施方式中，第一有源层的第一区11-1可以作为第七有源层的第一区17-1，被配置为与后续形成的第二初始信号线连接。
(22)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案的过程以及所形成的第一导电层图案与图6所示方案基本上相同，如图18A和图18B所示，图18B为图18A中第一导电层的示意图。
(23)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案的过程以及所形成的第二导电层图案与图6所示方案基本上相同，所不同的是，第二导电层没有设置第一初始信号线，如图19A和图19B所示，图19B为图19A中第二导电层的示意图。
(24)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案的过程以及所形成的多个过孔与图6所示方案基本上相同，所不同的是，每个电路单元的多个过孔至少包括第二过孔V2至第八过孔V8、第十过孔V10至第十七过孔V17，如图20所示。
在示例性实施方式中，由于本单元行中电路单元的第七有源层的第一区可以作为下一单元行中电路单元的第一有源层的第一区，因而本单元行中电路单元的第七过孔V7可以作为下一单元行中电路单元的第一过孔。由于第二导电层没有设置第一初始信号线，因而本实施例没有设置第九过孔。
(25)形成第三导电层图案。在示例性实施方式中，形成第三导电层图案的过程以及所形成的第三导电层图案与图6所示方案基本上相同，所不同的是，第三导电层没有设置第五连接电极，如图21A和图21B所示，图21B为图21A中第三导电层的示意图。
在示例性实施方式中，第二初始信号线82的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，第二初始信号线82通过第七过孔V7与每个电路单元中的第七有源层的第一区(也是第一有源层的第一区)连接，因而实现了第二初始信号线82可以 将第二初始信号写入第一晶体管T1的第一极和第七晶体管T7的第一极。
在示例性实施方式中，第二初始信号线82上设置有第二初始连接块82-1，第二初始连接块82-1可以设置在第N单元列和第N+2单元列的电路单元中。
在示例性实施方式中，第三初始信号线83的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，第三初始信号线83通过第八过孔V8与每个电路单元中的第八有源层的第一区连接，因而实现了第三初始信号线83可以将第三初始信号写入第八晶体管T8的第一极。
在示例性实施方式中，第三初始信号线83上设置有第三初始连接块83-1，第三初始信号线83可以设置在第N+1单元列的电路单元中。
(26)形成第一平坦层图案。在示例性实施方式中，形成第一平坦层图案的过程以及所形成的多个过孔与图6所示方案基本上相同，所不同的是，第一平坦层上没有设置第三十四过孔，如图22所示。
在示例性实施方式中，第三十五过孔V35暴露出第二初始连接块82-1的表面，第三十五过孔V35可以设置在N单元列和第N+2单元列的电路单元中。
在示例性实施方式中，第三十六过孔V36暴露出第三初始连接块83-1的表面，第三十六过孔V36可以设置在第N+1单元列的电路单元中。
(27)形成第四导电层图案。在示例性实施方式中，形成第四导电层图案的过程以及所形成的第四导电层图案与图6所示方案基本上相同，所不同的是，第四导电层没有设置第一初始连接线，如图23A和23B所示，图23B为图23A中第四导电层的示意图。
在示例性实施方式中，第二初始连接线85通过第三十五过孔V35与第二初始连接块82-1连接，因而实现了第二初始信号线82和第二初始连接线85在显示基板上形成网状的传输第二初始信号的网状连通结构。
在示例性实施方式中，第三导电层的第二初始信号线82可以设置在每个单元行中，第四导电层的第二初始连接线85可以每隔1个单元列设置一条。
在示例性实施方式中，第二初始连接线85可以设置在第N单元列和第N+2单元列的电路单元中。
在示例性实施方式中，第三初始连接线86通过第三十六过孔V36与第三初始连接块83-1连接，因而实现了第三初始信号线83和第三初始连接线86在显示基板上形成网状的传输第三初始信号的网状连通结构。
在示例性实施方式中，第三导电层的第三初始信号线83可以设置在每个单元行中，第四导电层的第三初始连接线86可以每隔1个单元列设置一条。
在示例性实施方式中，第三初始连接线86可以设置在第N+1单元列的电路单元中。
后续制备过程可以包括形成第二平坦层图案，以及依次制备发光结构层和封装结构层，形成过程以及图案与图6所示方案基本上相同，这里不再赘述。
本公开示例性实施例提供了一种显示基板，不仅具有图6所示方案的技术效果，而且通过减少一条初始信号线，可以优化布局空间，减小像素驱动电路的占用面积，有利于实现高分辨率。
图24为本公开示例性实施例又一种像素驱动电路的等效电路图。如图24所示，本实施例的像素驱动电路可以为9T2C结构，主体结构与图15所示实施例基本上相同，所不同的是，本实施例第四晶体管T4的第二极与第二节点N2连接。
在示例性实施方式中，本实施例第一节点N1、第三节点N3和第四节点N4的连接结构与图4和图15所示实施例基本上相同，所不同的是，第二节点N2分别与第三晶体管T3的第一极、第四晶体管T4的第二极、第五晶体管T5的第二极、第八晶体管T8的第二极和第九晶体管T9的第二极连接，第五节点N5分别与第九晶体管T9的第一极、第一 电容C1的第二端和第二电容C2的第二端连接。
在示例性实施方式中，本实施例像素驱动电路的驱动时序与图5所示驱动时序基本上相同，驱动电流也基本上相同，所不同的是，在数据写入阶段，第二扫描信号线S2和第四扫描信号线S4为低电平信号，第四晶体管T4和第九晶体管T9同步导通，数据信号线将数据信号写入第五节点N5。因此，本实施例第二扫描信号线S2的低电平信号脉宽相应加宽。
图25为本公开示例性实施例又一种显示基板的平面结构示意图。如图25所示，本实施例显示基板主体结构与图16所示实施例基本上相同，本实施例第一晶体管T1的栅电极和第二晶体管T2的栅电极连接同一条第三扫描信号线33，本单元行中电路单元的第七晶体管T7的栅电极与下一单元行中的第一扫描信号线31连接，本单元行中电路单元的第八晶体管T8的栅电极与本单元行中的第一扫描信号线31连接，第一晶体管T1的第一极和第七晶体管T7的第一极相互连接，且均与第二初始信号线82连接。所不同的是，本实施例第四晶体管T4和第九晶体管T9的连接关系不同。
在示例性实施方式中，本实施例显示基板的制备过程可以包括如下操作。
(31)形成半导体层图案。在示例性实施方式中，形成半导体层图案的过程以及所形成的半导体层图案与图16所示方案基本上相同，所不同的是，本实施例中的第九有源层的第一区19-1可以单独设置，第三有源层的第一区13-1可以同时作为第四有源层的第二区14-2、第五有源层的第二区15-2、第八有源层的第二区18-2和第九有源层的第二区19-2，构成像素驱动电路的第二节点N2，如图26所示。
(22)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案的过程以及所形成的第一导电层图案与图16所示方案基本上相同，所不同的是，第四栅电极24的形状可以为沿着第一方向X延伸的条形状，第四栅电极24与第四有源层相重叠的区域可以作为第四晶体管T4的栅电极，第九栅电极29的形状可以呈“L”字形状，第九栅电极29与第九有源层相重叠的区域可以作为双栅结构的第九晶体管T9的栅电极，如图27A和图27B所示，图27B为图27A中第一导电层的示意图。
(33)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案的过程以及所形成的第二导电层图案与图16所示方案基本上相同，如图28A和图28B所示，图28B为图28A中第二导电层的示意图。
(34)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案的过程以及所形成的多个过孔与图16所示方案基本上相同，所不同的是，第四过孔V4在基底上的正投影位于第九有源层的第一区在基底上的正投影的范围之内，第四过孔V4被配置为使后续形成的第二连接电极通过该过孔与第九有源层的第一区连接，如图29所示。
(35)形成第三导电层图案。在示例性实施方式中，形成第三导电层图案的过程以及所形成的第三导电层图案与图16所示方案基本上相同，所不同的是，第二连接电极42的第一端与通过第四过孔V4与第九有源层的第一区连接，第二连接电极42的第二端通过第十一过孔V11与第二极板72连接，第二连接电极42的第一端与第二端之间的位置通过第十二过孔V12与第三极板73连接，实现了第九晶体管T9的第一极、第一电容的第三极板73和第二电容的第二极板72之间的相互连接，形成像素驱动电路的第五节点N5，如图30A和图30B所示，图30B为图30A中第三导电层的示意图。
后续制备过程可以包括形成第一平坦层、第四导电层和第二平坦层图案，以及依次制备发光结构层和封装结构层，形成过程以及图案与图16所示方案基本上相同，这里不再赘述。
图31为本公开示例性实施例又一种像素驱动电路的等效电路图。如图31所示，本实施例的像素驱动电路可以为9T2C结构，主体结构与图4所示实施例基本上相同，所不同 的是，本单元行中电路单元的第七晶体管T7的栅电极与本单元行中的第一扫描信号线31连接，即本单元行中电路单元的第七晶体管T7和第八晶体管T8连接同一条扫描信号线，即连接同一条第一扫描信号线31。
在示例性实施方式中，本实施例像素驱动电路的驱动时序与图5所示驱动时序基本上相同，驱动电流也基本上相同，所不同的是，第一阶段A还包括第七晶体管T7导通，第二初始信号线INIT2的第二初始信号写入第四节点N4，对第四节点N4(发光器件)进行初始化。此外，第五阶段E中，第七晶体管T7和第八晶体管T8在相同时刻导通，在相同时刻断开。
图32为本公开示例性实施例又一种像素驱动电路的等效电路图。如图32所示，本实施例的像素驱动电路可以为9T2C结构，主体结构与图15所示实施例基本上相同，所不同的是，本单元行中电路单元的第七晶体管T7的栅电极与本单元行中的第一扫描信号线31连接，即本单元行中电路单元的第七晶体管T7和第八晶体管T8连接同一条扫描信号线，即连接同一条第一扫描信号线31。
在示例性实施方式中，本实施例像素驱动电路的驱动时序与图5所示驱动时序基本上相同，驱动电流也基本上相同，所不同的是，第一阶段A还包括第七晶体管T7导通，第二初始信号线INIT2的第二初始信号写入第四节点N4，对第四节点N4(发光器件)进行初始化。此外，第五阶段E中，第七晶体管T7和第八晶体管T8在相同时刻导通，在相同时刻断开。
图33为本公开示例性实施例又一种像素驱动电路的等效电路图。如图33所示，本实施例的像素驱动电路可以为9T2C结构，主体结构与图4所示实施例基本上相同，所不同的是，本实施例中第二晶体管T2的栅电极与第三扫描信号线S3连接，第二晶体管T2的第一极与第二初始信号线INIT2连接，第二晶体管T2的第二极与第三节点N3连接。
在示例性实施方式中，本实施例中第一节点N1分别与第一晶体管T1的第二极、第三晶体管T3的栅电极和第一电容C1的第一端连接，其它节点的结构与图4所示实施例基本上相同。
在示例性实施方式中，本实施例像素驱动电路的驱动时序与图5所示驱动时序基本上相同，驱动电流也基本上相同，这里不再赘述。
图34为本公开示例性实施例又一种像素驱动电路的等效电路图。如图34所示，本实施例的像素驱动电路可以为9T2C结构，主体结构与图33所示实施例基本上相同，所不同的是，本单元行中电路单元的第七晶体管T7的栅电极与本单元行中的第一扫描信号线31连接，即本单元行中电路单元的第七晶体管T7和第八晶体管T8连接同一条扫描信号线，即连接同一条第一扫描信号线31。
在示例性实施方式中，本实施例像素驱动电路的驱动时序与图5所示驱动时序基本上相同，驱动电流也基本上相同，所不同的是，第一阶段A还包括第七晶体管T7导通，第二初始信号线INIT2的第二初始信号写入第四节点N4，对第四节点N4(发光器件)进行初始化。此外，第五阶段E中，第七晶体管T7和第八晶体管T8在相同时刻导通，在相同时刻断开。
图35为本公开示例性实施例又一种像素驱动电路的等效电路图。如图35所示，本实施例的像素驱动电路可以为9T2C结构，主体结构与图4所示实施例基本上相同，所不同的是，第一晶体管T1、第二晶体管T2、第四晶体管T4和第九晶体管T9可以为氧化物晶体管，其它晶体管为低温多晶硅晶体管。
在示例性实施方式中，低温多晶硅晶体管具有迁移率高、充电快等优点，氧化物晶体管具有漏电流低等优点，本公开通过将低温多晶硅晶体管和氧化物晶体管集成在一个显示基板上，形成LTPS+Oxide(简称LTPO)显示基板，可以利用两者的优势，可以实现低 频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，本实施例像素驱动电路的驱动时序与图5所示驱动时序基本上相同，相应的驱动信号进行反相，驱动电流也基本上相同，这里不再赘述。
图36为本公开示例性实施例又一种像素驱动电路的等效电路图。如图36所示，本实施例的像素驱动电路可以为9T2C结构，主体结构与图24所示实施例基本上相同，所不同的是，第一晶体管T1、第二晶体管T2和第九晶体管T9可以为氧化物晶体管，其它晶体管为低温多晶硅晶体管。
在示例性实施方式中，本实施例像素驱动电路的驱动时序与图5所示驱动时序基本上相同，相应的驱动信号进行反相，驱动电流也基本上相同，这里不再赘述。
在一些可能的实施方式中，图15、图31、图32、图33、图34所示实施例亦可以采用LTPO结构，第一晶体管T1、第二晶体管T2、第四晶体管T4和第九晶体管T9中的至少一个晶体管或者多个晶体管为氧化物晶体管，其它晶体管为低温多晶硅晶体管，本公开在此不做限定。
在一些可能的实施方式中，图24所示实施例亦可以采用本单元行中电路单元的第七晶体管T7的栅电极与本单元行中的第一扫描信号线31连接、第二晶体管T2的第一极与第二初始信号线INIT2等结构，本公开在此不做限定。
在示例性实施方式中，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
在示例性实施方式中，本公开显示基板可以应用于具有像素驱动电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
本公开还提供一种显示基板的驱动方法，以驱动上述实施例提供的显示基板。在示例性实施方式中，所述显示基板包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路，所述像素驱动电路至少包括第一电容、第二电容、第一晶体管、第四晶体管、第八晶体管、第九晶体管、以及作为驱动晶体管的第三晶体管，所述第一晶体管的第二极分别与所述第三晶体管的栅电极和所述第一电容的第一端连接，所述第九晶体管的第一极分别与所述第一电容的第二端和所述第二电容的第二端连接，所述第九晶体管的第二极分别与所述第三晶体管的第一极和所述第八晶体管的第二极连接，所述第四晶体管的第一极与数据信号线连接；所述显示基板被配置为显示相应的显示内容，所述显示内容包括多个显示帧，至少一个显示帧包括刷新帧，所述刷新帧至少包括依次进行的补偿阶段和数据写入阶段，且所述补偿阶段通过电容自放电方式进行阈值电压的采样。
在示例性实施方式中，所述刷新帧至少包括初始化阶段、补偿阶段和数据写入阶段；
在所述初始化阶段，所述第八晶体管和所述第九晶体管导通，第三初始信号线的第三初始信号写入所述第一电容的第二端和所述第二电容的第二端，所述第二电容充电；
在所述补偿阶段，所述第一晶体管导通，对所述第三晶体管的栅电极进行初始化，所述第一电容和所述第二电容通过导通的第九晶体管和导通的第三晶体管放电，使所述第一电容两端的压差为|Vth|，Vth为所述第三晶体管的阈值电压；
在所述数据写入阶段，所述第四晶体管导通，所述数据信号线的数据信号写入所述第一电容的第二端和所述第二电容的第二端。
在示例性实施方式中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极分别与所述第一晶体管的第二极、所述第三晶体管的栅电极和所述第一电容的第一端连接，所述第二晶体管的第二极与所述第三晶体管的第二极连接；在所述补偿阶段，所述第 二晶体管导通，所述第一电容和所述第二电容通过导通的第九晶体管、导通的第三晶体管和导通的第二晶体管放电。
在示例性实施方式中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极与第二初始信号线连接，所述第二晶体管的第二极与所述第三晶体管的第二极连接；在所述补偿阶段，所述第二晶体管导通，所述第一电容和所述第二电容通过导通的第九晶体管、导通的第三晶体管和导通的第二晶体管放电。
在示例性实施方式中，所述像素驱动电路还包括第七晶体管，所述第七晶体管的第一极与第二初始信号线连接，所述第七晶体管的第二极与所述发光器件连接；在所述初始化阶段，所述第七晶体管导通，所述第二初始信号线的第二初始信号对所述发光器件进行初始化，或者，在所述补偿阶段，所述第七晶体管导通，所述第二初始信号线的第二初始信号对所述发光器件进行初始化。
在示例性实施方式中，至少一个显示帧还包括保持帧，所述保持帧至少包括调整阶段；
在所述调整阶段，所述第八晶体管导通，第三初始信号线的第三初始信号写入所述第三晶体管的第一极，调整所述第三晶体管的偏压状态。
在示例性实施方式中，所述像素驱动电路还包括第七晶体管，所述第七晶体管的第一极与第二初始信号线连接，所述第七晶体管的第二极与所述发光器件连接；在所述调整阶段，所述第七晶体管导通，所述第二初始信号线的第二初始信号对所述发光器件进行初始化。
本公开示例性实施例提供了一种显示基板的驱动方法，不仅实现了补偿阶段和数据写入两个阶段分离，而且实现了补偿阶段采用电容自放电方式进行阈值电压的采样，可以较快地实现数据信号的写入，可以支持更高帧频的显示，并提高了补偿效果。
本公开显示基板的驱动方法通过向第三晶体管的第一极施加直流信号，可以有效改善第三晶体管的磁滞情况，有利于残像改善和支持低频显示，有利于提高显示效果。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但应该注意，上述实施方式仅仅是示例性的，而不是限制性的。因此，本公开不限于在此具体示出和描述的内容。可以对实施的形式及细节进行多种修改、替换或省略，而不脱离本公开的范围。

Claims (21)

  1. 一种显示基板，包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路，所述像素驱动电路至少包括第一电容、第二电容、第一晶体管、第四晶体管、第八晶体管、第九晶体管、以及作为驱动晶体管的第三晶体管，所述第一晶体管的第二极分别与所述第三晶体管的栅电极和所述第一电容的第一端连接，所述第九晶体管的第一极分别与所述第一电容的第二端和所述第二电容的第二端连接，所述第九晶体管的第二极分别与所述第三晶体管的第一极和所述第八晶体管的第二极连接，所述第四晶体管的第一极与数据信号线连接。
  2. 根据权利要求1所述的显示基板，其中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极分别与所述第一晶体管的第二极、所述第三晶体管的栅电极和所述第一电容的第一端连接，所述第二晶体管的第二极与所述第三晶体管的第二极连接。
  3. 根据权利要求1所述的显示基板，其中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极与第二初始信号线连接，所述第二晶体管的第二极与所述第三晶体管的第二极连接。
  4. 根据权利要求2或3所述的显示基板，其中，所述第一晶体管和所述第二晶体管连接同一条扫描信号线。
  5. 根据权利要求4所述的显示基板，其中，在垂直于显示基板的方向上，所述显示基板至少包括设置在基底上的第一栅金属层、设置在所述第一栅金属层远离所述基底一侧的第二栅金属层、以及设置在所述第二栅金属层远离所述基底一侧的第一源漏金属层，所述第一晶体管的栅电极和所述第二晶体管的栅电极设置在所述第一栅金属层中，所述扫描信号线设置在所述第一源漏金属层中。
  6. 根据权利要求5所述的显示基板，其中，所述第一晶体管的栅电极和所述第二晶体管的栅电极为相互连接的一体结构。
  7. 根据权利要求6所述的显示基板，其中，所述第一晶体管和所述第二晶体管为双栅结构，所述第一晶体管的栅电极包括第一子栅电极和第三子栅电极，所述第二晶体管的栅电极包括第二子栅电极和第三子栅电极，所述第一晶体管和所述第二晶体管共用所述第三子栅电极。
  8. 根据权利要求7所述的显示基板，其中，所述第一子栅电极和所述第二子栅电极的形状为沿着第一方向延伸的条形状，所述第三子栅电极的形状为沿着第二方向延伸的条形状，所述第一方向和所述第二方向交叉；所述第一子栅电极和所述第二子栅电极设置在所述第三子栅电极所述第一方向的一侧，所述第一子栅电极设置在所述第三子栅电极所述第二方向的反方向的一侧，所述第二子栅电极设置在所述第三子栅电极所述第二方向的一侧，形成“C”字形状。
  9. 根据权利要求1所述的显示基板，其中，所述第四晶体管的第二极与所述所述第九晶体管的第一极连接，或者，所述第四晶体管的第二极与所述所述第九晶体管的第二极连接。
  10. 根据权利要求1所述的显示基板，其中，所述第一晶体管的第一极与第一初始信号线连接，所述像素驱动电路还包括第七晶体管，所述第七晶体管的第一极与第二初始信号线连接，所述第七晶体管的第二极与所述发光器件连接；本单元行中电路单元的第七晶体管的栅电极和第八晶体管的栅电极与本单元行中的第一扫描信号线连接。
  11. 根据权利要求1所述的显示基板，其中，所述第一晶体管的第一极与第一初始信号线连接，所述像素驱动电路还包括第七晶体管，所述第七晶体管的第一极与第二初始信号线连接，所述第七晶体管的第二极与所述发光器件连接；本单元行中电路单元的第七晶 体管的栅电极与下一单元行中的第一扫描信号线连接，本单元行中电路单元的第八晶体管的栅电极与本单元行中的第一扫描信号线连接。
  12. 根据权利要求1所述的显示基板，其中，所述像素驱动电路还包括第七晶体管，所述第七晶体管的第一极分别与所述第一晶体管的第一极和第二初始信号线连接，所述第七晶体管的第二极与所述发光器件连接；本单元行中电路单元的第七晶体管的栅电极和第八晶体管的栅电极与本单元行中的第一扫描信号线连接。
  13. 根据权利要求1所述的显示基板，其中，所述像素驱动电路还包括第七晶体管，所述第七晶体管的第一极分别与所述第一晶体管的第一极和第二初始信号线连接，所述第七晶体管的第二极与所述发光器件连接；本单元行中电路单元的第七晶体管的栅电极与下一单元行中的第一扫描信号线连接，本单元行中电路单元的第八晶体管的栅电极与本单元行中的第一扫描信号线连接。
  14. 一种显示装置，包括如权利要求1至13任一项所述的显示基板。
  15. 一种显示基板的驱动方法，所述显示基板包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路，所述像素驱动电路至少包括第一电容、第二电容、第一晶体管、第四晶体管、第八晶体管、第九晶体管、以及作为驱动晶体管的第三晶体管，所述第一晶体管的第二极分别与所述第三晶体管的栅电极和所述第一电容的第一端连接，所述第九晶体管的第一极分别与所述第一电容的第二端和所述第二电容的第二端连接，所述第九晶体管的第二极分别与所述第三晶体管的第一极和所述第八晶体管的第二极连接，所述第四晶体管的第一极与数据信号线连接；所述显示基板被配置为显示相应的显示内容，所述显示内容包括多个显示帧，至少一个显示帧包括刷新帧，所述刷新帧至少包括依次进行的补偿阶段和数据写入阶段，且所述补偿阶段通过电容自放电方式进行阈值电压的采样。
  16. 根据权利要求15所述的驱动方法，其中，所述刷新帧至少包括初始化阶段、补偿阶段和数据写入阶段；
    在所述初始化阶段，所述第八晶体管和所述第九晶体管导通，第三初始信号线的第三初始信号写入所述第一电容的第二端和所述第二电容的第二端，所述第二电容充电；
    在所述补偿阶段，所述第一晶体管导通，对所述第三晶体管的栅电极进行初始化，所述第一电容和所述第二电容通过导通的第九晶体管和导通的第三晶体管放电，使所述第一电容两端的压差为|Vth|，Vth为所述第三晶体管的阈值电压；
    在所述数据写入阶段，所述第四晶体管导通，所述数据信号线的数据信号写入所述第一电容的第二端和所述第二电容的第二端。
  17. 根据权利要求16所述的驱动方法，其中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极分别与所述第一晶体管的第二极、所述第三晶体管的栅电极和所述第一电容的第一端连接，所述第二晶体管的第二极与所述第三晶体管的第二极连接；在所述补偿阶段，所述第二晶体管导通，所述第一电容和所述第二电容通过导通的第九晶体管、导通的第三晶体管和导通的第二晶体管放电。
  18. 根据权利要求16所述的驱动方法，其中，所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极与第二初始信号线连接，所述第二晶体管的第二极与所述第三晶体管的第二极连接；在所述补偿阶段，所述第二晶体管导通，所述第一电容和所述第二电容通过导通的第九晶体管、导通的第三晶体管和导通的第二晶体管放电。
  19. 根据权利要求16所述的驱动方法，其中，所述像素驱动电路还包括第七晶体管，所述第七晶体管的第一极与第二初始信号线连接，所述第七晶体管的第二极与所述发光器件连接；在所述初始化阶段，所述第七晶体管导通，所述第二初始信号线的第二初始信号对所述发光器件进行初始化，或者，在所述补偿阶段，所述第七晶体管导通，所述第二初 始信号线的第二初始信号对所述发光器件进行初始化。
  20. 根据权利要求15所述的驱动方法，其中，至少一个显示帧还包括保持帧，所述保持帧至少包括调整阶段；
    在所述调整阶段，所述第八晶体管导通，第三初始信号线的第三初始信号写入所述第三晶体管的第一极，调整所述第三晶体管的偏压状态。
  21. 根据权利要求20所述的驱动方法，其中，所述像素驱动电路还包括第七晶体管，所述第七晶体管的第一极与第二初始信号线连接，所述第七晶体管的第二极与所述发光器件连接；在所述调整阶段，所述第七晶体管导通，所述第二初始信号线的第二初始信号对所述发光器件进行初始化。
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