WO2019014935A1

WO2019014935A1 - Advanced pixel circuit for display

Info

Publication number: WO2019014935A1
Application number: PCT/CN2017/093912
Authority: WO
Inventors: Takeshi Okuno
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2017-07-21
Filing date: 2017-07-21
Publication date: 2019-01-24
Also published as: CN110892473A

Abstract

A display device comprising a plurality of pixel circuits, each pixel circuit comprising: a light emitting diode (LED); a driving transistor; first to fifth transistors for switching; and first and second capacitors. During a first period for initialization and compensation, a compensation line is active so that the second, third and fourth transistors are on, and a voltage across the second capacitor becomes a threshold voltage of the driving transistor; during a second period for data writing, a scan line is active so that the fifth transistor is on, and a voltage of a data line is introduced in the pixel circuit; and during a third period for emission, an emission line is active so that the first transistor is on, a driving current flows through the first transistor, the driving transistor, and the LED, and the LED emits light.

Description

ADVANCED PIXEL CIRCUIT FOR DISPLAY

TECHNICAL FIELD

The present invention relates to a display device, in particular, a pixel circuit for a display device.

BACKGROUND

Recently, an Organic Light Emitting Diode (OLED) display is very attractive device due to high contrast ratio, fast response and high color reproducibility. Also it has a good applicability for the flexible display device.

Fig. 1 shows a schematic diagram of an OLED display panel. An LTPS-TFT (Low Temperature Poly Silicon -Thin Film Transistor) back plane, which is placed on a glass or a polyimide (PI) substrate and under emitting materials, is used as a panel driving circuit. The LTPS-TFT back plane includes a Scan Driver, an Emission Driver, a De-MUX circuit, and an array of pixel circuits. A display driver integrated circuit (DDIC) is placed on a flexible printed circuit (FPC) , and controls the Scan Driver, the Emission Driver, and the De-MUX circuit to output signals according to a timing sequence. Although Fig. 1 shows only one RGB pixel, an array of RGB pixel circuits can be placed to drive an array of OLEDs.

Fig. 2 shows a circuit diagram of the LTPS-TFT back plane. The Scan Driver and the Emission Driver usually comprise a shift-register circuit to control scan and emission of each pixel. Pixel (n, m) is connected to signal lines G (n-1) , G (n) , VINIT, ELVDD, EM (n) , and data (m) . The VINIT provides a DC voltage for initialization.

Fig. 3 shows an example of the De-MUX circuit including LTPS-TFT switches to select a data signal from the DDIC to each data line in a time division sequence. Namely, signals d1, d2, and d3 become low level in turn according to a timing sequence. The emission or non-emission of the OLED pixels is controlled by the above-mentioned circuits.

OLED luminance is controlled by an LTPS-TFT. The LTPS-TFT has some features, but the TFT’s threshold voltage (Vth) variation is so large. If there is a variation in the Vth for each pixel, a current to the OLED becomes uneven even if data for instructing the same voltage is input to the pixel circuit, and as a result, OLED luminance variation will occur. Luminance variation will cause deterioration of image quality. So, the OLED pixel needs a pixel compensation circuit to control the OLED driving current accurately.

The following explains a solution of the above-mentioned problem in the prior art. Fig. 4 shows a circuit diagram of a pixel circuit in the prior art. The pixel circuit in Fig. 4 is an example of the Pixel (n, m) in Fig. 2, and signals EM (n) and data (m) in Fig. 2 are shown as EM and data in Fig. 4, respectively. This pixel circuit includes seven TFTs and one capacitor (7T1C) . OLED luminance is controlled by a DTFT (driving TFT) analog current (denoted by a dashed line in Fig. 4) depending on a data voltage. The other TFTs M2 to M7 work as switches. Instruction data to the DTFT is Vgs (which is a TFT gate-source voltage) resulting from a voltage from a data line. The data voltage across a capacitor Cst (capacitance between DTFT gate-source) of each pixel is updated for each image frame.

Fig. 5 shows a timing sequence for driving the pixel circuit. In Fig. 2, G (n-2) , G (n-1) , G (n) , …lines are connected to the Scan Driver, and G (n-2) , G (n-1) , G (n) , …become low level in turn for each 1HS (one horizontal sync period (for example, in the case of FHD (1920x1080 resolution) 60Hz, 1/60/1920＝8.6us) ) . In Fig. 5, G (n-1) becomes low level in the first 1HS, and then G (n) becomes low level in the next 1HS. The second half of 1HS is used for charging data on the data line.

The operation of the pixel circuit will be described with reference to Fig. 6 (a) to Fig. 6 (c) . Fig. 6 (a) shows a current flow during a DTFT initial period corresponding to period (a) in Fig. 5. According to Fig. 5, G (n-1) is low level, and G (n) and EM are high level in period (a) . So, in Fig. 6 (a) , TFT M3 is “ON” and TFTs M2 and M4 to M7 are “OFF” . So, the DTFT’s gate voltage is initialized to the VINIT voltage, namely, previous data is cleared.

Fig. 6 (b) shows current flows during a data writing and Vth compensation period corresponding to period (b) in Fig. 5. According to Fig. 5, G (n-1) is high level, G (n) is low level, and EM is high level in period (b) . So, TFTs M2, M5 and M7 are “ON” and TFTs M3, M4, and M6 are “OFF” . So, the DTFT’s gate and drain are connected because M2 is “ON” . Eventually, the DTFT’s gate voltage is shown as equation (1) :

M1gate ＝ Vdata -Vth (DTFT) (1)

wherein Vdata denotes a voltage of a data signal from the data line, and Vth (DTFT) denotes a threshold voltage of the DTFT.

This means that if Vth differs between the DTFTs, M1gate differs for the same Vdata, and thus the variation of the DTFT’s Vth should be compensated by the pixel circuit. At the same time, according to Fig. 6 (b) , the charge of the OLED capacitance is discharged because M7 is “ON” . So, the OLED anode voltage is also initialized to the VINIT voltage.

Fig. 6 (c) shows a current flow during an emission period corresponding to period (c) in Fig. 5. According to Fig. 5, G (n-1) and G (n) are high level, and EM is low level in period (c) . So, TFTs M4 and M6 are “ON” and TFTs M2, M3, M5, and M7 are “OFF” . Generally, when a transistor operates in a saturation region, a current between a drain and a source (Ids) can be expressed as Ids ＝ (1/2) (W/L) M (Vgs -Vth) ² wherein W, L, and M denote a width, a length, and mobility of a transistor, respectively. Hereinafter, (1/2) (W/L) M is expressed as β/2. Namely, β is a parameter related to the design and the characteristics of the LTPS-TFT. Therefore, when the DTFT operates in the saturation region, DTFT current is shown as equation (2) :

Ids ＝ (β/2) (Vgs -Vth) ² (2)

wherein Vgs is the difference between the source voltage and the gate voltage of DTFT. The source voltage of DTFT is ELVDD and the gate voltage of DTFT is shown as equation (1) . So, Vgs is shown as equation (3) :

Vgs ＝ ELVDD - (Vdata -Vth) (3)

Substituting equation (3) into equation (2) , then below equation (4) will be derived:

Ids ＝ (β/2) (ELVDD -Vdata + Vth -Vth) ² (4)

Eventually, OLED current is shown as equation (5) :

Ids ＝ (β/2) (ELVDD -Vdata) ² (5)

As can be seen from equation (5) , Vth term can be removed. So, DTFT Vth can be compensated.

Some kinds of the pixel circuits have been proposed for compensating the LTPS-TFT variations, as is disclosed in, for example, Japanese Patent Application, Publication No. 2006-039544 and Japanese Patent Application, Publication No. 2008-158477.

The pixel circuit compensation method in the prior art is useful for the OLED current control to avoid the TFT’s Vth variations. However, the prior circuit has two major issues. Firstly, the compensation time is less than 1HS because data writing and Vth compensation are performed in the same period.

Secondly, the prior compensation circuit for Vth of DTFT uses a diode connection as shown in Fig. 6 (b) and Fig. 8. The diode connection does not work if Vth of DTFT is a negative value.

SUMMARY

The objectives of the pixel circuit according to the present invention are to solve the problems of the prior pixel circuit as follows: (i) longer compensation time (over 1HS) cannot be selected, and (ii) a negative Vth cannot be compensated. In order to achieve the objective (i) , the pixel circuit according to the present invention can separate the Vth compensation period and the data writing period. Also, in order to achieve the objective (ii) , a source follower type compensation circuit is used for the pixel circuit. To solve these issues it will be expected much higher image quality of the OLED display. Also, TFTs which have a wider range of Vth characteristics can be applied to the OLED display.

According to a first aspect, a display device comprising a plurality of pixel circuits is provided, each pixel circuit comprises:

a light emitting diode (LED) having anode and cathode terminals；

a driving transistor having source, drain, and gate terminals；

first, second, third, fourth, and fifth transistors for switching, each of them having first, second, and control terminals； and

first and second capacitors, each of them having first and second terminals.

The first terminals of the first transistor and the first capacitor are connected to a first power line, the second terminal of the first transistor is connected to the first terminal of the second transistor and the source of the driving transistor, the gate of the driving transistor is connected to the first terminals of the second capacitor and the third transistor, the drain of the driving transistor is connected to the first terminal of the fourth transistor and the anode of the LED, the cathode of the LED is connected to a second power line, the second terminal of the first capacitor is connected to the second terminals of the second transistor and the second capacitor, and the first terminal of the fifth transistor, the second terminal of the fifth transistor is connected to a data line, the second terminals of the third and fourth transistors are connected to an initialization line, the control terminal of the first transistor is connected to an emission line, the control terminals of the second, third and fourth transistors are connected to a compensation line, and the control terminal of the fifth transistor is connected to a scan line.

During a first period for initialization and compensation, the compensation line is active so that the second, third and fourth transistors are on, and a voltage across the second capacitor becomes a threshold voltage of the driving transistor；

during a second period for data writing, the scan line is active so that the fifth transistor is on, and a voltage of the data line is written in the pixel circuit； and

during a third period for emission, the emission line is active so that the first transistor is on, a driving current flows through the first transistor, the driving transistor, and the LED, and the LED emits light.

According to the first aspect, the pixel circuit can separate the Vth compensation period and the data writing period. So, the Vth compensation period longer than 1HS can be selected. The compensation ability increases when the duration for compensation becomes longer. Thus, much higher image quality of the LED display can be expected.

Furthermore, according to the first aspect, a source follower type compensation circuit is used for the pixel circuit. So, the pixel circuit can compensate both positive and negative Vth of the DTFT. Namely, the pixel circuit supports both positive and negative Vth values of the DTFT. Thus, TFTs which have a wider range of Vth characteristics can be applied to the LED display.

In a first possible implementation manner of the first aspect, the first period is longer than the second period.

According to the first possible implementation manner, the Vth compensation period is longer than 1HS. Thus, the compensation ability increases, and much higher image quality of the LED display can be expected.

In a second possible implementation manner of the first aspect, the first period does not coincide with the second period.

According to the second possible implementation manner, the pixel circuit can separate the Vth compensation period and the data writing period. So, the Vth compensation period longer than 1HS can be selected. Thus, the compensation ability increases, and much higher image quality of the LED display can be expected.

According to a second aspect, a method for operating a pixel circuit is provided, the pixel circuit comprises a light emitting diode (LED) ； and a driving transistor connected to the LED.

During a first period for initialization and compensation, a compensation line is active, and a threshold voltage of the driving transistor is compensated；

during a second period for data writing, a scan line is active, and a voltage of a data line is introduced in the pixel circuit； and

during a third period for emission, an emission line is active, a driving current flows through the driving transistor and the LED, and the LED emits light.

BRIEF DESCRIPTION OF DRAWINGS

To describe the technical solutions in the embodiments of the present invention or in the prior art more clearly, the following briefly introduces the accompanying drawings required for describing the embodiments or the prior art. Apparently, the accompanying drawings in the following description show merely some embodiments of the present invention, and a person of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts.

FIG. 1 illustrates a schematic diagram of an OLED display panel；

FIG. 2 illustrates a circuit diagram of the LTPS-TFT back plane；

FIG. 3 illustrates an example of a De-MUX circuit；

FIG. 4 illustrates a circuit diagram of a pixel circuit in the prior art；

FIG. 5 illustrates a timing sequence for driving the pixel circuit；

FIG. 6 (a) illustrates a current flow during a DTFT initial period；

FIG. 6 (b) illustrates current flows during a data writing and Vth compensation period；

FIG. 6 (c) illustrates a current flow during an emission period；

FIG. 7 illustrates relationship between compensation time and OLED driving current error rate；

FIG. 8 illustrates a diode connection of a DTFT；

FIG. 9 illustrates a circuit diagram of a pixel circuit according to the present invention；

FIG. 10 illustrates a timing sequence for driving the pixel circuit；

FIG. 11 illustrates a circuit diagram of a panel circuit；

FIG. 12 (a) illustrates the operation during a DTFT initialization, Vth compensation, and OLED discharge period；

FIG. 12 (b) illustrates the operation during a data writing period；

FIG. 12 (c) illustrates the operation during an emission period；

FIG. 13 illustrates another panel circuit according to the present invention； and

FIG. 14 illustrates another timing sequence for driving another pixel circuit according to the present invention.

DESCRIPTION OF EMBODIMENTS

The following clearly describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. The described embodiments are merely some but not all of the embodiments of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

Fig. 9 shows a circuit diagram of a pixel circuit according to embodiments of present invention. This pixel circuit is formed of six TFTs and two capacitors. The pixel circuit comprises a light emitting diode such as an organic light emitting diode OLED, a driving thin film transistor DTFT, a first switching TFT M4, a second switching TFT M2, a third switching TFT M3, a fourth switching TFT M6, a fifth switching TFT M5, a first capacitor C1, and a second capacitor C2.

First terminals of M4 and C1 are connected to a first power line ELVDD. A second terminal of M4 is connected to a first terminal of M2 and a source of DTFT. A gate of DTFT is connected to first terminals of C2 and M3. A drain of DTFT is connected to a first terminal of M6 and an anode of OLED. A cathode of OLED is connected to a second power line ELVSS. Second terminals of C1, C2 and M2, and a first terminal of M5 are connected to node A. A second terminal of M5 is connected to a data line Vdata. Second terminals of M3 and M6 are connected to an initialization line VINIT.

A control terminal of M4 is connected to an emission line EM. Control terminals of M2, M3 and M6 are connected to a compensation line Comp. A control terminal of M5 is connected to a scan line G (n) .

Fig. 10 shows a timing sequence for driving the pixel circuit. During a first period (a) , the compensation line Comp becomes low level (active) so that M2, M3 and M6 turn on, and a voltage across C2 becomes a threshold voltage Vth of DTFT. Duration of the first period (a) for initialization and compensation can be longer than 1HS. In this timing sequence, duration of the first period (a) is 2HS. The duration can be longer than 3HS. The compensation ability increases when the duration for compensation becomes longer. During a second period (b) , the scan line G (n) becomes low level (active) so that M5 turns on, and a voltage of the data line Vdata is written in the pixel circuit. During a third period (c) , the emission line EM becomes low level (active) so that M4 turns on, a driving current Ids flows through M4, DTFT and OLED, and OLED emits light.

Fig. 11 shows a circuit diagram of a panel circuit for a display device. This display device can be provided in various electronic devices, but not limited to, a smart phone, a mobile device, a computer, a television, etc. Lines Comp (n) , EM (n) , and data (m) in Fig. 11 are shown as Comp, EM, and Vdata in Figs. 9 and 10, respectively. In Fig. 11, compensation lines Comp (n-1) , Comp (n) , …from a Comp Driver 1, scan lines G (n-1) , G (n) , …from a Scan Driver 2, emission lines EM (n-1) , EM (n) , …from an Emission Driver 3, and data lines data (m-1) , data (m) , …from a De-MUX Circuit 5 are connected to an array of the pixel circuits 4. Scan lines G (n-1) , G (n) , …become low level in turn for each 1HS (one horizontal sync period) .

The operation of the pixel circuit will be described with reference to Fig. 12 (a) to Fig. 12 (c) . Fig. 12 (a) shows the operation of DTFT initialization, Vth compensation, and OLED discharge during the period (a) in Fig. 10. According to Fig. 10, Comp is low level (active) , and G (n) and EM are high level (non-active) during the period (a) . So, in Fig. 12 (a) , M2, M3 and M6 are “ON” , and M4 is “OFF” . So, voltages of DTFT’s gate and OLED’s anode are initialized to a voltage of VINIT. Node A and DTFT’s source are conducted through M2. So, a voltage of node A becomes VA as shown in equation (6) in accordance with source follower effect:

VA ＝ VINIT + Vth (6)

where Vth is a threshold voltage of DTFT. If Vth is a positive value, VA is higher than VINIT. If Vth is a negative value, VA is lower than VINIT. Namely, this pixel circuit supports both positive and negative Vth values of DTFT.

Fig. 12 (b) shows the operation of data writing during the period (b) in Fig. 10. According to Fig. 10, G (n) is low level, and Comp and EM are high level in the period (b) . So, in Fig. 12 (b) , M5 is “ON” , and M2, M3, M4 and M6 are “OFF” . So, a voltage of the node A becomes a voltage of Vdata. Eventually, a voltage of DTFT’s gate becomes VG as shown in equation (7) :

VG ＝ VINIT + (C2/Ct) (Vdata - (VINIT + Vth)) (7)

where Ct ＝ C1 + C2.

Fig. 12 (c) shows the operation of emission during the period (c) in Fig. 10. According to Fig. 10, EM is low level, and Comp and G (n) are high level in the period (c) . So, in Fig. 12 (c) , M4 is “ON” , and M2, M3 and M6 are “OFF” . So, a driving current Ids flows through M4, DTFT and OLED. When C1 and C2 are selected as C1 << C2, Ids is shown as equation (8) :

Ids ＝ (β/2) ( (C2/Ct) (ELVDD -Vdata) ) ² (8)

where β is a parameter related to design and characteristics of LTPS-TFT consisting of width W, length L and mobility of the TFT.

As can be seen from equation (8) , Vth term is removed. So, the pixel circuit in Fig. 9 can compensate Vth of DTFT.

The prior circuit has two major issues. Firstly, the compensation time is less than 1HS because data writing and Vth compensation are performed in the same period. In addition, compensation time would be half of 1HS when the De-Mux driving is applied as shown in Fig. 5. The compensation method of the prior pixel circuit is used for the data voltage. So, the data voltage must be charged to the data line before the start of the compensation operation. Fig. 7 shows relationship between compensation time and OLED driving current error rate. The compensation ability will decrease (current error rate will increase) when the compensation time becomes shorter. In fact, the compensation ability will decrease when being applied to the high resolution panel, because the compensation time which is 1HS becomes shorter.

Secondly, the prior compensation circuit for Vth of DTFT uses a diode connection as shown in Fig. 6 (b) and Fig. 8. The diode connection does not work if Vth of DTFT is a negative value. Generally, Vth of TFT depends on a LTPS process and there is a possibility that Vth becomes a negative value. So, it is desired that the compensation circuit works even if Vth is a negative value. Namely, the compensation circuit for Vth of both polarities, positive and negative, is desired.

Both problem (i) and problem (ii) can be solved by the aforementioned embodiment.

The good operation results of the Vth compensation were confirmed by simulation of waveforms in the pixel circuit according to the present invention.

The pixel circuit according to the present invention can separate the Vth compensation period and the data writing period. Thus, the Vth compensation period longer than 1HS can be selected. The compensation ability increases when the Vth compensation period becomes longer. So, the pixel circuit according to the present invention can solve the pixel circuit issues in the prior art. It will be expected much higher image quality of the OLED display. Also, TFTs which have a wider range of Vth characteristics can be applied to the OLED display.

The following describes alternative solutions for the above-mentioned objectives of the present invention. Fig. 13 and Fig. 14 show another panel circuit and timing sequence thereof according to the present invention. In this panel circuit, Comp Driver 1 in Fig. 11 is removed, and the compensation lines Comp (n-1) , Comp (n) , …is replaced with the scan lines G (n-2) , G (n-1) , …Thus, duration of period (a) in Fig. 14 for initialization and Vth compensation is fixed at 1HS. However, Comp Driver 1 is removed, and the constitution of the panel circuit is simplified.

In the prior art, the compensation time is less than 1HS because data writing and Vth compensation are performed in the same period. In addition, Vth compensation time would be half of 1HS when the De-Mux driving is applied. On the other hand, in the alternative embodiment of the present invention, Vth compensation time is fixed at 1HS. Thus, the aforementioned problem (i) can be solved by the alternative embodiment.

Furthermore, a source follower type compensation circuit is also used for the pixel circuit in the alternative embodiment. Thus, the aforementioned problem (ii) can be solved.

What is disclosed above is merely exemplary embodiments of the present invention, and certainly is not intended to limit the protection scope of the present invention. A person of ordinary skill in the art may understand that all or some of processes that implement the foregoing embodiments and equivalent modifications made in accordance with the claims of the present invention shall fall within the scope of the present invention.

Claims

A pixel circuit, comprising:

a light emitting diode (LED) having anode and cathode terminals；

a driving transistor having source, drain, and gate terminals；

first, second, third, fourth, and fifth transistors for switching, each of them having first, second, and control terminals； and

first and second capacitors, each of them having first and second terminals,

wherein the first terminals of the first transistor and the first capacitor are connected to a first power line, the second terminal of the first transistor is connected to the first terminal of the second transistor and the source of the driving transistor, the gate of the driving transistor is connected to the first terminals of the second capacitor and the third transistor, the drain of the driving transistor is connected to the first terminal of the fourth transistor and the anode of the LED, the cathode of the LED is connected to a second power line, the second terminal of the first capacitor is connected to the second terminals of the second transistor and the second capacitor, and the first terminal of the fifth transistor, the second terminal of the fifth transistor is connected to a data line, the second terminals of the third and fourth transistors are connected to an initialization line, the control terminal of the first transistor is connected to an emission line, the control terminals of the second, third and fourth transistors are connected to a compensation line, and the control terminal of the fifth transistor is connected to a scan line,

wherein during a first period for initialization and compensation, the compensation line is active so that the second, third and fourth transistors are on, and a voltage across the second capacitor becomes a threshold voltage of the driving transistor；

during a second period for data writing, the scan line is active so that the fifth transistor is on, and a voltage of the data line is written in the pixel circuit； and

during a third period for emission, the emission line is active so that the first transistor is on, a driving current flows through the first transistor, the driving transistor, and the LED, and the LED emits light.
The pixel circuit according to claim 1, wherein the first period is longer than the second period.
The pixel circuit according to claim 1, wherein the first period does not coincide with the second period.
A display device comprising a plurality of pixel circuits according to any of claims 1 to 3.
An electronic device comprising a display device according to claim 4.
A system comprising at least one of electronic device according to claim 5.
A method for operating a pixel circuit, the pixel circuit comprises a light emitting diode (LED) ； and a driving transistor connected to the LED,

wherein during a first period for initialization and compensation, a compensation line is active, and a threshold voltage of the driving transistor is compensated；

during a second period for data writing, a scan line is active, and a voltage of a data line is introduced in the pixel circuit； and

during a third period for emission, an emission line is active, a driving current flows through the driving transistor and the LED, and the LED emits light.