Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P30/00—Ion implantation into wafers, substrates or parts of devices
  • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
  • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
  • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
  • H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing

Definitions

• This disclosure relates to a method for manufacturing a power semiconductor device.
• a vertical IGBT Insulated Gate Bipolar Transistor
• a vertical diode is composed of, from the surface side, a p-type anode, an n-type drift layer, an n-type buffer layer, and an n-type cathode layer.
• Patent Document 1 discloses an IGBT with a vertical structure. Thinning IGBTs and diodes is effective in reducing losses, but it also has the adverse effect of reducing the margin for voltage snap-off. As a countermeasure, a wide n-type buffer layer is used.
• Patent Document 1 describes a method for manufacturing a buffer layer using proton (hydrogen ion) irradiation or implantation (hereinafter, both will be referred to as irradiation) and annealing.
• irradiation proton (hydrogen ion) irradiation or implantation
• annealing a method for manufacturing a buffer layer using proton (hydrogen ion) irradiation or implantation (hereinafter, both will be referred to as irradiation) and annealing.
• irradiation proton (hydrogen ion) irradiation or implantation
• Patent documents 2 and 3 describe methods for manufacturing a buffer layer without using proton irradiation.
• Patent document 2 describes a method for bonding wafers with different concentrations.
• Patent document 3 describes a method for manufacturing a buffer layer using multi-stage epitaxial growth.
• Patent Documents 1 to 3 When forming a wide n-type buffer layer in an IGBT or diode, the methods described in Patent Documents 1 to 3 have the following problems.
• the multi-stage proton irradiation described in Patent Document 1 involves a large number of irradiations, which causes excess damage to accumulate in the silicon wafer. There is also the problem of interfaces forming between the regions where donors are formed by each irradiation.
• the bonding method described in Patent Document 2 inevitably results in the problem of bonding interfaces forming.
• the multi-stage epitaxial growth described in Patent Document 3 is vapor phase growth, which inherently takes a long time to manufacture.
• This disclosure has been made to solve the above problems, and aims to form a wide buffer layer with minimal damage accumulation and no interfaces.
• the method for manufacturing a power semiconductor device disclosed herein involves introducing hydrogen into a silicon wafer having a first main surface and a second main surface opposite the first main surface, into a region including at least a first region extending from the second main surface to a predetermined depth, irradiating the silicon wafer with a penetrating electron beam to form defects in the first region and a second region between the first region and the first main surface, heat-treating the silicon wafer to react the hydrogen with the defects to form donors, and then laser annealing from the first or second main surface of the silicon wafer to inactivate the donors in the second region and turn the first region into a buffer layer.
• the disclosed method for manufacturing a power semiconductor device involves introducing hydrogen, penetrating electron beam irradiation, heat treatment, and laser annealing, leaving donors only in the first region, which can be formed as a buffer layer. Therefore, a wide buffer layer can be formed with minimal damage accumulation and no interface.
• 3 is a flowchart showing a method for manufacturing the power semiconductor device according to the first embodiment.
• 3A to 3C are cross-sectional views showing a manufacturing process of the power semiconductor device according to the first embodiment.
• 3A to 3C are cross-sectional views showing a manufacturing process of the power semiconductor device according to the first embodiment.
• 3A to 3C are cross-sectional views showing a manufacturing process of the power semiconductor device according to the first embodiment.
• 3A to 3C are cross-sectional views showing a manufacturing process of the power semiconductor device according to the first embodiment.
• 3A to 3C are cross-sectional views showing a manufacturing process of the power semiconductor device according to the first embodiment.
• 3A to 3C are cross-sectional views showing a manufacturing process of the power semiconductor device according to the first embodiment.
• 3A to 3C are cross-sectional views showing a manufacturing process of the power semiconductor device according to the first embodiment.
• 3A to 3C are cross-sectional views showing a manufacturing process of the power semiconductor device according to the first embodiment.
• 3A to 3C are cross-sectional views showing a manufacturing process of the power semiconductor device according to the first embodiment.
• 3A to 3C are cross-sectional views showing a manufacturing process of the power semiconductor device according to the first embodiment.
• FIG. 10 is a diagram showing the temperature dependence of the areal density of donors.
• 10A to 10C are cross-sectional views showing a manufacturing process of a power semiconductor device according to a second embodiment.
• 10A to 10C are cross-sectional views showing a manufacturing process of a power semiconductor device according to a second embodiment.
• 10A to 10C are cross-sectional views showing a manufacturing process of a power semiconductor device according to a second embodiment.
• 10A to 10C are cross-sectional views showing a manufacturing process of a power semiconductor device according to a second embodiment.
• 10A to 10C are cross-sectional views showing a manufacturing process of a power semiconductor device according to a second embodiment.
• 10A to 10C are cross-sectional views showing a manufacturing process of a power semiconductor device according to a second embodiment.
• 10 is a diagram showing a hydrogen concentration distribution in a power semiconductor device according to a second embodiment.
• 10 is a flowchart showing a method for manufacturing a power semiconductor device according to a third embodiment.
• 10A to 10C are cross-sectional views showing a manufacturing process of a power semiconductor device according to a third embodiment.
• the donors that contribute to the formation of the buffer layer are formed by combining point defects and hydrogen present in the silicon wafer.
• Point defects are localized disturbances in the crystal lattice and are divided into vacancy-type and interstitial silicon-type.
• the dangling bonds of the point defects are shielded by the hydrogen, resulting in no intraband level.
• shallow donor-type levels may form.
• it is possible to control the carrier concentration by controlling the donors formed in the silicon wafer and form a buffer layer in a power semiconductor device. This results in softer switching waveforms in the power semiconductor device, preventing snap-off or oscillation.
• Donors are usually formed in silicon wafers using proton irradiation, but they can also be formed by combining helium ion irradiation with some kind of hydrogen introduction process.
• annealing causes the donor generation region to expand toward the back side of the silicon wafer, making it possible to form a buffer layer of the desired thickness on the back side of the device. If this expansion width is small, a high-resistance region will remain on the back side of the device, resulting in poor performance of the power semiconductor device.
• multi-stage irradiation is performed to obtain a wide buffer layer, unnecessary damage will accumulate in the silicon. Therefore, the following embodiment describes a method for forming a buffer layer of the desired width without using multi-stage irradiation.
• Fig. 1 is a flowchart showing a method for manufacturing a power semiconductor device according to the first embodiment.
• Figs. 2 to 11 are cross-sectional views showing the manufacturing process of the power semiconductor device according to the first embodiment.
• the method for manufacturing the power semiconductor device according to the first embodiment will be described below with reference to these figures. Note that, as an example, a method for manufacturing a vertical IGBT or a vertical diode from an n-type or n-type silicon wafer will be described here.
• a silicon wafer 1 shown in Fig. 2 is prepared.
• the silicon wafer 1 is cut from an ingot and has a first main surface S1, which is the front surface, and a second main surface S2, which is the back surface opposite to the first main surface S1.
• the hydrogen concentration of the silicon wafer 1 is, for example, 1 ⁇ 10 13 cm -3 or less.
• the thickness of the silicon wafer 1 at this stage is W1.
• a hydrogen introduction process is performed to control the hydrogen concentration in the silicon wafer 1.
• the silicon wafer 1 is annealed in either a hydrogen gas or hydrogen plasma atmosphere.
• the silicon wafer 1 is exposed to a hydrogen atmosphere and annealed in a furnace such as a vertical furnace at a temperature range of 1000°C to 1300°C (627K to 1027K).
• a furnace such as a vertical furnace at a temperature range of 1000°C to 1300°C (627K to 1027K).
• the hydrogen penetration depth in the silicon is 1.7cm. Therefore, hydrogen can be impregnated throughout the entire depth direction of the silicon wafer 1 for power semiconductors.
• Figure 3 shows the silicon wafer 1 in this state, with the areas where hydrogen has been introduced indicated by matte hatching.
• the region of silicon wafer 1 that will become the buffer layer in a later process is referred to as the first region, and the region that will become the drift layer and anode layer or MOS structure in a later process is referred to as the second region.
• hydrogen was introduced into the entire depth direction of silicon wafer 1, i.e., into both the first and second regions, but it is sufficient that hydrogen is introduced into at least the first region.
• step S102 of FIG. 1 an electron beam irradiation process is performed in which an electron beam is irradiated from the second main surface S2 of the silicon wafer 1.
• an accelerator is used to irradiate the second main surface S2 of the silicon wafer 1 with electrons accelerated to between several hundred KeV and several tens of MeV.
• the electron beam penetrates the silicon wafer 1 for use as a power semiconductor, and point defects 2 are formed throughout the entire thickness of the silicon wafer 1, as shown in FIG. 4. In other words, point defects 2 are formed in both the first and second regions.
• the dose of the electron beam depends on the amount of point defects to be formed, but is, for example, 1 ⁇ 10 12 or more and 1 ⁇ 10 16 cm ⁇ 2 or less.
• the second main surface S2 of the silicon wafer 1 may be irradiated with protons or helium ions instead of the electron beam to form point defects 2 in localized portions of the silicon wafer.
• a donor activation annealing process is performed to form donors 3.
• the silicon wafer 1 is exposed to an inert gas atmosphere such as nitrogen, and annealed at a temperature of 200°C to 500°C. This process causes hydrogen in the silicon wafer 1 to react with point defects 2, forming donors 3 throughout the entire thickness of the silicon wafer 1, as shown in FIG. 5.
• Figure 12 shows the temperature dependence of donor areal density (cm -2 ). As shown in Figure 12, annealing at temperatures lower than 200°C is not preferred because it reduces the efficiency of donor formation. Also, annealing at temperatures higher than 500°C is not preferred because it significantly reduces the annihilation of donors. Therefore, the annealing temperature for donor activation is preferably 200°C or higher and 500°C or lower. The concentration of donors 3 can also be adjusted by the annealing time.
• a local donor passivation annealing process is performed to locally passivate the donors 3 formed in the second region of the silicon wafer 1.
• light in a wavelength band absorbed by silicon is irradiated onto the first main surface S1 of the silicon wafer 1.
• This causes a local temperature rise near the first main surface S1 of the silicon wafer 1, and heat is conducted in the direction from the first main surface S1 toward the second main surface S2.
• the donors 3 are passivated in the region where the temperature of the silicon has risen to 500°C or higher.
• a laser annealing device or lamp annealing device is used to irradiate light in this process.
• the wavelength, power density, and irradiation time of the light are adjusted so that the donor 3 in the first region of the silicon wafer 1 is not deactivated.
• the first region where the donor 3 remains undeactivated becomes a buffer layer 11.
• This buffer layer 11 is also referred to as the first buffer layer.
• a surface structure formation process is performed to form a surface structure for the device on the first main surface S1 side of the silicon wafer 1.
• the surface structure is also referred to as the first main surface structure.
• a p+ type anode layer 14 is formed on the first main surface S1 of the silicon wafer 1, and an anode electrode 15 is formed on the anode layer 14.
• a p-type base region is formed on the surface of the silicon wafer 1, an n-type source region is formed, the silicon wafer 1 is dry-etched to form a trench gate, a gate oxide film is formed, a gate electrode made of polysilicon or the like is formed, an interlayer insulating film made of TEOS or the like is formed, and a source electrode is formed.
• a wafer grinding process is performed in which the second main surface S2 is ground to reduce the silicon wafer 1 to the desired thickness.
• the second main surface S2 of the silicon wafer 1 is ground using a grinding method such as CMP (Chemical Mechanical Polish).
• CMP Chemical Mechanical Polish
• the silicon wafer 1 after grinding will be referred to as the semiconductor region.
• the thickness of the silicon wafer 1 after grinding will be referred to as W2.
• a second buffer layer formation process is performed to form a second buffer layer on the second main surface S2 of the silicon wafer 1.
• an n-type second buffer layer 12 is formed by implanting n-type dopant ions such as phosphorus into the second main surface S2.
• the second buffer layer 12 may be formed by multiple ion implantations.
• the second buffer layer 12 may be omitted and substituted with the first buffer layer 11.
• a back surface structure formation process is performed to form a back surface structure of the device on the second main surface S2 of the silicon wafer 1.
• the back surface structure of the device will also be referred to as the second main surface structure.
• an n+ type cathode layer 16 is formed on the second main surface S2 of the silicon wafer 1, as shown in FIG. 10.
• RFC Relaxed Field of Cathode
• a p+ type cathode layer is partially formed in addition to the n+ type cathode layer.
• a p+ type collector layer is formed on the back surface of the silicon wafer 1.
• an RC (Reverse Conductive) IGBT an n+ cathode layer is partially formed in addition to the collector layer.
• a back electrode is formed on the second main surface S2 of the silicon wafer 1.
• the back electrode is the cathode electrode 17 shown in FIG. 11.
• the back electrode is the collector electrode. This completes the method for manufacturing a power semiconductor device according to embodiment 1.
• Figure 13 shows a schematic diagram of the hydrogen concentration distribution in a power semiconductor device according to embodiment 1.
• the solid line shows the hydrogen concentration when the annealing temperature is high or the annealing time is long in the range of 200°C or higher and 500°C or lower.
• the dashed line shows the hydrogen concentration when the annealing temperature is lower or the annealing time is short compared to the solid line in the range of 200°C or higher and 500°C or lower.
• the power semiconductor device manufacturing method can form a wide first buffer layer 11 with no internal interface in a short time without accumulating damage to the silicon wafer 1 through the hydrogen introduction process, electron beam irradiation process, donor activation annealing process, and donor local passivation annealing process.
• the surface structure forming process, wafer grinding process, second buffer forming process, back surface structure forming process, and back surface electrode forming process are not limited to the above example, and other general IGBT or diode manufacturing methods can also be applied.
• the first buffer layer (steps S101 to S104 in FIG. 1) is formed before the device structure (steps S105 to S109 in FIG. 1).
• the first buffer layer is formed after the device structure is formed.
• the device structure places restrictions on the subsequent annealing temperature and annealing time.
• metal electrodes are generally used for the surface electrodes of power devices, after the surface structure is formed, it is not possible to input heat to the silicon wafer 1 by irradiating it with light from the front side. Therefore, in the method for manufacturing a power semiconductor device according to the second embodiment, heat is input to the silicon wafer 1 by irradiating it with light from the back side.
• FIG. 14 is a flowchart showing a method for manufacturing a power semiconductor device according to embodiment 2.
• the method for manufacturing a power semiconductor device according to embodiment 2 will be explained in accordance with the flow of FIG. 14. Note that, as an example, a method for manufacturing a vertical IGBT or a vertical diode from an n-type or n-type silicon wafer will be explained.
• a silicon wafer 1 with a thickness W1 is prepared, as in embodiment 1.
• a device surface structure is formed on the first main surface S1 of the silicon wafer 1.
• a p+ type anode layer 14 is formed on the first main surface S1 of the silicon wafer 1, and an anode electrode 15 is formed on the anode layer 14.
• the area of the silicon wafer 1 other than the anode layer 14 becomes the drift layer 13. This step is similar to step S105 of FIG. 1.
• step S202 a wafer grinding process is performed in which the second main surface S2 is ground to reduce the silicon wafer 1 to the desired thickness.
• This step is similar to step S106 in Figure 1. As a result of this process, the thickness of the silicon wafer 1 becomes W2.
• step S203 a second buffer layer formation process is performed in which a second buffer layer 12 is formed on the second main surface S2 of the silicon wafer 1. This step is similar to step S107 in Figure 1.
• step S204 a back surface structure formation process is performed to form a back surface structure of the device on the second main surface S2 of the silicon wafer 1.
• a back surface structure formation process is performed to form a back surface structure of the device on the second main surface S2 of the silicon wafer 1.
• an n+ type cathode layer 16 is formed on the second main surface S2 of the silicon wafer 1, as shown in FIG. 17. This step is similar to step S108 in FIG. 1.
• step S205 a hydrogen introduction process is performed to control the hydrogen concentration in the silicon wafer 1.
• This step is similar to step S101 in Figure 1, but the upper limit of the annealing temperature is set so that the surface structure is not destroyed, for example, 500°C or less.
• hydrogen should be introduced into at least the first region of the silicon wafer 1.
• step S206 an electron beam irradiation process is performed in which an electron beam is irradiated from the second main surface S2 of the silicon wafer 1 to form point defects 2.
• This step is similar to step S102 in Figure 1.
• Figure 18 shows the silicon wafer 1 in which point defects 2 have been formed by this process.
• step S207 a donor activation annealing process is performed to form donors 3.
• This step is similar to step S103 in Figure 1.
• Figure 19 shows the silicon wafer 1 after donors 3 have been formed through this process.
• step S208 a local donor passivation annealing process is performed to locally passivate the donors 3 formed in the second region of the silicon wafer 1.
• the first main surface S1 was irradiated with light in a wavelength band absorbed by silicon, but in this embodiment, the second main surface S2 is irradiated with pulsed laser light in a wavelength band not absorbed by silicon.
• the optical power is strong, local light absorption can occur only at the focal position of the incident light due to the nonlinear optical effect. In other words, it is possible to raise the temperature of only the deep portion to 500°C or higher without heating the second main surface S2 of the silicon wafer 1.
• the donors 3 generated in the donor activation annealing process are passivated.
• the donors 3 in the second region can be passivated.
• the region of the drift layer 13 where the donors 3 remain becomes the buffer layer 11.
• step S209 a backside electrode is formed on the second main surface S2 of the silicon wafer 1.
• step S209 a backside electrode is formed on the second main surface S2 of the silicon wafer 1. This step is the same as step S109 in Figure 1. This completes the method for manufacturing a power semiconductor device according to embodiment 2.
• Figure 21 schematically shows the hydrogen concentration distribution in a power semiconductor device according to embodiment 2.
• W3 is the total thickness of the first buffer layer 11, the second buffer layer 12, and the back surface structure.
• Figure 21 shows the case where hydrogen is introduced mainly into the first region of the silicon wafer 1 in step S205.
• the power semiconductor device manufacturing method can form a wide first buffer layer 11 with no internal interface in a short time without accumulating damage to the silicon wafer 1 through the hydrogen introduction process, electron beam irradiation process, donor activation annealing process, and donor local passivation annealing process.
• the surface structure forming process, wafer grinding process, second buffer forming process, back surface structure forming process, and back surface electrode forming process are not limited to the above example, and other general IGBT or diode manufacturing methods can also be applied.
• donors 3 are formed in the first and second regions of the silicon wafer 1, and then the donors 3 are locally inactivated in the second region, thereby forming the donors 3 only in the first region.
• donors 3 are formed locally in the first region of the silicon wafer 1 by annealing using light.
• FIG. 22 is a flowchart showing a method for manufacturing a power semiconductor device according to embodiment 3. Below, the method for manufacturing a power semiconductor device according to embodiment 3 will be explained in accordance with the flow of FIG. 22. Note that, as an example, a method for manufacturing a vertical IGBT or a vertical diode from an n-type or n-type silicon wafer will be explained.
• a silicon wafer 1 with a thickness W1 is prepared, as in embodiments 1 and 2.
• the subsequent processing from steps S301 to S306 is the same as steps S201 to S206 in Figure 14, and the processing shown in Figures 15 to 18 is performed.
• a donor local activation annealing process is performed to locally convert point defects 2 in the semiconductor region into donors.
• an annealing process is performed in which light such as laser annealing or lamp annealing is irradiated onto the second main surface S2 of the silicon wafer 1. This raises the temperature of the first region of the silicon wafer 1 to a donor formation temperature or higher, for example, 200°C or higher, and donors 3 are formed locally in the first region.
• the annealing temperature in this process is preferably between 200°C and 500°C.
• the light intensity and irradiation time are adjusted so that the donor concentration becomes the desired value. In this process, of the point defects 2 formed in the silicon wafer 1 by electron beam irradiation, only those present in the first region are converted into donors 3, and the first region becomes the first buffer layer 11.
• step S308 a backside structure formation process is performed to form a backside structure for the device on the second main surface S2 of the silicon wafer 1.
• This step is similar to step S108 in FIG. 1 and step S204 in FIG. 14. This completes the method for manufacturing a power semiconductor device according to embodiment 3.
• the hydrogen concentration distribution in the power semiconductor device according to embodiment 3 is as shown in Figure 21.
• the power semiconductor device manufacturing method makes it possible to form a wide first buffer layer 11 with no internal interface in a short time without accumulating damage to the silicon wafer 1 through the hydrogen introduction process, electron beam irradiation process, and donor local activation annealing process.
• the surface structure forming process, wafer grinding process, second buffer forming process, back surface structure forming process, and back surface electrode forming process are not limited to the above example, and other general IGBT or diode manufacturing methods can also be applied.
• an electron beam irradiation step is performed.
• the electron beam irradiation step is not essential.
• the hydrogen introduction process, electron beam irradiation process, donor activation annealing process, and donor local deactivation annealing process were performed before the surface structure formation process.
• Performing the hydrogen introduction process before the surface structure formation process has the advantage of allowing the processing temperature of the hydrogen introduction process to be higher.
• the hydrogen introduction process, electron beam irradiation process, donor activation annealing process, and donor local deactivation annealing process may also be appropriately incorporated after the surface structure formation process.
• the order of the hydrogen introduction process and electron beam irradiation process may also be reversed.
• the donor activation annealing process and donor local deactivation annealing process are performed in that order, and the order of each process can be changed as appropriate, as long as the silicon does not subsequently reach a temperature higher than 500°C (more preferably 400°C).
• the hydrogen introduction process, electron beam irradiation process, donor activation annealing process, and donor local passivation annealing process were performed after the back surface structure formation process, but these processes may be appropriately incorporated after the front surface structure formation process and before the back surface structure formation process.
• the order of the hydrogen introduction process and electron beam irradiation process may also be reversed. That is, after the hydrogen introduction process and electron beam irradiation process are performed, the donor activation annealing process and donor local passivation annealing process are performed in that order, and the order of each process can be changed as appropriate, as long as the silicon does not subsequently reach a temperature higher than 500°C (more preferably 400°C).
• the hydrogen introduction process, electron beam irradiation process, and donor local activation annealing process were performed after the back surface structure formation process, but these processes may be appropriately incorporated after the front surface structure formation process and before the back surface structure formation process.
• the order of the hydrogen introduction process and electron beam irradiation process may also be reversed. That is, the hydrogen introduction process and electron beam irradiation process are performed followed by the donor local activation annealing process, and the order of each process can be changed as appropriate, as long as the silicon does not subsequently reach a temperature higher than 500°C (more preferably 400°C).
• the hydrogen introduction process is performed on the surface of the silicon wafer, but the hydrogen introduction process may also be performed on the side surface, etc., in addition to the surface.
• the hydrogen introduction process involves annealing the silicon wafer 1 in an atmosphere of either hydrogen gas or hydrogen plasma.
• hydrogen can also be introduced into the silicon wafer 1 by annealing the silicon wafer 1 in a state in which a hydrogen-containing film has been deposited on the silicon wafer 1, or by immersing the silicon wafer 1 in a chemical solution containing hydrogen, i.e., an acidic liquid.
• diodes or IGBTs have been cited as examples of power semiconductor devices manufactured using the manufacturing methods of each embodiment, but MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), SBDs (Schottky Barrier Diodes), Thyristors, etc. may also be formed.
• MOSFETs Metal Oxide Semiconductor Field Effect Transistors
• SBDs Schottky Barrier Diodes
• Thyristors etc.

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