WO2025105425A1 - 蒸着マスク、及び電子デバイスの製造方法 - Google Patents

蒸着マスク、及び電子デバイスの製造方法 Download PDF

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Publication number
WO2025105425A1
WO2025105425A1 PCT/JP2024/040446 JP2024040446W WO2025105425A1 WO 2025105425 A1 WO2025105425 A1 WO 2025105425A1 JP 2024040446 W JP2024040446 W JP 2024040446W WO 2025105425 A1 WO2025105425 A1 WO 2025105425A1
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Prior art keywords
deposition
membrane
substrate
deposition mask
opening
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PCT/JP2024/040446
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English (en)
French (fr)
Japanese (ja)
Inventor
葵 佐野
数馬 碓氷
浩之 道
涼真 茂木
昭彦 小林
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Toppan Holdings Inc
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Toppan Holdings Inc
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Priority to CN202480035638.0A priority Critical patent/CN121263547A/zh
Priority to KR1020267006944A priority patent/KR20260046210A/ko
Priority to JP2025518929A priority patent/JP7831694B2/ja
Publication of WO2025105425A1 publication Critical patent/WO2025105425A1/ja
Anticipated expiration legal-status Critical
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/10—Apparatus or processes specially adapted to the manufacture of electroluminescent light sources
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering

Definitions

  • the present invention relates to a deposition mask and a method for manufacturing an electronic device.
  • deposition masks are known that are used to paint three colors, RGB, when making organic electroluminescence displays.
  • Patent Documents 1 and 2 disclose a deposition mask having a first layer (outer frame substrate) and a second layer (mask substrate). A plurality of openings are formed in the second layer (mask substrate).
  • the first layer (outer frame substrate) is a substrate that supports the second layer (mask substrate).
  • Patent Documents 1 and 2 do not solve the above problems by improving the shape of the first layer (outer frame substrate).
  • the present invention aims to provide a deposition mask that suppresses the occurrence of damage and a method for manufacturing electronic devices using the deposition mask.
  • the deposition mask of this embodiment is a deposition mask that is disposed between a substrate to be deposited and a deposition source, and is used to deposit a deposition material from the deposition source onto the surface of the substrate to be deposited through an opening, and is characterized in that it comprises a membrane having an opening region with a plurality of the openings and a peripheral region located around the opening region, and a support substrate that supports the membrane in the peripheral region, and the side surface of the support substrate includes a tapered surface that has a taper angle of less than 80° between the surface supporting the membrane and a parallel surface.
  • the present invention can reduce damage caused by handling, cleaning, etc. during the deposition mask manufacturing process, thereby increasing yield.
  • FIG. 2 is a cross-sectional view showing an example of a deposition mask according to the present embodiment.
  • FIG. 2 is a cross-sectional view showing an example of a deposition mask different from that shown in FIG. 1 .
  • FIG. 2 is a partially enlarged cross-sectional view of a support substrate of the deposition mask.
  • 1A to 1C are cross-sectional views showing a method for manufacturing an electronic device using the deposition mask of the present embodiment.
  • 1A to 1C are process diagrams illustrating an example of a method for manufacturing a deposition mask according to an embodiment of the present invention.
  • 1A to 1C are process diagrams illustrating an example of a method for manufacturing a deposition mask according to an embodiment of the present invention.
  • FIG. 1C are process diagrams illustrating an example of a method for manufacturing a deposition mask according to an embodiment of the present invention.
  • FIG. 11 is a cross-sectional view illustrating an example of a deposition mask according to another embodiment.
  • FIG. 11 is a cross-sectional view illustrating an example of a deposition mask according to another embodiment.
  • FIG. 11 is a cross-sectional view illustrating an example of a deposition mask according to another embodiment.
  • FIG. 11 is a cross-sectional view illustrating an example of a deposition mask according to another embodiment.
  • FIG. 1 is a plan view of a mask of an experimental example.
  • 1A is an SEM photograph showing a supporting substrate used in the experiment
  • FIG. 1B is a schematic diagram of FIG. 1A is an SEM photograph showing a supporting substrate used in the experiment
  • FIG. 1B is a schematic diagram of FIG.
  • FIG. 1A is a partially enlarged plan view of the deposition mask used in the experiment
  • FIG. 1B is a partially cross-sectional view of the deposition mask
  • FIG. 1C is a schematic perspective view showing an enlarged view of the vicinity of a support substrate of the membrane.
  • VR/AR Virtual reality/augmented reality
  • PPI Pixels Per Inch
  • OLED silicon-based organic light-emitting diode
  • Silicon-based OLED microdisplay technology is expected to achieve further miniaturization and high PPI. Furthermore, to effectively prepare for AR and VR as high-value-added industries, it is expected to realize ultra-high resolution displays of, for example, 1000 ppi or more. As a result, there is a growing need for deposition masks for RGB color separation used in the manufacturing process of OLED microdisplays.
  • the inventors have developed a deposition mask that can prevent damage by optimizing the shape of the support substrate that supports the membrane.
  • FIG. 1 is a cross-sectional view of a deposition mask 1 in the present embodiment.
  • the deposition mask 1 has a laminated structure of a membrane 2 and a support substrate 4.
  • the support substrate 4 is preferably configured by an SOI (Silicon on Insulator) substrate 9 including an insulating layer 3 and a silicon substrate 30.
  • the deposition mask 1 shown in FIG. 1 is configured by an SOI substrate 9 including a membrane 1, an insulating layer 3, and a support substrate 4 (in this case, the support substrate 4 does not include the insulating layer 3).
  • the support substrate 4 is, for example, a silicon substrate, but is not limited thereto.
  • the embodiments of FIGS. 8 to 10 described later are illustrated as a support substrate 4/insulating layer 3/membrane 2.
  • the membrane 2 is preferably a silicon single crystal layer, also called a semiconductor layer or an active layer.
  • the deposition mask 1 has multiple opening regions 15 and surrounding regions 16 located around the opening regions 15, and the surrounding regions 16 have a structure in which the membrane 2 and the support substrate 4 are laminated. Meanwhile, only the membrane 2 is disposed in the opening regions 15, that is, the support substrate 4 is removed, and multiple minute openings 5 are formed in each opening region 15.
  • the membrane 2 has a front surface 2a and a back surface 2b that face each other in the thickness direction.
  • a support substrate 4 is provided on the back surface 2b side.
  • the front surface 2 a is the front surface facing the deposition substrate 10
  • the back surface 2 b is the back surface facing the deposition source 11 .
  • the membrane 2 has a plurality of openings 5 formed between the front surface 2a and the back surface 2b.
  • the opening width of each opening 5 gradually narrows from the back surface 2b to the front surface 2a. Therefore, the side wall surface 5a of the opening 5 is inclined.
  • the opening width W1 is defined as the width dimension in the surface direction along the front surface 2a.
  • the opening width W1 is illustrated at the location where the width dimension is narrowest.
  • the symbols for the opening width W1 and the side wall surface 5a are illustrated for only one opening 5, but they are similarly applied to the other openings 5.
  • the distance between adjacent openings 5 is defined as the opening spacing dimension W2.
  • the opening spacing dimension W2 is defined as the dimension along the front surface 2a.
  • the opening width W1 is approximately 1 ⁇ m to 20 ⁇ m, preferably 3 ⁇ m to 15 ⁇ m, and more preferably 5 ⁇ m to 10 ⁇ m.
  • the opening spacing dimension W2 is approximately 1 ⁇ m to 20 ⁇ m, preferably 1 ⁇ m to 15 ⁇ m, and more preferably 3 ⁇ m to 10 ⁇ m.
  • the planar pattern of the openings 5 (the shape seen from directly above the membrane 2 toward the surface 2a) is not limited, but examples include rectangles (including squares), polygons other than rectangles, circles, and ellipses. All the openings 5 may have the same planar pattern, or some may have different patterns. The openings 5 may be regularly arranged, irregularly arranged, or a mixture of regular and irregular arrangements.
  • the outer peripheral shape of the membrane 2 is preferably a rectangular or disk-shaped wafer, and although there are no limitations on the diameter (the length of one side if rectangular), it is preferable for it to be approximately 100 mm to 500 mm. In this way, even if the diameter of the membrane 2 is large, each opening 5 can be formed uniformly.
  • the insulating layer 3 may be an oxide layer or a nitride layer, but is preferably an oxide layer, and more specifically, is preferably a silicon oxide (SiO 2 ) layer.
  • the insulating layer 3 is also called a BOX layer (Buried Oxide Layer).
  • the thickness of the insulating layer 3 is not limited, but is, for example, about 100 nm to 20 ⁇ m.
  • the insulating layer 3 shown in FIG. 1 is not provided in the opening area facing the opening 5 of the membrane 2, but has been removed, and is left only in the surrounding area of the opening area on the back surface 2b of the membrane 2.
  • the insulating layer 3 serves as an etching stopper for the membrane 2, and the presence of the insulating layer 3 enables stable processing.
  • the support substrate 4 including the insulating layer 3 and the silicon substrate 30 can function as the columnar portions 16a and the peripheral frame 16b constituting the peripheral region 16 of the opening region 15 on the rear surface 2b of the membrane 2. Therefore, the membrane 2 can be kept in a taut state by the support substrate 4, making tensioning unnecessary, and the deposition mask 1 of this embodiment can be adhered to the deposition substrate 10 using an electrostatic chuck that utilizes electrostatic force.
  • the columnar portions 16a are located inside the peripheral frame 16b, and they are all the same height, but for example, the height of the columnar portions 16a may be lower than the peripheral frame 16b. However, by making the heights uniform, strength can be maintained.
  • an alignment mark for positioning can be formed in the peripheral region on the surface 2a side of the membrane 2.
  • the alignment mark can be formed, for example, in a concave shape on the surface 2a, and can be formed to a depth that reaches the insulating layer 3.
  • the support substrate 4 has a first surface 4a facing the membrane 2 and a second surface 4b opposite to the first surface 4a.
  • the first surface 4a is a surface closer to the deposition substrate 10 shown in Fig. 4
  • the second surface 4b is a surface closer to the deposition source 11 shown in Fig. 4.
  • the side surface 4e is inclined so that the width of the support substrate 4 gradually increases from the second surface 4b toward the first surface 4a of the support substrate 4.
  • the taper angle ⁇ of the side surface 4e is defined as the angle between the surface supporting the membrane 2 and a parallel surface.
  • the "surface supporting the membrane 2" is the back surface 2b of the membrane 2 and the first surface 4a of the support substrate 4, and in FIG. 1, the boundary surface between the silicon substrate 30 and the insulating layer 3 (referred to as the "third surface 4f") is used as the "parallel surface”.
  • the "parallel surface” may be other than the third surface 4f, for example, the first surface 4a, but it is preferable to use a surface that is easy to measure the taper angle ⁇ .
  • the insulating layer 3 constituting the support substrate 4 is extremely thin compared to the silicon substrate 30, it is preferable to use the side surface 4e of the silicon substrate 30, which can be clearly identified in a SEM photograph, for measuring the taper angle ⁇ . Therefore, as shown in FIG. 1, defining the taper angle ⁇ as the angle between the third surface 4f of the silicon substrate 30 and the side surface 4e of the silicon substrate 30 can lead to a more accurate angle.
  • the taper angle ⁇ of the side surface 4e is less than 80°. If the taper angle ⁇ of the side surface 4e is 80° or more, the area receiving the water pressure during the oscillation is smaller than when the taper angle ⁇ of the side surface 4e is less than 80° when the mask is oscillated (up and down three times) in the cleaning process described below, and the load per unit area is larger. As a result, the load applied to the edge portion 4c of the first surface 4a of the support substrate 4 is large, making the membrane 2 more likely to be damaged.
  • the taper angle ⁇ is preferably 70° or less, more preferably 60° or less, even more preferably 50° or less, even more preferably 40° or less, and even more preferably 30° or less. There is no restriction on the lower limit of the taper angle ⁇ , but it is preferable that it is, for example, 5° or more, or 10° or more.
  • the entire side surface 4e has a taper angle ⁇ of less than 80°, but a portion of the side surface may have a different angle.
  • the side surface may be a vertical surface or may be an inversely tapered surface.
  • the concentration of force applied to the membrane 2 can be alleviated (dispersed) when handling the support substrate 4 as a frame or during the cleaning process.
  • damage such as cracks between the openings 5 of the membrane 2 can be suppressed, and the yield can be increased.
  • FIG. 2 is a cross-sectional view showing an example of a deposition mask different from that shown in FIG. 1.
  • FIG. 3 is a partially enlarged cross-sectional view showing the support substrate of the deposition mask.
  • the side surface 4e of the support substrate 4 is inclined at a generally constant taper angle ⁇ from the second surface 4b to the first surface 4a, but in FIG. 2, the side surface 4e is formed by a first taper surface 6 and a second taper surface 7. As shown in FIG. 2, the first taper surface 6 and the second taper surface 7 have different taper angles between the first surface 4a and the side surface 4e.
  • the first taper angle of the first taper surface 6 is indicated by ⁇ 1
  • the second taper angle of the second taper surface 7 is indicated by ⁇ 2.
  • the taper angle ⁇ 1 is greater than the taper angle ⁇ 2.
  • the second taper surface 7, which has a smaller taper angle ⁇ 2, is formed on the side closer to the membrane 2 than the first taper surface 6 (the side in contact with the insulating layer 3).
  • the first taper angle ⁇ 1 is approximately 90°, and therefore the first taper surface 6 is an approximately vertical surface.
  • the first taper surface 6 may be referred to as the "vertical surface 6."
  • the word “approximately” includes an error of 5% or less.
  • the first taper angle ⁇ 1 does not have to be approximately 90°, but it is preferably approximately 90° or close to it.
  • the second taper angle ⁇ 2 is preferably less than 80°, more preferably 70° or less, even more preferably 60° or less, even more preferably 50° or less, even more preferably 40° or less, and even more preferably 30° or less.
  • FIG. 14(a) shows a partially enlarged plan view of the deposition mask 1 used in the experiment described below, and FIG. 14(a) shows cells 8 arranged in a matrix. A large number of openings 5 are formed in the cell 8 in the vertical and horizontal directions (XY directions). Note that in FIG. 14(a), only one cell 8 and opening 5 are given a reference number as a representative. A columnar portion 16a (see also FIG. 1 and FIG. 2) of the support substrate 4 is arranged on the back side between the cells 8.
  • FIG. 14(b) is a partial cross-sectional view showing one cell 8 shown in FIG. 14(a).
  • Narrowing the spacing between cells 8 means narrowing the width of the columnar portion 16a of the support substrate 4.
  • Figure 1 if one tries to configure a single-stage taper surface ( Figure 1), it is not possible to form a very gentle slope. Therefore, by forming the first taper surface on the side away from the membrane 2 as a vertical surface 6 or a taper surface with a high taper angle close to that, and by making the second taper angle ⁇ 2 of the second taper surface 7 on the side closer to the membrane 2 smaller, it is possible to narrow the spacing between cells 8 while improving the damage suppression effect.
  • FIG. 3(a) is a partially enlarged schematic diagram showing a portion of the support substrate 4 in this embodiment.
  • the side surface 4e of the support substrate 4 is composed of a first tapered surface 6 and a second tapered surface 7 with different taper angles, with the first tapered surface (vertical surface) 6 with a high taper angle being on the side away from the membrane 2, and the second tapered surface 7 with a low taper angle being formed on the side closer to the membrane 2.
  • the vertical surface 6 and the second tapered surface 7 are formed continuously.
  • the height dimension of second tapered surface 7 is defined as the height dimension t2 of vertical surface v drawn vertically from inflection point p between first tapered surface 6 and second tapered surface 7 to first surface 4a.
  • the protruding width of the second tapered surface from vertical surface v is defined as w.
  • t2/t1 is 0.3 or more and less than 0.85. It is also preferable that w/t2 is 0.4 or more and 1.4 or less. This increases the strength of the support substrate 4 regardless of the height dimension t1 of the support substrate 4, while also ensuring a contact area with the membrane 2, thereby improving the damage prevention effect.
  • the side surface 4e is composed of three or more tapered surfaces, the tapered surface that is the subject of t2/t1 and w/t2 is the tapered surface closest to the membrane 2.
  • the side surface 4e of the support substrate 4 shown in FIG. 3(b) is also formed by a first tapered surface (vertical surface) 6 and a second tapered surface 17, similar to FIG. 3(a), but unlike FIG. 3(b), the second tapered surface 17 is formed in a concave shape rather than a straight shape. In this way, by forming the second tapered surface 17 in a concave shape, the second taper angle ⁇ 2 can be made smaller, that is, the second tapered surface 7 can be formed in a more gentle shape.
  • the second taper angle ⁇ 2 of the second tapered surface 17 can be determined by drawing a tangent line L that contacts the second tapered surface 17 from the edge 4c of the first surface 4a, and determining the second taper angle ⁇ 2 as the angle between the first surface 4a and the tangent line L.
  • the second taper angle ⁇ 2 of the second tapered surface 17 formed by a concave surface is 50° or less, preferably 30° or less, and more preferably 10° or less.
  • the first surface 4a is used as the reference surface for the height dimensions t1, t2, and protrusion width w, but the height dimensions t1, t2, and protrusion width w can be measured using the third surface 4f (see FIG. 2, etc.) of the silicon substrate 30 as the reference surface.
  • the second taper angle ⁇ 2 is preferably measured excluding the insulating layer 3, since it may be clearer and easier to measure it on the side of the silicon substrate 30. Since the thickness of the insulating layer 3 is extremely thin, there is no change in the numerical ranges described above even if t2/t1 and w/t2 are measured only on the silicon substrate 30 excluding the insulating layer 3.
  • the distance D between the edge 4c of the first surface 4a of the support substrate 4 on the membrane 2 side and the opening 5 of the membrane 2 closest to the edge 4c is 30 ⁇ m or more and 100 ⁇ m or less.
  • This distance D is the distance in the horizontal direction (the surface direction parallel to the first surface 4a).
  • the distance D is set to 30 ⁇ m or more and 100 ⁇ m or less.
  • the side surface 4e of the support substrate 4 it is sufficient for the side surface 4e of the support substrate 4 to have an inclined tapered surface, and the taper angle is not limited, but as described in Figures 1 and 2, it is preferably less than 80°, more preferably 70° or less, even more preferably 60° or less, even more preferably 50° or less, even more preferably 40° or less, and even more preferably 30° or less.
  • the following inventions can exist independently.
  • the side surface 4e of the support substrate 4 has at least a first tapered surface 6 and a second tapered surface 7 that have different taper angles between the surface supporting the membrane 2 and a surface parallel to the surface, the second tapered surface 7 has a smaller taper angle than the first tapered surface 6 and is formed on the side closer to the membrane 2, and the taper angle ⁇ 2 of the second tapered surface is less than 80° (see Figures 2 and 3).
  • the side surface 4e of the support substrate 4 has at least a first tapered surface 6 and a second tapered surface 7 that have different taper angles between the surface supporting the membrane 2 and a surface parallel to the surface, and the second tapered surface 7 is formed closer to the membrane 2 than the first tapered surface 6, and when the height dimension of the support substrate 4 is t1, the height dimension of the second tapered surface 7 is t2, and the protruding width of the second tapered surface 7 is w, t2/t1 is 0.3 or more and less than 0.85, and w/t2 is 0.4 or more and 1.4 or less (see Figure 3).
  • inventions (1) to (4) may be combined in multiple ways.
  • invention (2) may be combined with invention (3), or invention (1) may be combined with invention (4).
  • the side wall surface 5a of the plurality of openings 5 formed in the membrane 2 is inclined, and the taper angle of the side wall surface 5a is ⁇ 3.
  • the taper angle ⁇ 3 of the opening 5 is defined as the angle between the surface 2a (the surface facing the deposition substrate) of the opening 5 and the side wall surface 5a.
  • This taper angle ⁇ 3 is different from the taper angle ⁇ of the side surface 4e of the support substrate 4.
  • the taper angle of the support substrate 4 to be compared with the taper angle ⁇ 3 is compared with the taper angle ⁇ 2 of the taper surface closest to the membrane 2 (the second taper surface 7, 17 in Figs. 2 and 3) when the side surface 4e is formed of a plurality of taper surfaces as shown in Figs. 2 and 3.
  • the taper angle ⁇ 3 of the opening 5 of the membrane 2 is greater than the taper angles ⁇ and ⁇ 2 of the side surface 4e of the support substrate 4.
  • the opening pitch is narrow, and there is a restriction that the taper angle ⁇ 3 cannot be made small.
  • the taper angle ⁇ 3 of the opening 5 is in the range of 80° or more and less than 90°.
  • the taper angles ⁇ and ⁇ 2 of the side surface 4e of the support substrate 4 are preferably small to enhance the damage suppression effect, and it is desirable to control the taper angles ⁇ and ⁇ 2 so that they are smaller than the taper angle ⁇ 3.
  • the membrane 2 and the support substrate 4 have different thickness dimensions. Specifically, the membrane 2 is thinner than the support substrate 4. There is no upper limit to the thickness of the membrane 2, but it is 10 ⁇ m or less, and preferably 5 ⁇ m or less. A thin thickness increases deposition efficiency and makes it easier to achieve high definition. There is no lower limit to the thickness of the membrane 2, but it is preferably 1 ⁇ m or more from the standpoint of processability, durability, etc.
  • the thickness of the support substrate 4 (corresponding to the height dimension t1 shown in FIG. 3(a)) is, for example, about 100 ⁇ m to 1000 ⁇ m.
  • the silicon substrate 30 accounts for the majority of the support substrate 4, with the silicon substrate 30 accounting for approximately 80% or more of the height dimension t1, preferably approximately 90% or more, more preferably approximately 95% or more, and even more preferably 99% or more.
  • the thickness of the membrane 2 is thin.
  • the thickness of the support substrate 4 is thick. Therefore, it is preferable to control the thickness of the support substrate 4 so that it is greater than the thickness of the membrane 2.
  • the membrane 2 is thin, but the thinner it is, the more susceptible it is to breakage. If the thickness of the membrane 2 is 5 ⁇ m or less, the effect of breakage is particularly large, so it is preferable to increase the breakage prevention effect by making the taper angle ⁇ of the side surface 4 e of the support substrate 4 as small as possible, or by forming the side surface 4 e shown in FIG. 3(a) with multiple taper surfaces with different taper angles, or by forming the taper surface as a concave surface as shown in FIG. 3(b).
  • FIG. 5 is a process diagram showing a first manufacturing method of the deposition mask 1 of the present embodiment.
  • the deposition mask 1 in the manufacturing process shown in FIG. 5 and FIG. 6 described later shows only one opening region 15 and its vicinity, but in reality, the multiple opening regions 15 shown in FIG. 1 are formed simultaneously.
  • FIG. 5(a) an SOI substrate 9 is prepared.
  • the SOI substrate 9 has a laminated structure of a membrane 2, an insulating layer 3, and a silicon substrate 30 (the insulating layer 3 and the silicon substrate 30 together constitute the support substrate 4).
  • the material and thickness of each layer have been described in FIG. 1, so please refer to that description.
  • the diameter is not limited, but in this embodiment, it can accommodate up to about 500 mm.
  • a mask layer 14 is patterned on the surface of the membrane 2.
  • the mask layer 14 is preferably a resist, and can be patterned by exposure and development.
  • a plurality of through holes 14a are formed in the mask layer 14.
  • the through holes 14a are an opening pattern for forming the openings 5 in the membrane 2.
  • the membrane 2 exposed from the through-holes 14a of the mask layer 14 is dry-etched.
  • the membrane 2 is deep-etched. It is preferable to use a method in which, for example, etching of Si with SF6 and generation of a polymer film with C4F8 are repeated in the so-called Bosch process to deeply etch silicon, and sidewall protection and bottom etching are alternately performed.
  • the composition of the etching gas, the flow rate, the pressure inside the etching chamber, the power of the high frequency power source, etc. are appropriately adjusted so as to form an inverted tapered surface as shown in FIG. 5(c).
  • the Bosch process was carried out in a dry etching apparatus by alternately using SF6 gas and C4F8 gas .
  • Anisotropic dry etching using fluorine ions was carried out by applying a bias to the substrate to be etched using the same gas as that used in the mode in which isotropic dry etching using fluorine radicals is carried out using SF6 gas.
  • the processing conditions were SF6 gas at 0 to 500 sccm, C4F8 gas at 0 to 300 sccm, Platen LF at 0 to 1500 W, Coil RF at 300 to 1500 W, and chamber pressure at 1 to 10 Pa, and various conditions were adjusted.
  • a plurality of openings 5 can be deeply formed in the membrane 2, and at this time, the taper angle ⁇ 3 of the side wall surface 5a of the openings 5 can be appropriately adjusted. 5D, the mask layer 14 is removed, thereby completing the SOI substrate 9 having the membrane 2 with the multiple openings 5 formed therein.
  • a protective layer 20 is formed on the surface of the membrane 2. This allows the entire surface of the membrane 2 to be appropriately protected.
  • the protective layer 20 is, for example, a resist film.
  • a mask layer 21 is formed on the surface of the silicon substrate 30, which corresponds to the back surface of the SOI substrate 9.
  • the mask layer 21 is a resist pattern.
  • the mask layer 21 is not formed in the opening region 15 that faces the opening 5 formed in the membrane 2 in the thickness direction, but is provided only in the surrounding region 16 (see also FIG. 1).
  • the mask layer 21 may be formed together with the mask layer 14 during the process shown in FIG. 5(b).
  • the silicon substrate 30 that is not covered by the mask layer 21 is removed by, for example, dry etching, and in the process shown in FIG. 5(h), the insulating layer 3 that appears after removing the silicon substrate 30 is removed by wet etching. At this time, the membrane 2 is not affected by the wet etching and maintains its shape with multiple openings 5.
  • FIG. 6 is a process diagram showing a second manufacturing method of the deposition mask 1 of this embodiment.
  • an SOI substrate 9 is prepared.
  • the SOI substrate 9 has a layered structure of a membrane 2, an insulating layer 3, and a silicon substrate 30.
  • the material and thickness of each layer are explained in FIG. 1, so please refer to that.
  • the diameter of the SOI substrate 9 there is no limit to the diameter of the SOI substrate 9, but in this embodiment, it can accommodate a diameter of up to approximately 500 mm.
  • a mask layer 21 is formed on the surface of the silicon substrate 30, which corresponds to the back surface of the SOI substrate 9.
  • the mask layer 21 is a resist pattern.
  • the mask layer 21 is provided only in the peripheral region of the SOI substrate 9.
  • the silicon substrate 30 that is not covered by the mask layer 21 is removed by, for example, dry etching, and in the process shown in FIG. 6(d), the insulating layer 3 that is revealed by removing the silicon substrate 30 is removed by wet etching.
  • a mask layer 22 is formed on the back surface of the membrane 2.
  • the mask layer 22 can be formed with a resist pattern.
  • a pattern of a plurality of openings 22a is formed in the mask layer 22 by exposure and development.
  • the membrane 2 exposed from the opening 22a is etched.
  • This etching is dry etching, and although not limited thereto, it is preferable to use an etching gas that contains a fluorine compound and oxygen, and optionally a rare gas.
  • the fluorine compound may be, for example, one or more selected from CF 4 , SF 6 , NF 3 , BF 3 , PF 5 , and F 2
  • the rare gas may be, for example, one or more selected from helium and argon.
  • etching was performed using CF4 gas, O2 gas, and Ar gas in a dry etching apparatus.
  • the processing conditions were CF4 gas at 10 to 100 sccm, O2 gas at 0 to 100 sccm, Ar gas at 0 to 200 sccm, IPC power at 200 to 1000 W, RIE power at 0 to 1000 W, and chamber pressure at 1 to 10 Pa, and various conditions were adjusted.
  • an opening 5 is formed in the membrane 2, the width of which gradually decreases as it moves away from the mask layer 22 (towards the surface 2a of the membrane 2). This allows the side wall surface 5a of the opening 5 to be formed as a tapered surface. Then, in the step of FIG. 6(g), the mask layer 22 is removed. This completes the deposition mask 1.
  • the method for forming the side surface 4e of the silicon substrate 30 constituting the support substrate 4 as a tapered surface is not limited, but for example, etching was performed using CF4 gas, O2 gas, and Ar gas in a dry etching device.
  • the fluorine compound can be one or more selected from CF4 , SF6 , NF3 , BF3 , PF5 , and F2
  • the rare gas can be one or more selected from helium and argon.
  • the processing conditions were adjusted to CF4 gas at 10 to 100 sccm, O2 gas at 0 to 100 sccm, Ar gas at 0 to 200 sccm, IPC power at 200 to 1000 W, RIE power at 0 to 1000 W, and chamber pressure at 1 to 10 Pa. This allows the side surface 4e of the silicon substrate 30 to be formed as a tapered surface.
  • a Bosch process was performed using alternately SF6 gas and C4F8 gas in a dry etching apparatus.
  • Anisotropic dry etching using fluorine ions was performed by applying a bias to the substrate to be etched using the same gas as that used in the mode in which isotropic dry etching using fluorine radicals was performed using SF6 gas.
  • the processing conditions were SF6 gas at 0 to 500 sccm, C4F8 gas at 0 to 300 sccm , Platen LF at 0 to 1500 W, Coil RF at 300 to 1500 W, and chamber pressure at 1 to 10 Pa, and various conditions were adjusted.
  • the above vertical process may be combined with a wet etching process.
  • etching processes for example, a mixture of hydrofluoric acid, nitric acid, and acetic acid, electrolytic etching using hydrofluoric acid, and crystal anisotropic etching using potassium hydroxide and TMAH were selected and processed to obtain the desired angle.
  • a mixture of hydrofluoric acid, nitric acid, and acetic acid was used for processing, and the processing temperature was set to 20°C to 40°C.
  • the side surface 4e of the support substrate 4 can be formed with multiple tapered surfaces with different taper angles by combining the above-mentioned dry etching process with a wet etching process, or by changing the etching conditions during the dry etching process.
  • the side of the remaining insulating layer 3 is also likely to be formed following the taper angle of the silicon substrate 30, but depending on the conditions, the side of the insulating layer 3 may be formed as a nearly vertical surface or an inversely tapered surface. Also, since the insulating layer 3 is extremely thin compared to the silicon substrate 30, it may be difficult to determine the side of the insulating layer 3. Therefore, it is preferable to measure the taper angles ⁇ and ⁇ 2 of the side 4e of the support substrate 4 using the angle of the side 4e of the silicon substrate 30, as shown in FIG. 1 and FIG. 2.
  • the manufacturing method of this embodiment allows the taper angles ⁇ and ⁇ 2 of the side surface 4e of the support substrate 4 to be adjusted to less than 80°.
  • the height dimension drawn vertically from the second surface 4b of the support substrate 4 toward the first surface 4a is t1
  • the height dimension of the second tapered surface 7 is t2
  • the protruding width of the second tapered surface 7 is w
  • the distance D between the edge 4c of the first surface 4a of the support substrate 4 and the opening 5 closest to the support substrate 4 is 30 ⁇ m or more and 100 ⁇ m or less.
  • the deposition mask 1 is placed between the deposition substrate 10 and the deposition source 11. At this time, the front surface 2a of the membrane 2 of the deposition mask 1 faces the deposition substrate 10, and the back surface 2b of the membrane 2 faces the deposition source 11. A plurality of openings 5 are formed in the membrane 2, and the opening width is narrower on the deposition substrate 10 side than on the deposition source 11 side.
  • the deposition mask 1 is placed in a holder (not shown) of the deposition device, and the deposition mask 1 and the deposition substrate 10 can be fixed with an electrostatic chuck.
  • the deposition mask 1 and the deposition substrate 10 are rotated around the axial center of the holder as the rotation axis.
  • the deposition material (deposition particles) 12 from the deposition source 11 passes through the openings 5 in the deposition mask 1 and reaches the surface 10a of the deposition substrate 10, forming a deposition film 13.
  • examples of electronic devices include OLED microdisplay panels, liquid crystal panels, solar cells, etc.
  • the present invention is particularly suitable for a manufacturing method for an OLED microdisplay panel as an organic electronic device.
  • the present invention is not limited to the above-mentioned embodiments and modifications, and may be modified, substituted, or altered in various ways without departing from the spirit of the technical idea. Furthermore, if the technical idea can be realized in a different way due to technological advances or derived other technologies, it may be implemented using that method. Therefore, the claims cover all embodiments that may fall within the scope of the technical idea.
  • 1 is formed of an SOI substrate, but may be configured, for example, as shown in Fig. 7, by forming a membrane 31 of SiN, SiO2 , or the like on the surface of a frame-shaped silicon substrate 30, and forming a plurality of openings 32 in the membrane 31 in a central region from which the silicon substrate 30 has been removed.
  • the membrane is formed by CVD, but it is preferable to use SiN from the viewpoint of easy stress control.
  • the silicon substrate 30 shown in FIG. 7 constitutes the support substrate of this embodiment, and preferably has at least one of the above-mentioned inventions (1) to (4). This can enhance the damage prevention effect.
  • an SOI substrate 9 is used as in Figure 1, but in Figure 8, a SiN layer 33 is formed on the back side (support substrate 4 side, facing deposition source 11) of the SOI substrate 9, in Figure 9, a SiN layer 33 is formed on the front side (semiconductor layer 2 side, facing deposition substrate 10) of the SOI substrate 9, and in Figure 10, a SiN layer 33 is formed on both the back side and front side of the SOI substrate 9.
  • a SiN layer 33 is formed on the front side (semiconductor layer 2 side) of the SOI substrate 9
  • an opening 5 is formed in contiguous with the semiconductor layer 2 as shown in Figures 9 and 10.
  • the SiN layer 33 By providing the SiN layer 33, it becomes easier to control the stress of the deposition mask, and distortion and the like can be suppressed. Moreover, it is preferable that the SiN layer 33 formed on the front side of the SOI substrate 9 is thinner than the SiN layer 33 formed on the back side of the SOI substrate 9. Although not limited thereto, the thickness of the SiN layer 33 formed on the front side of the SOI substrate 9 is about 0.05 ⁇ m to 0.5 ⁇ m, and the thickness of the SiN layer 33 formed on the back side of the SOI substrate 9 is about 0.05 ⁇ m to 3 ⁇ m.
  • the SiN layer 33 formed on the front side of the SOI substrate 9 is formed thinner than the SiN layer 33 formed on the back side of the SOI substrate 9 in order to control the stress in a well-balanced manner between the front side and the back side.
  • At least one of the support substrate 4 and the membrane 2 may have a polycrystalline silicon structure. Since polycrystalline silicon does not have a clear cleavage plane, it is less likely to break in the cleavage direction than single crystal silicon having a cleavage plane. Although it is technically difficult to make a large substrate from a single crystal silicon material, by forming the deposition mask 1 with a polycrystalline silicon structure, it is possible to easily form a silicon substrate larger than a single crystal silicon substrate. By forming the deposition mask 1 with a polygonal (e.g., rectangular) planar shape, the chamfering efficiency can be improved and the number of faces can be increased, compared to a deposition mask 1 with a circular shape. Note that a large silicon substrate is preferably 500 mm x 500 mm or more.
  • the deposition mask used was an SOI substrate, and the SOI substrate used was a silicon substrate (675 ⁇ m)/insulating layer (0.5 ⁇ m)/membrane (4 ⁇ m).
  • the parentheses indicate thickness.
  • the membrane was a Si layer, and the insulating layer was a SiO 2 layer.
  • the silicon substrate and the insulating layer were combined to form a support substrate that supports the membrane.
  • the outer diameter of the SOI substrate was 200 mm.
  • the membrane multiple openings with an opening width of 5 to 10 ⁇ m were formed in each cell.
  • the side surface 4e of the support substrate 4 was formed with a single taper as shown in FIG. 1, or a two-step taper as shown in FIG. 3(a) or FIG. 3(b).
  • the taper angle was measured by SEM observation.
  • the device used for the measurement was a Hitachi High-Technologies SU3500.
  • FIG. 12(a) is an SEM photograph of the support substrate in Experimental Example 5, and FIG. 12(b) is a schematic diagram thereof.
  • the support substrate was formed with a two-stage inclination of a vertical surface and a tapered surface, and the tapered surface was concave.
  • the taper angle ⁇ 2 of the tapered surface was 10°.
  • FIG. 13(a) is an SEM photograph of the support substrate in Experimental Example 8
  • FIG. 13(b) is a schematic diagram thereof.
  • the support substrate was formed with a two-stage inclination of a vertical surface and a tapered surface, and the tapered surface was approximately linear.
  • the taper angle ⁇ 2 of the tapered surface was 60°.
  • the taper angle ⁇ 2 of the side surface of the silicon substrate was measured, as shown in FIG. 2.
  • the cleaning was performed by placing the deposition mask vertically (the direction perpendicular to the mask thickness direction was the up-down direction).
  • One cycle consisted of immersion in sulfuric acid, immersion in pure water, and rocking the mask (up-and-down three times), and this was repeated five times.
  • Experimental Examples 1 to 3 had a single-stage inclined shape as shown in Figure 1.
  • Experimental Example 4 the entire side surface of the support substrate was a vertical surface.
  • Experimental Examples 5 to 10 had a two-stage inclined shape as shown in Figures 3(a) and (b). All of these were a combination of a vertical surface and a tapered surface.
  • the preferred taper angle was set to less than 80°, and the more preferred taper angle was set to 70° or less.
  • the experimental example with a taper angle of 30° in Table 2 was produced by combining a dry etching process and a wet etching process so that the second taper angle ⁇ 2 shown in Figure 2 was a two-step shape with a second taper angle of 30°, and the experimental example with a taper angle of 60° in Table 2 was produced using only a dry etching process so that the inclined shape shown in Figure 1 was obtained.
  • distance D refers to the distance between edge 4c of first surface 4a of support substrate 4 on the membrane 2 side and opening 5 of membrane 2 that is closest to edge 4c.
  • Opening width W1 refers to the width dimension of opening 5 along surface 2a of membrane 2 as shown in FIG. 14(b).
  • opening spacing dimension W2 refers to the distance between openings on surface 2a of membrane 2.
  • the cleaning method was the same as in the experiment in Table 1, and cleaning was evaluated by observing cracks and damage occurring between the openings close to the support substrate at 40 locations after cleaning under a microscope and calculating the rate of damage occurrence.
  • the experimental results are shown in Table 2 below.
  • the distance D was 10 ⁇ m, and the breakage occurrence rate was higher than 10%, resulting in a rating of x. In other words, if the distance D is too close, breakage or cracks are more likely to occur due to effects such as cleaning during the manufacturing process.
  • the distance D is set to 30 ⁇ m or more and 100 ⁇ m or less. It was also found that the opening width is preferably about 5 to 10 ⁇ m, and the distance between the openings is preferably about 3 to 10 ⁇ m.

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PCT/JP2024/040446 2023-11-16 2024-11-14 蒸着マスク、及び電子デバイスの製造方法 Pending WO2025105425A1 (ja)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000133443A (ja) * 1998-10-23 2000-05-12 Nec Corp シャドウマスク及びその製造方法並びにシャドウマスクを用いた有機ｅｌディスプレイの製造方法
JP2006202548A (ja) * 2005-01-19 2006-08-03 Seiko Epson Corp マスク、及びマスクの製造方法
JP2009087840A (ja) * 2007-10-02 2009-04-23 Seiko Epson Corp 蒸着マスク、蒸着マスクの製造方法、有機ｅｌ素子、電子機器
WO2023145955A1 (ja) * 2022-01-31 2023-08-03 大日本印刷株式会社 マスク及びマスクの製造方法
JP2024014701A (ja) * 2022-07-22 2024-02-01 オラム マテリアル コーポレーション マスクと支持部との連結体及びその製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000133433A (ja) 1998-10-29 2000-05-12 Sharp Corp 高周波加熱装置
JP4092914B2 (ja) 2001-01-26 2008-05-28 セイコーエプソン株式会社 マスクの製造方法、有機エレクトロルミネッセンス装置の製造方法
CN108735915B (zh) 2017-04-14 2021-02-09 上海视涯技术有限公司 用于oled蒸镀的荫罩及其制作方法、oled面板的制作方法
JP2022175925A (ja) 2021-05-14 2022-11-25 キヤノン株式会社 蒸着マスク、及び、有機電子デバイスの製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000133443A (ja) * 1998-10-23 2000-05-12 Nec Corp シャドウマスク及びその製造方法並びにシャドウマスクを用いた有機ｅｌディスプレイの製造方法
JP2006202548A (ja) * 2005-01-19 2006-08-03 Seiko Epson Corp マスク、及びマスクの製造方法
JP2009087840A (ja) * 2007-10-02 2009-04-23 Seiko Epson Corp 蒸着マスク、蒸着マスクの製造方法、有機ｅｌ素子、電子機器
WO2023145955A1 (ja) * 2022-01-31 2023-08-03 大日本印刷株式会社 マスク及びマスクの製造方法
JP2024014701A (ja) * 2022-07-22 2024-02-01 オラム マテリアル コーポレーション マスクと支持部との連結体及びその製造方法

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